Lines Matching +full:interconnect +full:- +full:0
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/ti-sysc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Texas Instruments interconnect target module
10 - Tony Lindgren <tony@atomide.com>
13 Texas Instruments SoCs can have a generic interconnect target module
14 for devices connected to various interconnects such as L3 interconnect
15 using Arteris NoC, and L4 interconnect using Sonics s3220. This module
18 than that it is mostly independent of the interconnect.
20 Each interconnect target module can have one or more devices connected to
21 it. There is a set of control registers for managing the interconnect target
22 module clocks, idle modes and interconnect level resets.
24 The interconnect target module control registers are sprinkled into the
26 the interconnect target module. Typically the register names are REVISION,
31 pattern: "^target-module(@[0-9a-f]+)?$"
35 - items:
36 - enum:
37 - ti,sysc-omap2
38 - ti,sysc-omap4
39 - ti,sysc-omap4-simple
40 - ti,sysc-omap2-timer
41 - ti,sysc-omap4-timer
42 - ti,sysc-omap3430-sr
43 - ti,sysc-omap3630-sr
44 - ti,sysc-omap4-sr
45 - ti,sysc-omap3-sham
46 - ti,sysc-omap-aes
47 - ti,sysc-mcasp
48 - ti,sysc-dra7-mcasp
49 - ti,sysc-usb-host-fs
50 - ti,sysc-dra7-mcan
51 - ti,sysc-pruss
52 - const: ti,sysc
53 - items:
54 - const: ti,sysc
58 Interconnect target module control registers consisting of
64 reg-names:
66 Interconnect target module control register names consisting
69 - minItems: 1
71 - const: rev
72 - const: sysc
73 - const: syss
74 - items:
75 - const: rev
76 - const: syss
77 - enum: [ sysc, syss ]
79 power-domains:
92 clock-names:
97 - enum: [ ick, fck, sys_clk ]
98 - items:
99 - const: fck
100 - enum: [ ick, dbclk, osc, sys_clk, dss_clk, ahclkx ]
101 - items:
102 - const: fck
103 - const: phy-clk
104 - const: phy-clk-div
105 - items:
106 - const: fck
107 - const: hdmi_clk
108 - const: sys_clk
109 - const: tv_clk
110 - items:
111 - const: fck
112 - const: ahclkx
113 - const: ahclkr
122 reset-names:
127 - const: rstctrl
129 '#address-cells':
132 '#size-cells':
137 dma-ranges: true
139 ti,sysc-mask:
143 ti,sysc-midle:
145 $ref: /schemas/types.yaml#/definitions/uint32-array
147 ti,sysc-sidle:
149 $ref: /schemas/types.yaml#/definitions/uint32-array
151 ti,syss-mask:
155 ti,sysc-delay-us:
157 default: 0
158 minimum: 0
161 ti,no-reset-on-init:
162 description: Interconnect target module shall not be reset at init
165 ti,no-idle-on-init:
166 description: Interconnect target module shall not be idled at init
169 ti,no-idle:
170 description: Interconnect target module shall not be idled
174 description: Interconnect module name to use with legacy hwmod data
179 - compatible
180 - '#address-cells'
181 - '#size-cells'
182 - ranges
188 - |
189 #include <dt-bindings/bus/ti-sysc.h>
190 #include <dt-bindings/clock/omap4.h>
192 target-module@2b000 {
193 compatible = "ti,sysc-omap2", "ti,sysc";
195 reg = <0x2b400 0x4>,
196 <0x2b404 0x4>,
197 <0x2b408 0x4>;
198 reg-names = "rev", "sysc", "syss";
199 clocks = <&l3_init_clkctrl OMAP4_USB_OTG_HS_CLKCTRL 0>;
200 clock-names = "fck";
201 ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
204 ti,sysc-midle = <SYSC_IDLE_FORCE>,
207 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
211 ti,syss-mask = <1>;
212 #address-cells = <1>;
213 #size-cells = <1>;
214 ranges = <0 0x2b000 0x1000>;