Lines Matching +full:ssc +full:- +full:controller
1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/bus/qcom,ssc-block-bus.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: The AHB Bus Providing a Global View of the SSC Block on (some) qcom SoCs
10 - Michael Srba <Michael.Srba@seznam.cz>
20 The SSC (Snapdragon Sensor Core) block contains a gpio controller, i2c/spi/uart
21 controllers, a hexagon core, and a clock controller which provides clocks for
27 - const: qcom,msm8998-ssc-block-bus
28 - const: qcom,ssc-block-bus
32 - description: SSCAON_CONFIG0 registers
33 - description: SSCAON_CONFIG1 registers
35 reg-names:
37 - const: mpm_sscaon_config0
38 - const: mpm_sscaon_config1
40 '#address-cells':
43 '#size-cells':
51 clock-names:
53 - const: xo
54 - const: aggre2
55 - const: gcc_im_sleep
56 - const: aggre2_north
57 - const: ssc_xo
58 - const: ssc_ahbs
60 power-domains:
62 - description: CX power domain
63 - description: MX power domain
65 power-domain-names:
67 - const: ssc_cx
68 - const: ssc_mx
72 - description: Main reset
73 - description:
74 SSC Branch Control Register reset (associated with the ssc_xo and
77 reset-names:
79 - const: ssc_reset
80 - const: ssc_bcr
82 qcom,halt-regs:
83 $ref: /schemas/types.yaml#/definitions/phandle-array
84 description: describes how to locate the ssc AXI halt register
86 - items:
87 - description: Phandle reference to a syscon representing TCSR
88 - description: offset for the ssc AXI halt register
91 - compatible
92 - reg
93 - reg-names
94 - '#address-cells'
95 - '#size-cells'
96 - ranges
97 - clocks
98 - clock-names
99 - power-domains
100 - power-domain-names
101 - resets
102 - reset-names
103 - qcom,halt-regs
109 - |
110 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
111 #include <dt-bindings/clock/qcom,rpmcc.h>
112 #include <dt-bindings/power/qcom-rpmpd.h>
115 #address-cells = <1>;
116 #size-cells = <1>;
118 …// devices under this node are physically located in the SSC block, connected to an ssc-internal b…
120 #address-cells = <1>;
121 #size-cells = <1>;
124 compatible = "qcom,msm8998-ssc-block-bus", "qcom,ssc-block-bus";
126 reg-names = "mpm_sscaon_config0", "mpm_sscaon_config1";
134 clock-names = "xo", "aggre2", "gcc_im_sleep", "aggre2_north", "ssc_xo", "ssc_ahbs";
137 reset-names = "ssc_reset", "ssc_bcr";
139 power-domains = <&rpmpd MSM8998_SSCCX>, <&rpmpd MSM8998_SSCMX>;
140 power-domain-names = "ssc_cx", "ssc_mx";
142 qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;