Lines Matching +full:wait +full:- +full:on +full:- +full:read
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 external memory (such as NAND or other memory-mapped peripherals) whereas
16 data lines (16 bits), OE (output enable), ADV (address valid, used on some
17 NOR flash memories), WE (write enable). This on top of 6 different chip selects
20 Apparently this bus is clocked at 64MHz. It has dedicated pins on the package
21 and the bus can only come out on these pins, however if some of the pins are
25 Also CS1 and CS2 has -A and -B signals. Why they have that is unclear to me.
31 CS0 GPIO134 0x1a800000-0x1b000000 (8MB)
32 CS1 GPIO39 (A) / GPIO123 (B) 0x1b000000-0x1b800000 (8MB)
33 CS2 GPIO40 (A) / GPIO124 (B) 0x1b800000-0x1c000000 (8MB)
34 CS3 GPIO133 0x1d000000-0x25000000 (128 MB)
35 CS4 GPIO132 0x1c800000-0x1d000000 (8MB)
36 CS5 GPIO131 0x1c000000-0x1c800000 (8MB)
38 The APQ8060 Qualcomm Application Processor User Guide, 80-N7150-14 Rev. A,
44 this is something just used on the FAST chip selects and that the SLOW
58 - Bjorn Andersson <andersson@kernel.org>
63 - qcom,apq8060-ebi2
64 - qcom,msm8660-ebi2
68 - description: EBI2 config region
69 - description: XMEM config region
71 reg-names:
73 - const: ebi2
74 - const: xmem
80 - description: EBI_2X clock
81 - description: EBI clock
83 clock-names:
85 - const: ebi2x
86 - const: ebi2
88 '#address-cells':
91 '#size-cells':
95 - compatible
96 - reg
97 - reg-names
98 - ranges
99 - clocks
100 - clock-names
101 - '#address-cells'
102 - '#size-cells'
105 "^.*@[0-5],[0-9a-f]+$":
113 qcom,xmem-recovery-cycles:
117 is de-asserted, in order to avoid contention on the data bus.
119 CS or read followed by write on the same CS. Minimum value is
124 qcom,xmem-write-hold-cycles:
134 qcom,xmem-write-delta-cycles:
142 qcom,xmem-read-delta-cycles:
145 The initial latency for read cycles inserted for the first
146 read to a page or burst memory.
150 qcom,xmem-write-wait-cycles:
153 The number of wait cycles for every write access.
157 qcom,xmem-read-wait-cycles:
160 The number of wait cycles for every read access.
166 qcom,xmem-address-hold-enable:
173 qcom,xmem-adv-to-oe-recovery-cycles:
181 qcom,xmem-read-hold-cycles:
184 The length in cycles of the first segment of a read transfer.
185 For a single read transfer this will be the time from CS
191 - reg
196 - |
197 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
198 #include <dt-bindings/interrupt-controller/irq.h>
199 #include <dt-bindings/gpio/gpio.h>
201 external-bus@1a100000 {
202 compatible = "qcom,msm8660-ebi2";
204 reg-names = "ebi2", "xmem";
213 clock-names = "ebi2x", "ebi2";
215 #address-cells = <2>;
216 #size-cells = <1>;
222 interrupts-extended = <&pm8058_gpio 7 IRQ_TYPE_EDGE_FALLING>,
224 reset-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
226 phy-mode = "mii";
227 reg-io-width = <2>;
228 smsc,force-external-phy;
229 smsc,irq-push-pull;
232 qcom,xmem-recovery-cycles = <0>;
233 qcom,xmem-write-hold-cycles = <3>;
234 qcom,xmem-write-delta-cycles = <31>;
235 qcom,xmem-read-delta-cycles = <28>;
236 qcom,xmem-write-wait-cycles = <9>;
237 qcom,xmem-read-wait-cycles = <9>;