Lines Matching +full:interconnect +full:- +full:0

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/bus/baikal,bt1-axi.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Baikal-T1 AXI-bus
11   - Serge Semin <fancer.lancer@gmail.com>
14   AXI3-bus is the main communication bus of Baikal-T1 SoC connecting all
15   high-speed peripheral IP-cores with RAM controller and with MIPS P5600
16   cores. Traffic arbitration is done by means of DW AXI Interconnect (so
17   called AXI Main Interconnect) routing IO requests from one block to
22   (Errors Handler Block) embedded on top of the DW AXI Interconnect and
23   accessible by means of the Baikal-T1 System Controller.
26   - $ref: /schemas/simple-bus.yaml#
31       const: baikal,bt1-axi
36       - description: Synopsys DesignWare AXI Interconnect QoS registers
37       - description: AXI EHB MMIO system controller registers
39   reg-names:
42       - const: qos
43       - const: ehb
45   '#interconnect-cells':
50     description: Phandle to the Baikal-T1 System Controller DT node
57       - description: Main Interconnect uplink reference clock
59   clock-names:
61       - const: aclk
65       - description: Main Interconnect reset line
67   reset-names:
69       - const: arst
74   - compatible
75   - reg
76   - reg-names
77   - syscon
78   - interrupts
79   - clocks
80   - clock-names
83   - |
84     #include <dt-bindings/interrupt-controller/mips-gic.h>
87       compatible = "baikal,bt1-axi", "simple-bus";
88       reg = <0x1f05a000 0x1000>,
89             <0x1f04d110 0x8>;
90       reg-names = "qos", "ehb";
91       #address-cells = <1>;
92       #size-cells = <1>;
93       #interconnect-cells = <1>;
101       clocks = <&ccu_axi 0>;
102       clock-names = "aclk";
104       resets = <&ccu_axi 0>;
105       reset-names = "arst";