Lines Matching +full:cortex +full:- +full:a8
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Mark Rutland <mark.rutland@arm.com>
11 - Will Deacon <will.deacon@arm.com>
16 representation in the device tree should be done as under:-
21 - enum:
22 - apm,potenza-pmu
23 - apple,avalanche-pmu
24 - apple,blizzard-pmu
25 - apple,firestorm-pmu
26 - apple,icestorm-pmu
27 - arm,armv8-pmuv3 # Only for s/w models
28 - arm,arm1136-pmu
29 - arm,arm1176-pmu
30 - arm,arm11mpcore-pmu
31 - arm,cortex-a5-pmu
32 - arm,cortex-a7-pmu
33 - arm,cortex-a8-pmu
34 - arm,cortex-a9-pmu
35 - arm,cortex-a12-pmu
36 - arm,cortex-a15-pmu
37 - arm,cortex-a17-pmu
38 - arm,cortex-a32-pmu
39 - arm,cortex-a34-pmu
40 - arm,cortex-a35-pmu
41 - arm,cortex-a53-pmu
42 - arm,cortex-a55-pmu
43 - arm,cortex-a57-pmu
44 - arm,cortex-a65-pmu
45 - arm,cortex-a72-pmu
46 - arm,cortex-a73-pmu
47 - arm,cortex-a75-pmu
48 - arm,cortex-a76-pmu
49 - arm,cortex-a77-pmu
50 - arm,cortex-a78-pmu
51 - arm,cortex-a510-pmu
52 - arm,cortex-a520-pmu
53 - arm,cortex-a710-pmu
54 - arm,cortex-a715-pmu
55 - arm,cortex-a720-pmu
56 - arm,cortex-a725-pmu
57 - arm,cortex-x1-pmu
58 - arm,cortex-x2-pmu
59 - arm,cortex-x3-pmu
60 - arm,cortex-x4-pmu
61 - arm,cortex-x925-pmu
62 - arm,neoverse-e1-pmu
63 - arm,neoverse-n1-pmu
64 - arm,neoverse-n2-pmu
65 - arm,neoverse-n3-pmu
66 - arm,neoverse-v1-pmu
67 - arm,neoverse-v2-pmu
68 - arm,neoverse-v3-pmu
69 - arm,neoverse-v3ae-pmu
70 - brcm,vulcan-pmu
71 - cavium,thunder-pmu
72 - nvidia,denver-pmu
73 - nvidia,carmel-pmu
74 - qcom,krait-pmu
75 - qcom,scorpion-pmu
76 - qcom,scorpion-mp-pmu
80 description: 1 per-cpu interrupt (PPI) or 1 interrupt per core.
82 interrupt-affinity:
83 $ref: /schemas/types.yaml#/definitions/phandle-array
96 the interrupt-affinity property shouldn't be present).
101 qcom,no-pc-write:
106 secure-reg-access:
116 not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux
117 in Non-secure state.
120 - compatible