Lines Matching +full:mt8192 +full:- +full:power
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Eugen Hristev <eugen.hristev@collabora.com>
18 - items:
19 - enum:
20 - mediatek,mt2701-audsys
21 - mediatek,mt6765-audsys
22 - mediatek,mt6779-audsys
23 - mediatek,mt7622-audsys
24 - mediatek,mt8167-audsys
25 - mediatek,mt8173-audsys
26 - mediatek,mt8183-audsys
27 - mediatek,mt8186-audsys
28 - mediatek,mt8192-audsys
29 - mediatek,mt8516-audsys
30 - const: syscon
31 - items:
33 - const: mediatek,mt7623-audsys
34 - const: mediatek,mt2701-audsys
35 - const: syscon
40 '#clock-cells':
43 audio-controller:
44 $ref: /schemas/sound/mediatek,mt2701-audio.yaml#
48 - compatible
49 - '#clock-cells'
54 - |
55 #include <dt-bindings/interrupt-controller/arm-gic.h>
56 #include <dt-bindings/interrupt-controller/irq.h>
57 #include <dt-bindings/power/mt2701-power.h>
58 #include <dt-bindings/clock/mt2701-clk.h>
60 #address-cells = <2>;
61 #size-cells = <2>;
62 audsys: clock-controller@11220000 {
63 compatible = "mediatek,mt7622-audsys", "syscon";
65 #clock-cells = <1>;
67 afe: audio-controller {
68 compatible = "mediatek,mt2701-audio";
71 interrupt-names = "afe", "asys";
72 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
109 clock-names = "infra_sys_audio_clk",
144 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
148 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
150 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;