Lines Matching +full:armada +full:- +full:xp +full:- +full:cpu +full:- +full:clock
1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
14 "cpus" node, which in turn contains a number of subnodes (ie "cpu") defining
15 properties for every cpu.
17 Bindings for CPU nodes follow the Devicetree Specification, available from:
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
34 cpus and cpu node bindings definition
38 requires the cpus and cpu nodes to be present and contain the properties
53 Bits [11:0] in the reg cell must be set to bits [11:0] in CPU ID register.
57 On 32-bit ARM v7 or later systems this property is required and matches
58 the CPU MPIDR[23:0] register bits.
64 On ARM v8 64-bit systems this property is required and matches the
67 * If cpus node's #address-cells property is set to 2
75 * If cpus node's #address-cells property is set to 1
83 - apple,avalanche
84 - apple,blizzard
85 - apple,cyclone
86 - apple,firestorm
87 - apple,hurricane-zephyr
88 - apple,icestorm
89 - apple,mistral
90 - apple,monsoon
91 - apple,twister
92 - apple,typhoon
93 - arm,arm710t
94 - arm,arm720t
95 - arm,arm740t
96 - arm,arm7ej-s
97 - arm,arm7tdmi
98 - arm,arm7tdmi-s
99 - arm,arm9es
100 - arm,arm9ej-s
101 - arm,arm920t
102 - arm,arm922t
103 - arm,arm925
104 - arm,arm926e-s
105 - arm,arm926ej-s
106 - arm,arm940t
107 - arm,arm946e-s
108 - arm,arm966e-s
109 - arm,arm968e-s
110 - arm,arm9tdmi
111 - arm,arm1020e
112 - arm,arm1020t
113 - arm,arm1022e
114 - arm,arm1026ej-s
115 - arm,arm1136j-s
116 - arm,arm1136jf-s
117 - arm,arm1156t2-s
118 - arm,arm1156t2f-s
119 - arm,arm1176jzf
120 - arm,arm1176jz-s
121 - arm,arm1176jzf-s
122 - arm,arm11mpcore
123 - arm,armv8 # Only for s/w models
124 - arm,cortex-a5
125 - arm,cortex-a7
126 - arm,cortex-a8
127 - arm,cortex-a9
128 - arm,cortex-a12
129 - arm,cortex-a15
130 - arm,cortex-a17
131 - arm,cortex-a32
132 - arm,cortex-a34
133 - arm,cortex-a35
134 - arm,cortex-a53
135 - arm,cortex-a55
136 - arm,cortex-a57
137 - arm,cortex-a65
138 - arm,cortex-a72
139 - arm,cortex-a73
140 - arm,cortex-a75
141 - arm,cortex-a76
142 - arm,cortex-a77
143 - arm,cortex-a78
144 - arm,cortex-a78ae
145 - arm,cortex-a78c
146 - arm,cortex-a510
147 - arm,cortex-a520
148 - arm,cortex-a710
149 - arm,cortex-a715
150 - arm,cortex-a720
151 - arm,cortex-a725
152 - arm,cortex-m0
153 - arm,cortex-m0+
154 - arm,cortex-m1
155 - arm,cortex-m3
156 - arm,cortex-m4
157 - arm,cortex-r4
158 - arm,cortex-r5
159 - arm,cortex-r7
160 - arm,cortex-r52
161 - arm,cortex-x1
162 - arm,cortex-x1c
163 - arm,cortex-x2
164 - arm,cortex-x3
165 - arm,cortex-x4
166 - arm,cortex-x925
167 - arm,neoverse-e1
168 - arm,neoverse-n1
169 - arm,neoverse-n2
170 - arm,neoverse-n3
171 - arm,neoverse-v1
172 - arm,neoverse-v2
173 - arm,neoverse-v3
174 - arm,neoverse-v3ae
175 - arm,rainier
176 - brcm,brahma-b15
177 - brcm,brahma-b53
178 - brcm,vulcan
179 - cavium,thunder
180 - cavium,thunder2
181 - faraday,fa526
182 - intel,sa110
183 - intel,sa1100
184 - marvell,feroceon
185 - marvell,mohawk
186 - marvell,pj4a
187 - marvell,pj4b
188 - marvell,sheeva-v5
189 - marvell,sheeva-v7
190 - nvidia,tegra132-denver
191 - nvidia,tegra186-denver
192 - nvidia,tegra194-carmel
193 - qcom,krait
194 - qcom,kryo
195 - qcom,kryo240
196 - qcom,kryo250
197 - qcom,kryo260
198 - qcom,kryo280
199 - qcom,kryo360
200 - qcom,kryo385
201 - qcom,kryo465
202 - qcom,kryo468
203 - qcom,kryo470
204 - qcom,kryo485
205 - qcom,kryo560
206 - qcom,kryo570
207 - qcom,kryo660
208 - qcom,kryo670
209 - qcom,kryo685
210 - qcom,kryo780
211 - qcom,oryon
212 - qcom,scorpion
213 - samsung,mongoose-m2
214 - samsung,mongoose-m3
215 - samsung,mongoose-m5
217 enable-method:
220 # On ARM v8 64-bit this property is required
221 - enum:
222 - psci
223 - spin-table
224 # On ARM 32-bit systems this property is optional
225 - enum:
226 - actions,s500-smp
227 - allwinner,sun6i-a31
228 - allwinner,sun8i-a23
229 - allwinner,sun9i-a80-smp
230 - allwinner,sun8i-a83t-smp
231 - amlogic,meson8-smp
232 - amlogic,meson8b-smp
233 - arm,realview-smp
234 - aspeed,ast2600-smp
235 - brcm,bcm11351-cpu-method
236 - brcm,bcm23550
237 - brcm,bcm2836-smp
238 - brcm,bcm63138
239 - brcm,bcm-nsp-smp
240 - brcm,brahma-b15
241 - marvell,armada-375-smp
242 - marvell,armada-380-smp
243 - marvell,armada-390-smp
244 - marvell,armada-xp-smp
245 - marvell,98dx3236-smp
246 - marvell,mmp3-smp
247 - mediatek,mt6589-smp
248 - mediatek,mt81xx-tz-smp
249 - qcom,gcc-msm8660
250 - qcom,kpss-acc-v1
251 - qcom,kpss-acc-v2
252 - qcom,msm8226-smp
253 - qcom,msm8909-smp
254 # Only valid on ARM 32-bit, see above for ARM v8 64-bit
255 - qcom,msm8916-smp
256 - renesas,apmu
257 - renesas,r9a06g032-smp
258 - rockchip,rk3036-smp
259 - rockchip,rk3066-smp
260 - socionext,milbeaut-m10v-smp
261 - ste,dbx500-smp
262 - ti,am3352
263 - ti,am4372
265 cpu-release-addr:
267 - $ref: /schemas/types.yaml#/definitions/uint32
268 - $ref: /schemas/types.yaml#/definitions/uint64
270 The DT specification defines this as 64-bit always, but some 32-bit Arm
271 systems have used a 32-bit value which must be supported.
273 cpu-idle-states:
274 $ref: /schemas/types.yaml#/definitions/phandle-array
278 List of phandles to idle state nodes supported by this cpu (see
279 ./idle-states.yaml).
281 capacity-dmips-mhz:
283 u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in
284 DMIPS/MHz, relative to highest capacity-dmips-mhz in the system.
286 cci-control-port: true
288 dynamic-power-coefficient:
295 The dynamic power consumption of the CPU is proportional to the square of
296 the Voltage (V) and the clock frequency (f). The coefficient is used to
297 calculate the dynamic power as below -
299 Pdyn = dynamic-power-coefficient * V^2 * f
307 nvmem-cells:
310 nvmem-cell-names:
313 performance-domains:
316 power-domains:
320 power-domain-names:
334 arm-supply:
336 description: Use 'cpu-supply' instead
338 cpu0-supply:
340 description: Use 'cpu-supply' instead
342 mem-supply: true
344 proc-supply:
346 description: Use 'cpu-supply' instead
348 sram-supply:
350 description: Use 'mem-supply' instead
359 Specifies the SAW node associated with this CPU.
364 Specifies the ACC node associated with this CPU.
366 qcom,freq-domain:
367 description: Specifies the QCom CPUFREQ HW associated with the CPU.
368 $ref: /schemas/types.yaml#/definitions/phandle-array
374 Specifies the syscon node controlling the cpu core power domains.
376 Optional for systems that have an "enable-method" property value of
377 "rockchip,rk3066-smp". While optional, it is the preferred way to get
378 access to the cpu-core power-domains.
380 secondary-boot-reg:
383 Required for systems that have an "enable-method" property value of
384 "brcm,bcm11351-cpu-method", "brcm,bcm23550" or "brcm,bcm-nsp-smp".
390 The secondary-boot-reg property is a u32 value that specifies the
392 code release a secondary CPU. The value written to the register is
393 formed by encoding the target CPU id into the low bits of the
396 thermal-idle:
400 - $ref: /schemas/cpu.yaml#
401 - $ref: /schemas/opp/opp-v1.yaml#
402 - if:
403 # If the enable-method property contains one of those values
405 enable-method:
408 - brcm,bcm11351-cpu-method
409 - brcm,bcm23550
410 - brcm,bcm-nsp-smp
411 # and if enable-method is present
413 - enable-method
416 - secondary-boot-reg
417 - if:
419 enable-method:
421 - spin-table
422 - renesas,r9a06g032-smp
424 - enable-method
427 - cpu-release-addr
428 - if:
430 enable-method:
432 - qcom,kpss-acc-v1
433 - qcom,kpss-acc-v2
434 - qcom,msm8226-smp
435 - qcom,msm8916-smp
437 - enable-method
440 - qcom,acc
441 - qcom,saw
445 # "spin-table" or "psci" enable-methods. Disallowing the properties for
451 const: arm,cortex-a53
458 - device_type
459 - reg
460 - compatible
463 rockchip,pmu: [enable-method]
468 - |
470 #size-cells = <0>;
471 #address-cells = <1>;
473 cpu@0 {
474 device_type = "cpu";
475 compatible = "arm,cortex-a15";
479 cpu@1 {
480 device_type = "cpu";
481 compatible = "arm,cortex-a15";
485 cpu@100 {
486 device_type = "cpu";
487 compatible = "arm,cortex-a7";
491 cpu@101 {
492 device_type = "cpu";
493 compatible = "arm,cortex-a7";
498 - |
499 // Example 2 (Cortex-A8 uniprocessor 32-bit system):
501 #size-cells = <0>;
502 #address-cells = <1>;
504 cpu@0 {
505 device_type = "cpu";
506 compatible = "arm,cortex-a8";
511 - |
512 // Example 3 (ARM 926EJ-S uniprocessor 32-bit system):
514 #size-cells = <0>;
515 #address-cells = <1>;
517 cpu@0 {
518 device_type = "cpu";
519 compatible = "arm,arm926ej-s";
524 - |
525 // Example 4 (ARM Cortex-A57 64-bit system):
527 #size-cells = <0>;
528 #address-cells = <2>;
530 cpu@0 {
531 device_type = "cpu";
532 compatible = "arm,cortex-a57";
534 enable-method = "spin-table";
535 cpu-release-addr = <0 0x20000000>;
538 cpu@1 {
539 device_type = "cpu";
540 compatible = "arm,cortex-a57";
542 enable-method = "spin-table";
543 cpu-release-addr = <0 0x20000000>;
546 cpu@100 {
547 device_type = "cpu";
548 compatible = "arm,cortex-a57";
550 enable-method = "spin-table";
551 cpu-release-addr = <0 0x20000000>;
554 cpu@101 {
555 device_type = "cpu";
556 compatible = "arm,cortex-a57";
558 enable-method = "spin-table";
559 cpu-release-addr = <0 0x20000000>;
562 cpu@10000 {
563 device_type = "cpu";
564 compatible = "arm,cortex-a57";
566 enable-method = "spin-table";
567 cpu-release-addr = <0 0x20000000>;
570 cpu@10001 {
571 device_type = "cpu";
572 compatible = "arm,cortex-a57";
574 enable-method = "spin-table";
575 cpu-release-addr = <0 0x20000000>;
578 cpu@10100 {
579 device_type = "cpu";
580 compatible = "arm,cortex-a57";
582 enable-method = "spin-table";
583 cpu-release-addr = <0 0x20000000>;
586 cpu@10101 {
587 device_type = "cpu";
588 compatible = "arm,cortex-a57";
590 enable-method = "spin-table";
591 cpu-release-addr = <0 0x20000000>;
594 cpu@100000000 {
595 device_type = "cpu";
596 compatible = "arm,cortex-a57";
598 enable-method = "spin-table";
599 cpu-release-addr = <0 0x20000000>;
602 cpu@100000001 {
603 device_type = "cpu";
604 compatible = "arm,cortex-a57";
606 enable-method = "spin-table";
607 cpu-release-addr = <0 0x20000000>;
610 cpu@100000100 {
611 device_type = "cpu";
612 compatible = "arm,cortex-a57";
614 enable-method = "spin-table";
615 cpu-release-addr = <0 0x20000000>;
618 cpu@100000101 {
619 device_type = "cpu";
620 compatible = "arm,cortex-a57";
622 enable-method = "spin-table";
623 cpu-release-addr = <0 0x20000000>;
626 cpu@100010000 {
627 device_type = "cpu";
628 compatible = "arm,cortex-a57";
630 enable-method = "spin-table";
631 cpu-release-addr = <0 0x20000000>;
634 cpu@100010001 {
635 device_type = "cpu";
636 compatible = "arm,cortex-a57";
638 enable-method = "spin-table";
639 cpu-release-addr = <0 0x20000000>;
642 cpu@100010100 {
643 device_type = "cpu";
644 compatible = "arm,cortex-a57";
646 enable-method = "spin-table";
647 cpu-release-addr = <0 0x20000000>;
650 cpu@100010101 {
651 device_type = "cpu";
652 compatible = "arm,cortex-a57";
654 enable-method = "spin-table";
655 cpu-release-addr = <0 0x20000000>;