Lines Matching +full:always +full:- +full:running
25 virtual-->physical address translations obtained from the software
44 the TLB. After running, this interface must make sure that
46 'mm' will be visible to the cpu. That is, after running,
57 address translations from the TLB. After running, this
59 modifications for the address space 'vma->vm_mm' in the range
60 'start' to 'end-1' will be visible to the cpu. That is, after
61 running, there will be no entries in the TLB for 'mm' for
62 virtual addresses in the range 'start' to 'end-1'.
78 address space is available via vma->vm_mm. Also, one may
79 test (vma->vm_flags & VM_EXEC) to see if this region is
81 split-tlb type setups).
83 After running, this interface must make sure that any previous
84 page table modification for address space 'vma->vm_mm' for
86 is, after running, there will be no entries in the TLB for
87 'vma->vm_mm' for virtual address 'addr'.
97 in the software page tables for address space "vma->vm_mm"
104 For example, it could use this event to pre-load TLB
109 is changing an existing virtual-->physical mapping to a new value,
124 The cache level flush will always be first, because this allows
126 a virtual-->physical translation to exist for a virtual address
133 indexed caches which must be flushed when virtual-->physical
144 the caches. That is, after running, there will be no cache
153 the caches. That is, after running, there will be no cache
166 addresses from the cache. After running, there will be no
167 entries in the cache for 'vma->vm_mm' for virtual addresses in
168 the range 'start' to 'end-1'.
184 address space is available via vma->vm_mm. Also, one may
185 test (vma->vm_flags & VM_EXEC) to see if this region is
194 After running, there will be no entries in the cache for
195 'vma->vm_mm' for virtual address 'addr' which translates
206 After running, there will be no entries in the cache for
216 of (kernel) virtual addresses from the cache. After running,
218 space for virtual addresses in the range 'start' to 'end-1'.
229 Is your port susceptible to virtual aliasing in its D-cache?
230 Well, if your D-cache is virtually indexed, is larger in size than
234 If your D-cache has this problem, first define asm/shmparam.h SHMLBA
236 addressed D-cache (or if the size is variable, the largest possible
246 Next, you have to solve the D-cache aliasing issue for all
248 mapped into some user address space, there is always at least one more
251 physical page into its address space, by implication the D-cache
259 pages. It allows a port to efficiently avoid D-cache alias
273 If D-cache aliasing is not an issue, these two routines may
299 flush here to handle D-cache aliasing, to make sure these kernel stores
306 If D-cache aliasing is not an issue, this routine may simply be defined
309 There is a bit set aside in folio->flags (PG_arch_1) as "architecture