Lines Matching +full:reg +full:- +full:spaces

1 .. SPDX-License-Identifier: GPL-2.0
10   Segment-register:Byte-address
12 The segment base address is added to the Byte-address to compute the
14 instances of data with the identical Byte-address, i.e. the same code. The
15 selection of a particular instance is purely based on the base-address in
18 In 32-bit mode the CPU provides 6 segments, which also support segment
21 In 64-bit mode the CS/SS/DS/ES segments are ignored and the base address is
23 still functional in 64-bit mode.
26 ------------------------------
42 ------------------------------------------
46  - the arch_prctl() system call
48  - the FSGSBASE instruction family
51 --------------------------------------
53  The arch_prctl(2) based mechanism is available on all 64-bit CPUs and all
70 ---------------------------------------------------
78   RDFSBASE %reg   Read the FS base register
79   RDGSBASE %reg   Read the GS base register
80   WRFSBASE %reg   Write the FS base register
81   WRGSBASE %reg   Write the GS base register
139 code and the compiler option -mfsgsbase has to be added.
142 -------------------------------------------
145 Named Address Spaces. GCC implements the following address space
154 address spaces are supported. Code which implements fallback modes should
181 address spaces via an attribute based mechanism in Clang 2.6 and newer
190 -------------------------------------------
192 In case the compiler does not support address spaces, inline assembly can
195 	mov %fs:offset, %reg
196 	mov %gs:offset, %reg
198 	mov %reg, %fs:offset
199 	mov %reg, %gs:offset