Lines Matching +full:riscv +full:- +full:zicond
1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
34 How matching is done depends on the key type. For value-like keys, matching
35 means to be the exact same as the value. For boolean-like keys, matching
49 as defined by the RISC-V privileged architecture specification.
52 defined by the RISC-V privileged architecture specification.
55 defined by the RISC-V privileged architecture specification.
58 user-visible behavior that this kernel supports. The following base user ABIs
68 kernel-controlled mechanism such as the vDSO).
76 minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
79 by version 2.2 of the RISC-V ISA manual.
82 version 1.0 of the RISC-V Vector extension manual.
85 supported, as defined in version 1.0 of the Bit-Manipulation ISA
89 in version 1.0 of the Bit-Manipulation ISA extensions.
92 in version 1.0 of the Bit-Manipulation ISA extensions.
95 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
98 in version 1.0 of the Bit-Manipulation ISA extensions.
128 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
131 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
134 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
137 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
140 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
143 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
146 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
149 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
152 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
155 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
158 as defined in the RISC-V ISA manual.
161 supported as defined in the RISC-V ISA manual.
164 is supported as defined in the RISC-V ISA manual.
167 defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
171 defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
175 defined in the RISC-V ISA manual starting from commit 056b6ff467c7
179 defined in the RISC-V ISA manual starting from commit 5618fb5a216b
183 defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
187 is supported as defined in the RISC-V ISA manual.
189 * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
190 defined in the RISC-V Integer Conditional (Zicond) operations extension
195 supported as defined in the RISC-V ISA manual starting from commit
199 is supported as defined in the RISC-V ISA manual.
201 * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
202 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
204 * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
205 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
207 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
208 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
210 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
211 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
213 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
214 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
216 * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
217 supported as defined in the RISC-V ISA manual starting from commit
223 riscv-code-size-reduction.
228 riscv-code-size-reduction.
233 riscv-code-size-reduction.
238 riscv-code-size-reduction.
240 * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is
241 supported as defined in the RISC-V ISA manual starting from commit
246 riscv/zawrs") of riscv-isa-manual.
249 defined in the in the RISC-V ISA manual starting from commit e87412e621f1
253 defined in the in the RISC-V ISA manual starting from commit e87412e621f1
257 defined in version 1.0 of the RISC-V Pointer Masking extensions.
260 defined in the RISC-V ISA manual starting from commit 4dc23d6229de
264 defined in the RISC-V ISA manual starting from commit 4dc23d6229de
268 defined in the RISC-V ISA manual starting from commit 4dc23d6229de
272 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
316 * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector
320 * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector
330 * T-HEAD
333 extension is supported in the T-Head ISA extensions spec starting from
334 commit a18c801634 ("Add T-Head VECTOR vendor extension. ").