Lines Matching +full:riscv +full:- +full:crypto
1 .. SPDX-License-Identifier: GPL-2.0
3 RISC-V Hardware Probing Interface
4 ---------------------------------
6 The RISC-V hardware probing interface is based around a single syscall, which
18 The arguments are split into three groups: an array of key-value pairs, a CPU
19 set, and some flags. The key-value pairs are supplied with a count. Userspace
22 will be cleared to -1, and its value set to 0. The CPU set is defined by
23 CPU_SET(3) with size ``cpusetsize`` bytes. For value-like keys (eg. vendor,
25 have the same value. Otherwise -1 will be returned. For boolean-like keys, the
33 by sys_riscv_hwprobe() to only those which match each of the key-value pairs.
34 How matching is done depends on the key type. For value-like keys, matching
35 means to be the exact same as the value. For boolean-like keys, matching
49 as defined by the RISC-V privileged architecture specification.
52 defined by the RISC-V privileged architecture specification.
55 defined by the RISC-V privileged architecture specification.
58 user-visible behavior that this kernel supports. The following base user ABIs
68 kernel-controlled mechanism such as the vDSO).
76 minimumNumber/maximumNumber, not minNum/maxNum") of the RISC-V ISA manual.
79 by version 2.2 of the RISC-V ISA manual.
82 version 1.0 of the RISC-V Vector extension manual.
85 supported, as defined in version 1.0 of the Bit-Manipulation ISA
89 in version 1.0 of the Bit-Manipulation ISA extensions.
92 in version 1.0 of the Bit-Manipulation ISA extensions.
95 ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
98 in version 1.0 of the Bit-Manipulation ISA extensions.
101 defined in version 1.0 of the Scalar Crypto ISA extensions.
104 defined in version 1.0 of the Scalar Crypto ISA extensions.
107 defined in version 1.0 of the Scalar Crypto ISA extensions.
110 defined in version 1.0 of the Scalar Crypto ISA extensions.
113 defined in version 1.0 of the Scalar Crypto ISA extensions.
116 defined in version 1.0 of the Scalar Crypto ISA extensions.
119 defined in version 1.0 of the Scalar Crypto ISA extensions.
122 defined in version 1.0 of the Scalar Crypto ISA extensions.
125 in version 1.0 of the Scalar Crypto ISA extensions.
128 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
131 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
134 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
137 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
140 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
143 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
146 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
149 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
152 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
155 defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
158 as defined in the RISC-V ISA manual.
161 supported as defined in the RISC-V ISA manual.
164 is supported as defined in the RISC-V ISA manual.
167 defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
171 defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
175 defined in the RISC-V ISA manual starting from commit 056b6ff467c7
179 defined in the RISC-V ISA manual starting from commit 5618fb5a216b
183 defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
187 defined in the RISC-V Integer Conditional (Zicond) operations extension
192 supported as defined in the RISC-V ISA manual starting from commit
195 * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
196 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
198 * :c:macro:`RISCV_HWPROBE_EXT_ZVE32F`: The Vector sub-extension Zve32f is
199 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
201 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64X`: The Vector sub-extension Zve64x is
202 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
204 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64F`: The Vector sub-extension Zve64f is
205 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
207 * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is
208 supported, as defined by version 1.0 of the RISC-V Vector extension manual.
210 * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
211 supported as defined in the RISC-V ISA manual starting from commit
217 riscv-code-size-reduction.
222 riscv-code-size-reduction.
227 riscv-code-size-reduction.
232 riscv-code-size-reduction.
234 * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is
235 supported as defined in the RISC-V ISA manual starting from commit
240 riscv/zawrs") of riscv-isa-manual.
243 defined in version 1.0 of the RISC-V Pointer Masking extensions.
287 * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_SLOW`: 32-bit misaligned accesses using vector
291 * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_FAST`: 32-bit misaligned accesses using vector
301 * T-HEAD
304 extension is supported in the T-Head ISA extensions spec starting from
305 commit a18c801634 ("Add T-Head VECTOR vendor extension. ").