Lines Matching full:will

48 references will complete in one go if there are no conflicts with other
54 lwarx/stwcx), either *both* SAVINGS_ACCT(r3) and CURRENT_ACCT(r3) will be
55 updated, or neither will be updated.
58 transaction, the transaction will be aborted by the CPU.  Register and memory
59 state will roll back to that at the 'tbegin', and control will continue from
60 'tbegin+4'.  The branch to abort_handler will be taken this second time; the
72 - See the ISA for full documentation of everything that will abort transactions.
78 Syscalls made from within an active transaction will not be performed and the
79 transaction will be doomed by the kernel with the failure code TM_CAUSE_SYSCALL
86 effects will be persistent, independent of transaction success or failure.  No
87 guarantees are provided by the kernel about which syscalls will affect
121 and simply returning from the handler will deal with things correctly:
124 from the second ucontext.  This will be necessary for crash handlers to
158 stack pointer will be back at the tbegin but our in memory stack won't be valid
163 state.  This ensures that the signal context (written tm suspended) will be
166 signal will be rolled back anyway.
172 from the sighandler to the kernel will get reclaimed and discarded.
193 a TM_CAUSE_ALIGNMENT will be persistent while a TM_CAUSE_RESCHED will not.
200 presented).  The transaction cannot then be continued and will take the failure
201 handler route.  Furthermore, the transactional 2nd register state will be
223 transaction when tm suspend occurs. So tsuspend will cause a
224 transaction to be aborted and rolled back. Kernel exceptions will also
226 will not occur. If userspace constructs a sigcontext that enables TM
227 suspend, the sigcontext will be rejected by the kernel. This mode is
234 makes heavy use of TM suspend (tsuspend or kernel suspend) will result
235 in traps into the hypervisor and hence will suffer a performance
245 Guest migration from POWER8 to POWER9 will work with POWER9N DD2.2 and
257 kernel via some exception, MSR will end up as TM=0 and TS=01 (ie. TM
258 off but TM suspended). Regularly the kernel will want change bits in
259 the MSR and will perform an rfid to do this. In this case rfid can
261 resulting MSR will retain TM = 0 and TS=01 from before (ie. stay in