Lines Matching +full:mode +full:- +full:loader
13 (EL0 - EL3), with EL0, EL1 and EL2 having a secure and a non-secure
15 level and exists only in secure mode. Both are architecturally optional.
17 For the purposes of this document, we will use the term `boot loader`
23 Essentially, the boot loader should provide (as a minimum) the
33 ---------------------------
37 The boot loader is expected to find and initialise all RAM that the
41 the RAM in the machine, or any other method the boot loader designer
49 -------------------------
53 The device tree blob (dtb) must be placed on an 8-byte boundary and must
62 ------------------------------
68 loader if a compressed Image target (e.g. Image.gz) is used. For
74 ------------------------
78 The decompressed kernel image contains a 64-byte header as follows::
94 - As of v3.17, all fields are little endian unless stated otherwise.
96 - code0/code1 are responsible for branching to stext.
98 - when booting through EFI, code0/code1 are initially skipped.
103 - Prior to v3.17, the endianness of text_offset was not specified. In
105 endianness of the kernel. Where image_size is non-zero image_size is
106 little-endian and must be respected. Where image_size is zero,
109 - The flags field (introduced in v3.17) is a little-endian 64-bit field
114 Bit 1-2 Kernel Page size.
116 * 0 - Unspecified.
117 * 1 - 4K
118 * 2 - 16K
119 * 3 - 64K
129 the 48-bit addressable range of physical memory
130 Bits 4-63 Reserved.
133 - When image_size is zero, a bootloader should attempt to keep as much
159 - Quiesce all DMA capable devices so that memory does not get
163 - Primary CPU general-purpose register settings:
165 - x0 = physical address of device tree blob (dtb) in system RAM.
166 - x1 = 0 (reserved for future use)
167 - x2 = 0 (reserved for future use)
168 - x3 = 0 (reserved for future use)
170 - CPU mode
174 The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
177 - Caches, MMUs
193 - Architected timers
200 - Coherency
207 - System registers
215 - If EL3 is present:
217 - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
219 - The value of SCR_EL3.FIQ must be the same as the one present at boot
222 - If EL3 is present and the kernel is entered at EL2:
224 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
226 For systems with a GICv5 interrupt controller to be used in v5 mode:
228 - If the kernel is entered at EL1 and EL2 is present:
230 - ICH_HFGRTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.
231 - ICH_HFGRTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.
232 - ICH_HFGRTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.
233 - ICH_HFGRTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.
234 - ICH_HFGRTR_EL2.ICC_PPI_HMRn_EL1 (bit 16) must be initialised to 0b1.
235 - ICH_HFGRTR_EL2.ICC_IAFFIDR_EL1 (bit 7) must be initialised to 0b1.
236 - ICH_HFGRTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.
237 - ICH_HFGRTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.
238 - ICH_HFGRTR_EL2.ICC_HPPIR_EL1 (bit 4) must be initialised to 0b1.
239 - ICH_HFGRTR_EL2.ICC_HAPR_EL1 (bit 3) must be initialised to 0b1.
240 - ICH_HFGRTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.
241 - ICH_HFGRTR_EL2.ICC_IDRn_EL1 (bit 1) must be initialised to 0b1.
242 - ICH_HFGRTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.
244 - ICH_HFGWTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.
245 - ICH_HFGWTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.
246 - ICH_HFGWTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.
247 - ICH_HFGWTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.
248 - ICH_HFGWTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.
249 - ICH_HFGWTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.
250 - ICH_HFGWTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.
251 - ICH_HFGWTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.
253 - ICH_HFGITR_EL2.GICRCDNMIA (bit 10) must be initialised to 0b1.
254 - ICH_HFGITR_EL2.GICRCDIA (bit 9) must be initialised to 0b1.
255 - ICH_HFGITR_EL2.GICCDDI (bit 8) must be initialised to 0b1.
256 - ICH_HFGITR_EL2.GICCDEOI (bit 7) must be initialised to 0b1.
257 - ICH_HFGITR_EL2.GICCDHM (bit 6) must be initialised to 0b1.
258 - ICH_HFGITR_EL2.GICCDRCFG (bit 5) must be initialised to 0b1.
259 - ICH_HFGITR_EL2.GICCDPEND (bit 4) must be initialised to 0b1.
260 - ICH_HFGITR_EL2.GICCDAFF (bit 3) must be initialised to 0b1.
261 - ICH_HFGITR_EL2.GICCDPRI (bit 2) must be initialised to 0b1.
262 - ICH_HFGITR_EL2.GICCDDIS (bit 1) must be initialised to 0b1.
263 - ICH_HFGITR_EL2.GICCDEN (bit 0) must be initialised to 0b1.
265 - The DT or ACPI tables must describe a GICv5 interrupt controller.
267 For systems with a GICv3 interrupt controller to be used in v3 mode:
268 - If EL3 is present:
270 - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
271 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
272 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
276 - If the kernel is entered at EL1:
278 - ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1
279 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
281 - The DT or ACPI tables must describe a GICv3 interrupt controller.
284 compatibility (v2) mode:
286 - If EL3 is present:
290 - If the kernel is entered at EL1:
294 - The DT or ACPI tables must describe a GICv2 interrupt controller.
298 - If EL3 is present:
300 - SCR_EL3.APK (bit 16) must be initialised to 0b1
301 - SCR_EL3.API (bit 17) must be initialised to 0b1
303 - If the kernel is entered at EL1:
305 - HCR_EL2.APK (bit 40) must be initialised to 0b1
306 - HCR_EL2.API (bit 41) must be initialised to 0b1
310 - If EL3 is present:
312 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
313 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
314 - AMCNTENSET0_EL0 must be initialised to 0b1111
315 - AMCNTENSET1_EL0 must be initialised to a platform specific value
319 - If the kernel is entered at EL1:
321 - AMCNTENSET0_EL0 must be initialised to 0b1111
322 - AMCNTENSET1_EL0 must be initialised to a platform specific value
328 - If EL3 is present and the kernel is entered at EL2:
330 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
334 - If EL3 is present and the kernel is entered at EL2:
336 - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
340 - If EL3 is present and the kernel is entered at EL2:
342 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
346 - If EL3 is present:
348 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
350 - If EL2 is present and the kernel is entered at EL1:
352 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
356 - if EL3 is present:
358 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
360 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
363 - If the kernel is entered at EL1 and EL2 is present:
365 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
367 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
369 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
374 - If EL3 is present:
376 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
378 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
380 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
383 - If the kernel is entered at EL1 and EL2 is present:
385 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
387 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
389 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
391 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
394 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
396 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
398 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
400 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
404 - If EL3 is present:
406 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
408 - If the kernel is entered at EL1 and EL2 is present:
410 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
414 - If EL3 is present:
416 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
418 - If the kernel is entered at EL1 and EL2 is present:
420 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
424 - If EL3 is present:
426 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
428 - If the kernel is entered at EL1 and EL2 is present:
430 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
434 - If EL3 is present:
436 - MDCR_EL3.SBRBE (bits 33:32) must be initialised to 0b01 or 0b11.
438 - If the kernel is entered at EL1 and EL2 is present:
440 - BRBCR_EL2.CC (bit 3) must be initialised to 0b1.
441 - BRBCR_EL2.MPRED (bit 4) must be initialised to 0b1.
443 - HDFGRTR_EL2.nBRBDATA (bit 61) must be initialised to 0b1.
444 - HDFGRTR_EL2.nBRBCTL (bit 60) must be initialised to 0b1.
445 - HDFGRTR_EL2.nBRBIDR (bit 59) must be initialised to 0b1.
447 - HDFGWTR_EL2.nBRBDATA (bit 61) must be initialised to 0b1.
448 - HDFGWTR_EL2.nBRBCTL (bit 60) must be initialised to 0b1.
450 - HFGITR_EL2.nBRBIALL (bit 56) must be initialised to 0b1.
451 - HFGITR_EL2.nBRBINJ (bit 55) must be initialised to 0b1.
455 - If EL3 is present:
457 - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1.
459 - If the kernel is entered at EL1 and EL2 is present:
461 - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
462 - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
463 - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
465 - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
466 - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
467 - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
471 - If EL3 is present:
473 - MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1.
475 - If the kernel is entered at EL1 and EL2 is present:
477 - HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
478 - HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
482 - If the kernel is entered at EL1 and EL2 is present:
484 - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
486 - HCRX_EL2.MCE2 (bit 10) must be initialised to 0b1 and the hypervisor
491 - If EL3 is present:
493 - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
495 - If the kernel is entered at EL1 and EL2 is present:
497 - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
501 - If EL3 is present:
503 - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
505 - If the kernel is entered at EL1 and EL2 is present:
507 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
509 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
511 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
513 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
515 - For CPUs with Guarded Control Stacks (FEAT_GCS):
517 - GCSCR_EL1 must be initialised to 0.
519 - GCSCRE0_EL1 must be initialised to 0.
521 - If EL3 is present:
523 - SCR_EL3.GCSEn (bit 39) must be initialised to 0b1.
525 - If EL2 is present:
527 - GCSCR_EL2 must be initialised to 0.
529 - If the kernel is entered at EL1 and EL2 is present:
531 - HCRX_EL2.GCSEn must be initialised to 0b1.
533 - HFGITR_EL2.nGCSEPP (bit 59) must be initialised to 0b1.
535 - HFGITR_EL2.nGCSSTR_EL1 (bit 58) must be initialised to 0b1.
537 - HFGITR_EL2.nGCSPUSHM_EL1 (bit 57) must be initialised to 0b1.
539 - HFGRTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
541 - HFGRTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
543 - HFGWTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
545 - HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
547 - For CPUs with debug architecture i.e FEAT_Debugv8pN (all versions):
549 - If EL3 is present:
551 - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
553 - For CPUs with FEAT_PMUv3:
555 - If EL3 is present:
557 - MDCR_EL3.TPM (bit 6) must be initialized to 0b0
559 The requirements described above for CPU mode, caches, MMUs, architected
566 The boot loader is expected to enter the kernel on each CPU in the
569 - The primary CPU must jump directly to the first instruction of the
571 an 'enable-method' property for each cpu node. The supported
572 enable-methods are described below.
577 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
579 naturally-aligned 64-bit zero-initalised memory location.
583 device tree) polling their cpu-release-addr location, which must be
585 to reduce the overhead of the busy-loop and a sev will be issued by
587 cpu-release-addr returns a non-zero value, the CPU must jump to this
588 value. The value will be written as a single 64-bit little-endian
592 - CPUs with a "psci" enable method should remain outside of
603 - Secondary CPU general-purpose register settings
605 - x0 = 0 (reserved for future use)
606 - x1 = 0 (reserved for future use)
607 - x2 = 0 (reserved for future use)
608 - x3 = 0 (reserved for future use)