Lines Matching full:initialised
210 level where the kernel image will be entered must be initialised by
224 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
230 - ICH_HFGRTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.
231 - ICH_HFGRTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.
232 - ICH_HFGRTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.
233 - ICH_HFGRTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.
234 - ICH_HFGRTR_EL2.ICC_PPI_HMRn_EL1 (bit 16) must be initialised to 0b1.
235 - ICH_HFGRTR_EL2.ICC_IAFFIDR_EL1 (bit 7) must be initialised to 0b1.
236 - ICH_HFGRTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.
237 - ICH_HFGRTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.
238 - ICH_HFGRTR_EL2.ICC_HPPIR_EL1 (bit 4) must be initialised to 0b1.
239 - ICH_HFGRTR_EL2.ICC_HAPR_EL1 (bit 3) must be initialised to 0b1.
240 - ICH_HFGRTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.
241 - ICH_HFGRTR_EL2.ICC_IDRn_EL1 (bit 1) must be initialised to 0b1.
242 - ICH_HFGRTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.
244 - ICH_HFGWTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.
245 - ICH_HFGWTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.
246 - ICH_HFGWTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.
247 - ICH_HFGWTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.
248 - ICH_HFGWTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.
249 - ICH_HFGWTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.
250 - ICH_HFGWTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.
251 - ICH_HFGWTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.
253 - ICH_HFGITR_EL2.GICRCDNMIA (bit 10) must be initialised to 0b1.
254 - ICH_HFGITR_EL2.GICRCDIA (bit 9) must be initialised to 0b1.
255 - ICH_HFGITR_EL2.GICCDDI (bit 8) must be initialised to 0b1.
256 - ICH_HFGITR_EL2.GICCDEOI (bit 7) must be initialised to 0b1.
257 - ICH_HFGITR_EL2.GICCDHM (bit 6) must be initialised to 0b1.
258 - ICH_HFGITR_EL2.GICCDRCFG (bit 5) must be initialised to 0b1.
259 - ICH_HFGITR_EL2.GICCDPEND (bit 4) must be initialised to 0b1.
260 - ICH_HFGITR_EL2.GICCDAFF (bit 3) must be initialised to 0b1.
261 - ICH_HFGITR_EL2.GICCDPRI (bit 2) must be initialised to 0b1.
262 - ICH_HFGITR_EL2.GICCDDIS (bit 1) must be initialised to 0b1.
263 - ICH_HFGITR_EL2.GICCDEN (bit 0) must be initialised to 0b1.
270 - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
271 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
278 - ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1
279 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
288 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
292 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
300 - SCR_EL3.APK (bit 16) must be initialised to 0b1
301 - SCR_EL3.API (bit 17) must be initialised to 0b1
305 - HCR_EL2.APK (bit 40) must be initialised to 0b1
306 - HCR_EL2.API (bit 41) must be initialised to 0b1
312 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
313 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
314 - AMCNTENSET0_EL0 must be initialised to 0b1111
315 - AMCNTENSET1_EL0 must be initialised to a platform specific value
321 - AMCNTENSET0_EL0 must be initialised to 0b1111
322 - AMCNTENSET1_EL0 must be initialised to a platform specific value
330 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
336 - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
342 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
348 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
352 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
358 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
360 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
365 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
367 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
369 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
376 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
378 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
380 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
385 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
387 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
389 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
391 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
394 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
396 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
398 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
400 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
406 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
410 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
416 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
420 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
426 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
430 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
436 - MDCR_EL3.SBRBE (bits 33:32) must be initialised to 0b01 or 0b11.
440 - BRBCR_EL2.CC (bit 3) must be initialised to 0b1.
441 - BRBCR_EL2.MPRED (bit 4) must be initialised to 0b1.
443 - HDFGRTR_EL2.nBRBDATA (bit 61) must be initialised to 0b1.
444 - HDFGRTR_EL2.nBRBCTL (bit 60) must be initialised to 0b1.
445 - HDFGRTR_EL2.nBRBIDR (bit 59) must be initialised to 0b1.
447 - HDFGWTR_EL2.nBRBDATA (bit 61) must be initialised to 0b1.
448 - HDFGWTR_EL2.nBRBCTL (bit 60) must be initialised to 0b1.
450 - HFGITR_EL2.nBRBIALL (bit 56) must be initialised to 0b1.
451 - HFGITR_EL2.nBRBINJ (bit 55) must be initialised to 0b1.
457 - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1.
461 - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
462 - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
463 - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
465 - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
466 - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
467 - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
473 - MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1.
477 - HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
478 - HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
484 - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
486 - HCRX_EL2.MCE2 (bit 10) must be initialised to 0b1 and the hypervisor
493 - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
497 - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
503 - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
507 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
509 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
511 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
513 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
517 - GCSCR_EL1 must be initialised to 0.
519 - GCSCRE0_EL1 must be initialised to 0.
523 - SCR_EL3.GCSEn (bit 39) must be initialised to 0b1.
527 - GCSCR_EL2 must be initialised to 0.
531 - HCRX_EL2.GCSEn must be initialised to 0b1.
533 - HFGITR_EL2.nGCSEPP (bit 59) must be initialised to 0b1.
535 - HFGITR_EL2.nGCSSTR_EL1 (bit 58) must be initialised to 0b1.
537 - HFGITR_EL2.nGCSPUSHM_EL1 (bit 57) must be initialised to 0b1.
539 - HFGRTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
541 - HFGRTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
543 - HFGWTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
545 - HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.