Lines Matching full:be
20 hypervisor code, or it may just be a handful of instructions for
53 The device tree blob (dtb) must be placed on an 8-byte boundary and must
54 not exceed 2 megabytes in size. Since the dtb will be mapped cacheable
55 using blocks of up to 2 megabytes in size, it must not be placed within
56 any 2M region which must be mapped with any specific attributes.
58 NOTE: versions prior to v4.2 also require that the DTB be placed within
67 therefore requires decompression (gzip etc.) to be performed by the boot
106 little-endian and must be respected. Where image_size is zero,
107 text_offset can be assumed to be 0x80000.
113 Bit 0 Kernel endianness. 1 if BE, 0 if LE.
123 2MB aligned base should be as close as possible
138 The Image must be placed text_offset bytes from a 2MB aligned base
141 special significance to the kernel, and may be used for other purposes.
142 At least image_size bytes from the start of the image must be free for
145 physical offset of the Image so it is recommended that the Image be
154 memreserve region in the device tree) will be considered as available to
157 Before jumping into the kernel, the following conditions must be met:
172 All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
174 The CPU must be in non-secure state, either in EL2 (RECOMMENDED in order
179 The MMU must be off.
181 The instruction cache may be on or off, and must not hold any stale
184 The address range corresponding to the loaded kernel image must be
189 operations must be configured and may be enabled.
191 operations (not recommended) must be configured and disabled.
195 CNTFRQ must be programmed with the timer frequency and CNTVOFF must
196 be programmed with a consistent value on all CPUs. If entering the
202 All CPUs to be booted by the kernel must be part of the same coherency
210 level where the kernel image will be entered must be initialised by
219 - The value of SCR_EL3.FIQ must be the same as the one present at boot
224 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
226 For systems with a GICv3 interrupt controller to be used in v3 mode:
229 - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
230 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
231 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
237 - ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1
238 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
242 For systems with a GICv3 interrupt controller to be used in
247 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
251 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
259 - SCR_EL3.APK (bit 16) must be initialised to 0b1
260 - SCR_EL3.API (bit 17) must be initialised to 0b1
264 - HCR_EL2.APK (bit 40) must be initialised to 0b1
265 - HCR_EL2.API (bit 41) must be initialised to 0b1
271 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
272 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
273 - AMCNTENSET0_EL0 must be initialised to 0b1111
274 - AMCNTENSET1_EL0 must be initialised to a platform specific value
280 - AMCNTENSET0_EL0 must be initialised to 0b1111
281 - AMCNTENSET1_EL0 must be initialised to a platform specific value
289 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
295 - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
301 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
307 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
311 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
317 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
319 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
324 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
326 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
328 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
335 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
337 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
339 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
344 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
346 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
348 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
350 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
353 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
355 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
357 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
359 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
365 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
369 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
375 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
379 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
385 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
389 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
395 - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1.
399 - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
400 - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
401 - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
403 - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
404 - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
405 - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
411 - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
413 - HCRX_EL2.MCE2 (bit 10) must be initialised to 0b1 and the hypervisor
420 - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
424 - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
430 - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
434 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
436 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
438 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
440 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
444 - GCSCR_EL1 must be initialised to 0.
446 - GCSCRE0_EL1 must be initialised to 0.
450 - SCR_EL3.GCSEn (bit 39) must be initialised to 0b1.
454 - GCSCR_EL2 must be initialised to 0.
458 - HCRX_EL2.GCSEn must be initialised to 0b1.
460 - HFGITR_EL2.nGCSEPP (bit 59) must be initialised to 0b1.
462 - HFGITR_EL2.nGCSSTR_EL1 (bit 58) must be initialised to 0b1.
464 - HFGITR_EL2.nGCSPUSHM_EL1 (bit 57) must be initialised to 0b1.
466 - HFGRTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
468 - HFGRTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
470 - HFGWTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
472 - HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
478 - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
484 - MDCR_EL3.TPM (bit 6) must be initialized to 0b0
489 disable traps it is permissible for these traps to be enabled so long as
510 device tree) polling their cpu-release-addr location, which must be
511 contained in the reserved region. A wfe instruction may be inserted
512 to reduce the overhead of the busy-loop and a sev will be issued by
515 value. The value will be written as a single 64-bit little-endian