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10 is relevant to all public releases of the AArch64 Linux kernel.
18 simply to define all software that executes on the CPU(s) before control
19 is passed to the Linux kernel. This may include secure monitor and
37 The boot loader is expected to find and initialise all RAM that the
40 to automatically locate and size all RAM, or it may use knowledge of
55 using blocks of up to 2 megabytes in size, it must not be placed within
58 NOTE: versions prior to v4.2 also require that the DTB be placed within
67 therefore requires decompression (gzip etc.) to be performed by the boot
96 - code0/code1 are responsible for branching to stext.
99 res5 is an offset to the PE header and the PE header has the EFI
101 jumps to code0 to resume the normal boot process.
103 - Prior to v3.17, the endianness of text_offset was not specified. In
107 text_offset can be assumed to be 0x80000.
124 to the base of DRAM, since memory below it is not
133 - When image_size is zero, a bootloader should attempt to keep as much
141 special significance to the kernel, and may be used for other purposes.
144 NOTE: versions prior to v4.6 cannot make use of memory below the
146 placed as close as possible to the start of system RAM.
148 If an initrd/initramfs is passed to the kernel at boot, it must reside
149 entirely within a 1 GB aligned physical memory window of up to 32 GB in
152 Any memory described to the kernel (even that below the start of the
154 memreserve region in the device tree) will be considered as available to
175 to have access to the virtualisation extensions), or in EL1.
182 entries corresponding to the loaded kernel image.
184 The address range corresponding to the loaded kernel image must be
185 cleaned to the PoC. In the presence of a system cache or other
202 All CPUs to be booted by the kernel must be part of the same coherency
203 domain on entry to the kernel. This may require IMPLEMENTATION DEFINED
204 initialisation to enable the receiving of maintenance operations on
211 software at a higher exception level to prevent execution in an UNKNOWN
224 - SCR_EL3.HCE (bit 8) must be initialised to 0b1.
226 For systems with a GICv5 interrupt controller to be used in v5 mode:
230 - ICH_HFGRTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.
231 - ICH_HFGRTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.
232 - ICH_HFGRTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.
233 - ICH_HFGRTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.
234 - ICH_HFGRTR_EL2.ICC_PPI_HMRn_EL1 (bit 16) must be initialised to 0b1.
235 - ICH_HFGRTR_EL2.ICC_IAFFIDR_EL1 (bit 7) must be initialised to 0b1.
236 - ICH_HFGRTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.
237 - ICH_HFGRTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.
238 - ICH_HFGRTR_EL2.ICC_HPPIR_EL1 (bit 4) must be initialised to 0b1.
239 - ICH_HFGRTR_EL2.ICC_HAPR_EL1 (bit 3) must be initialised to 0b1.
240 - ICH_HFGRTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.
241 - ICH_HFGRTR_EL2.ICC_IDRn_EL1 (bit 1) must be initialised to 0b1.
242 - ICH_HFGRTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.
244 - ICH_HFGWTR_EL2.ICC_PPI_ACTIVERn_EL1 (bit 20) must be initialised to 0b1.
245 - ICH_HFGWTR_EL2.ICC_PPI_PRIORITYRn_EL1 (bit 19) must be initialised to 0b1.
246 - ICH_HFGWTR_EL2.ICC_PPI_PENDRn_EL1 (bit 18) must be initialised to 0b1.
247 - ICH_HFGWTR_EL2.ICC_PPI_ENABLERn_EL1 (bit 17) must be initialised to 0b1.
248 - ICH_HFGWTR_EL2.ICC_ICSR_EL1 (bit 6) must be initialised to 0b1.
249 - ICH_HFGWTR_EL2.ICC_PCR_EL1 (bit 5) must be initialised to 0b1.
250 - ICH_HFGWTR_EL2.ICC_CR0_EL1 (bit 2) must be initialised to 0b1.
251 - ICH_HFGWTR_EL2.ICC_APR_EL1 (bit 0) must be initialised to 0b1.
253 - ICH_HFGITR_EL2.GICRCDNMIA (bit 10) must be initialised to 0b1.
254 - ICH_HFGITR_EL2.GICRCDIA (bit 9) must be initialised to 0b1.
255 - ICH_HFGITR_EL2.GICCDDI (bit 8) must be initialised to 0b1.
256 - ICH_HFGITR_EL2.GICCDEOI (bit 7) must be initialised to 0b1.
257 - ICH_HFGITR_EL2.GICCDHM (bit 6) must be initialised to 0b1.
258 - ICH_HFGITR_EL2.GICCDRCFG (bit 5) must be initialised to 0b1.
259 - ICH_HFGITR_EL2.GICCDPEND (bit 4) must be initialised to 0b1.
260 - ICH_HFGITR_EL2.GICCDAFF (bit 3) must be initialised to 0b1.
261 - ICH_HFGITR_EL2.GICCDPRI (bit 2) must be initialised to 0b1.
262 - ICH_HFGITR_EL2.GICCDDIS (bit 1) must be initialised to 0b1.
263 - ICH_HFGITR_EL2.GICCDEN (bit 0) must be initialised to 0b1.
267 For systems with a GICv3 interrupt controller to be used in v3 mode:
270 - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1.
271 - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1.
272 - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across
278 - ICC_SRE_EL2.Enable (bit 3) must be initialised to 0b1
279 - ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b1.
283 For systems with a GICv3 interrupt controller to be used in
288 ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b0.
292 ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0.
300 - SCR_EL3.APK (bit 16) must be initialised to 0b1
301 - SCR_EL3.API (bit 17) must be initialised to 0b1
305 - HCR_EL2.APK (bit 40) must be initialised to 0b1
306 - HCR_EL2.API (bit 41) must be initialised to 0b1
312 - CPTR_EL3.TAM (bit 30) must be initialised to 0b0
313 - CPTR_EL2.TAM (bit 30) must be initialised to 0b0
314 - AMCNTENSET0_EL0 must be initialised to 0b1111
315 - AMCNTENSET1_EL0 must be initialised to a platform specific value
321 - AMCNTENSET0_EL0 must be initialised to 0b1111
322 - AMCNTENSET1_EL0 must be initialised to a platform specific value
330 - SCR_EL3.FGTEn (bit 27) must be initialised to 0b1.
336 - SCR_EL3.FGTEn2 (bit 59) must be initialised to 0b1.
342 - SCR_EL3.HXEn (bit 38) must be initialised to 0b1.
348 - CPTR_EL3.TFP (bit 10) must be initialised to 0b0.
352 - CPTR_EL2.TFP (bit 10) must be initialised to 0b0.
358 - CPTR_EL3.EZ (bit 8) must be initialised to 0b1.
360 - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
365 - CPTR_EL2.TZ (bit 8) must be initialised to 0b0.
367 - CPTR_EL2.ZEN (bits 17:16) must be initialised to 0b11.
369 - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
376 - CPTR_EL3.ESM (bit 12) must be initialised to 0b1.
378 - SCR_EL3.EnTP2 (bit 41) must be initialised to 0b1.
380 - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
385 - CPTR_EL2.TSM (bit 12) must be initialised to 0b0.
387 - CPTR_EL2.SMEN (bits 25:24) must be initialised to 0b11.
389 - SCTLR_EL2.EnTP2 (bit 60) must be initialised to 0b1.
391 - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
394 - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
396 - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
398 - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
400 - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
406 - SMCR_EL3.FA64 (bit 31) must be initialised to 0b1.
410 - SMCR_EL2.FA64 (bit 31) must be initialised to 0b1.
416 - SCR_EL3.ATA (bit 26) must be initialised to 0b1.
420 - HCR_EL2.ATA (bit 56) must be initialised to 0b1.
426 - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1.
430 - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1.
436 - MDCR_EL3.SBRBE (bits 33:32) must be initialised to 0b01 or 0b11.
440 - BRBCR_EL2.CC (bit 3) must be initialised to 0b1.
441 - BRBCR_EL2.MPRED (bit 4) must be initialised to 0b1.
443 - HDFGRTR_EL2.nBRBDATA (bit 61) must be initialised to 0b1.
444 - HDFGRTR_EL2.nBRBCTL (bit 60) must be initialised to 0b1.
445 - HDFGRTR_EL2.nBRBIDR (bit 59) must be initialised to 0b1.
447 - HDFGWTR_EL2.nBRBDATA (bit 61) must be initialised to 0b1.
448 - HDFGWTR_EL2.nBRBCTL (bit 60) must be initialised to 0b1.
450 - HFGITR_EL2.nBRBIALL (bit 56) must be initialised to 0b1.
451 - HFGITR_EL2.nBRBINJ (bit 55) must be initialised to 0b1.
457 - MDCR_EL3.EnPM2 (bit 7) must be initialised to 0b1.
461 - HDFGRTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
462 - HDFGRTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
463 - HDFGRTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
465 - HDFGWTR2_EL2.nPMICNTR_EL0 (bit 2) must be initialised to 0b1.
466 - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1.
467 - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1.
473 - MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1.
477 - HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
478 - HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1.
484 - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1.
486 - HCRX_EL2.MCE2 (bit 10) must be initialised to 0b1 and the hypervisor
493 - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1.
497 - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1.
503 - SCR_EL3.PIEn (bit 45) must be initialised to 0b1.
507 - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
509 - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1.
511 - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
513 - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1.
517 - GCSCR_EL1 must be initialised to 0.
519 - GCSCRE0_EL1 must be initialised to 0.
523 - SCR_EL3.GCSEn (bit 39) must be initialised to 0b1.
527 - GCSCR_EL2 must be initialised to 0.
531 - HCRX_EL2.GCSEn must be initialised to 0b1.
533 - HFGITR_EL2.nGCSEPP (bit 59) must be initialised to 0b1.
535 - HFGITR_EL2.nGCSSTR_EL1 (bit 58) must be initialised to 0b1.
537 - HFGITR_EL2.nGCSPUSHM_EL1 (bit 57) must be initialised to 0b1.
539 - HFGRTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
541 - HFGRTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
543 - HFGWTR_EL2.nGCS_EL1 (bit 53) must be initialised to 0b1.
545 - HFGWTR_EL2.nGCS_EL0 (bit 52) must be initialised to 0b1.
551 - MDCR_EL3.TDA (bit 9) must be initialized to 0b0
557 - MDCR_EL3.TPM (bit 6) must be initialized to 0b0
560 timers, coherency and system registers apply to all CPUs. All CPUs must
562 disable traps it is permissible for these traps to be enabled so long as
566 The boot loader is expected to enter the kernel on each CPU in the
569 - The primary CPU must jump directly to the first instruction of the
575 properties and insert them into the blob prior to kernel entry.
582 memory (communicated to the kernel by a /memreserve/ region in the
585 to reduce the overhead of the busy-loop and a sev will be issued by
586 the primary CPU. When a read of the location pointed to by the
587 cpu-release-addr returns a non-zero value, the CPU must jump to this
589 value, so CPUs must convert the read value to their native endianness
590 before jumping to it.
593 the kernel (i.e. outside of the regions of memory described to the
595 to the kernel by a /memreserve/ region in the device tree). The
598 processors") to bring CPUs into the kernel.