Lines Matching full:cpus

193   be programmed with a consistent value on all CPUs.  If entering the
199   All CPUs to be booted by the kernel must be part of the same coherency
214     - SCR_EL3.FIQ must have the same value across all CPUs the kernel is
229         all CPUs the kernel is executing on, and must stay constant
252   For CPUs with pointer authentication functionality:
264   For CPUs with Activity Monitors Unit v1 (AMUv1) extension present:
282   For CPUs with the Fine Grained Traps (FEAT_FGT) extension present:
288   For CPUs with support for HCRX_EL2 (FEAT_HCX) present:
294   For CPUs with Advanced SIMD and floating point support:
304   For CPUs with the Scalable Vector Extension (FEAT_SVE) present:
310     - ZCR_EL3.LEN must be initialised to the same value for all CPUs the
319     - ZCR_EL2.LEN must be initialised to the same value for all CPUs the
322   For CPUs with the Scalable Matrix Extension (FEAT_SME):
330     - SMCR_EL3.LEN must be initialised to the same value for all CPUs the
341     - SMCR_EL2.LEN must be initialised to the same value for all CPUs the
352   For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64):
362   For CPUs with the Memory Tagging Extension feature (FEAT_MTE2):
372   For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2):
382   For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS):
388   For CPUs with the Extended Translation Control Register feature (FEAT_TCR2):
398   For CPUs with the Stage 1 Permission Indirection Extension feature (FEAT_S1PIE):
415 timers, coherency and system registers apply to all CPUs.  All CPUs must
432 - CPUs with a "spin-table" enable-method must have a 'cpu-release-addr'
436   These CPUs should spin outside of the kernel in a reserved area of
444   value, so CPUs must convert the read value to their native endianness
447 - CPUs with a "psci" enable method should remain outside of
453   processors") to bring CPUs into the kernel.