Lines Matching +full:powered +full:- +full:off
2 Cluster-wide Power-up/power-down race avoidance algorithm
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19 ability to turn off individual CPUs when the system is idle, reducing
23 to have the ability to turn off entire clusters.
25 Turning entire clusters off and on is a risky business, because it
29 cluster-level operations are only performed when it is truly safe to do
35 disabling those mechanisms may itself be a non-atomic operation (such as
38 power-down and power-up at the cluster level.
46 -----------
50 - DOWN
51 - COMING_UP
52 - UP
53 - GOING_DOWN
57 +---------> UP ----------+
63 +--------- DOWN <--------+
67 The CPU or cluster is not coherent, and is either powered off or
68 suspended, or is ready to be powered off or suspended.
92 CPUs in the cluster simultaneously modifying the state. The cluster-
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103 In this algorithm, each individual core in a multi-core processor is
104 referred to as a "CPU". CPUs are assumed to be single-threaded:
111 - CPU_DOWN
112 - CPU_COMING_UP
113 - CPU_UP
114 - CPU_GOING_DOWN
120 +-----------> CPU_UP ------------+
126 +----------- CPU_DOWN <----------+
143 power-down. On reaching this state, the CPU will typically
153 a) an explicit hardware power-up operation, resulting
214 -------------
233 - CLUSTER_DOWN
234 - CLUSTER_UP
235 - CLUSTER_GOING_DOWN
239 - INBOUND_NOT_COMING_UP
240 - INBOUND_COMING_UP
247 +==========> INBOUND_NOT_COMING_UP -------------+
250 CLUSTER_UP <----+ |
257 INBOUND_COMING_UP <----+ |
260 +=========== CLUSTER_DOWN <------------+
263 Transitions -----> can only be made by the outbound CPU, and
278 cluster can actually be powered down.
309 a) an explicit hardware power-up operation, resulting
322 The purpose of this state is to do sufficient cluster-level
329 cluster-level setup and hardware coherency complete
336 Cluster-level setup is complete and hardware coherency is
354 Cluster-level setup is complete and hardware coherency is
377 cluster-level coherency.
389 cluster torn down and ready to power off
398 a) an explicit hardware power-up operation,
422 the cluster is not really going to be powered down.
429 cluster-level setup and hardware
437 cluster torn down and ready to power off
444 --------------------------------
446 The CPU which performs cluster tear-down operations on the outbound side
461 non-coherent.
466 Because CPUs may power up asynchronously in response to external wake-up
468 attempts to play the first man role and do the cluster-level
472 Cluster-level initialisation may involve actions such as configuring
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485 The current ARM-based implementation is split between
486 arch/arm/common/mcpm_head.S (low-level inbound CPU operations) and
496 low-level power-up code in mcpm_head.S. This could
497 involve CPU-specific setup code, but in the current
503 the case of an aborted cluster power-down).
506 functions due to the extra inter-CPU coordination which
510 the low-level power-up code in mcpm_head.S. This
511 typically involves platform-specific setup code,
512 provided by the platform-specific power_up_setup
520 extended by replicating the cluster-level states for the
522 rules for the intermediate (non-outermost) cluster levels.
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531 Copyright (C) 2012-2013 Linaro Limited