Lines Matching full:pmu

2 NVIDIA Tegra SoC Uncore Performance Monitoring Unit (PMU)
14 PMU Driver
17 The PMUs in this document are based on ARM CoreSight PMU Architecture as
19 PMUs are managed by a common driver "arm-cs-arch-pmu". This driver describes
20 the available events and configuration of each PMU in sysfs. Please see the
21 sections below to get the sysfs path of each PMU. Like other uncore PMU drivers,
23 the PMU event. There is also "associated_cpus" sysfs attribute, which contains a
24 list of CPUs associated with the PMU instance.
28 SCF PMU
31 The SCF PMU monitors system level cache events, CPU traffic, and
33 :ref:`NVIDIA_Uncore_PMU_Traffic_Coverage_Section` for more info about the PMU
36 The events and configuration options of this PMU device are described in sysfs,
49 NVLink-C2C0 PMU
52 The NVLink-C2C0 PMU monitors incoming traffic from a GPU/CPU connected with
53 NVLink-C2C (Chip-2-Chip) interconnect. The type of traffic captured by this PMU
58   In this config, the PMU captures GPU ATS translated or EGM traffic from the GPU.
62   In this config, the PMU captures read and relaxed ordered (RO) writes from
66 the PMU traffic coverage.
68 The events and configuration options of this PMU device are described in sysfs,
93 PMU will monitor both ports by default if not specified.
105 NVLink-C2C1 PMU
108 The NVLink-C2C1 PMU monitors incoming traffic from a GPU connected with
109 NVLink-C2C (Chip-2-Chip) interconnect. This PMU captures untranslated GPU
110 traffic, in contrast with NvLink-C2C0 PMU that captures ATS translated traffic.
112 the PMU traffic coverage.
114 The events and configuration options of this PMU device are described in sysfs,
139 PMU will monitor both ports by default if not specified.
151 CNVLink PMU
154 The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets
155 to local memory. For PCIE traffic, this PMU captures read and relaxed ordered
157 for more info about the PMU traffic coverage.
159 The events and configuration options of this PMU device are described in sysfs,
165 socket 1 to 3. The PMU will monitor all remote sockets by default if not
170 The PMU can not distinguish the remote traffic initiator, therefore it does not
193 PCIE PMU
196 The PCIE PMU monitors all read/write traffic from PCIE root ports to
198 for more info about the PMU traffic coverage.
200 The events and configuration options of this PMU device are described in sysfs,
205 "root_port=0xF" corresponds to root port 0 to 3. The PMU will monitor all root
225 The PMU traffic coverage may vary dependent on the chip configuration:
256   | Following table contains traffic coverage of Grace SoC PMU in socket-A:
267    | Local        | PCIE  |NVLink-C2C0|NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
268    | SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |          | PMU      |
270    | Local GMEM   | PCIE  |    N/A    |NVLink-C2C1| SCF | SCF PMU  | CNVLink  |
271    |              | PMU   |           |PMU        | PMU |          | PMU      |
274    | SYSRAM/CMEM  | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
278    | over CNVLink | PMU   |PMU        |PMU        | PMU |   N/A    |   N/A    |
313   | Following table contains traffic coverage of Grace SoC PMU in socket-A:
324    | Local           |  PCIE PMU | SCF PMU | SCF PMU  | NVLink-C2C0 |
325    | SYSRAM/CMEM     |           |         |          | PMU         |
328    | SYSRAM/CMEM     |  PCIE PMU | SCF PMU |   N/A    |     N/A     |