Lines Matching +full:memory +full:- +full:to +full:- +full:memory
2 NUMA Memory Performance
8 Some platforms may have multiple types of memory attached to a compute
9 node. These disparate memory ranges may share some characteristics, such
13 A system supports such heterogeneous memory by grouping each memory type
15 characteristics. Some memory may share the same node as a CPU, and others
16 are provided as memory only nodes. While memory only nodes do not provide
17 CPUs, they may still be local to one or more compute nodes relative to
19 nodes with local memory and a memory only node for each of compute node::
21 +------------------+ +------------------+
22 | Compute Node 0 +-----+ Compute Node 1 |
24 +--------+---------+ +--------+---------+
26 +--------+---------+ +--------+---------+
28 +------------------+ +--------+---------+
30 A "memory initiator" is a node containing one or more devices such as
31 CPUs or separate memory I/O devices that can initiate memory requests.
32 A "memory target" is a node containing one or more physical address
33 ranges accessible from one or more memory initiators.
35 When multiple memory initiators exist, they may not all have the same
36 performance when accessing a given memory target. Each initiator-target
37 pair may be organized into different ranked access classes to represent
38 this relationship. The highest performing initiator to a given target
39 is considered to be one of that target's local initiators, and given
42 memory targets.
44 To aid applications matching memory targets with their initiators, the
45 kernel provides symlinks to each other. The following example lists the
46 relationship for the access class "0" memory initiators and targets::
48 # symlinks -v /sys/devices/system/node/nodeX/access0/targets/
49 relative: /sys/devices/system/node/nodeX/access0/targets/nodeY -> ../../nodeY
51 # symlinks -v /sys/devices/system/node/nodeY/access0/initiators/
52 relative: /sys/devices/system/node/nodeY/access0/initiators/nodeX -> ../../nodeX
54 A memory initiator may have multiple memory targets in the same access
55 class. The target memory's initiators in a given class indicate the
56 nodes' access characteristics share the same performance relative to other
60 The access class "1" is used to allow differentiation between initiators
68 Applications may wish to consider which node they want their memory to
72 memory node's access class 0 initiators as follows::
82 # tree -P "read*|write*" /sys/devices/system/node/nodeY/access0/initiators/
84 |-- read_bandwidth
85 |-- read_latency
86 |-- write_bandwidth
87 `-- write_latency
93 The values reported here correspond to the rated latency and bandwidth
96 Access class 1 takes the same form but only includes values for CPU to
97 memory activity.
102 System memory may be constructed in a hierarchy of elements with various
103 performance characteristics in order to provide large address space of
104 slower performing memory cached by a smaller higher performing memory. The
105 system physical addresses memory initiators are aware of are provided
106 by the last memory level in the hierarchy. The system meanwhile uses
107 higher performing memory to transparently cache access to progressively
110 The term "far memory" is used to denote the last level memory in the
112 initiator access, and the term "near memory" represents the fastest
116 L1, L2, L3) uses the CPU-side view where each increased level is lower
117 performing. In contrast, the memory cache level is centric to the last
118 level memory, so the higher numbered cache level corresponds to memory
119 nearer to the CPU, and further from far memory.
121 The memory-side caches are not directly addressable by software. When
123 near memory cache if it is present. If it is not present, the system
124 accesses the next level of memory until there is either a hit in that
125 cache level, or it reaches far memory.
127 An application does not need to know about caching attributes in order
128 to use the system. Software may optionally query the memory cache
129 attributes in order to maximize the performance out of such a setup.
130 If the system provides a way for the kernel to discover this information,
131 for example with ACPI HMAT (Heterogeneous Memory Attribute Table),
132 the kernel will append these attributes to the NUMA node memory target.
134 When the kernel first registers a memory cache with a node, the kernel
140 a memory-side cache, or that information is not accessible to the kernel.
151 software to query::
155 |-- index1
156 | |-- indexing
157 | |-- line_size
158 | |-- size
159 | `-- write_policy
161 The "indexing" will be 0 if it is a direct-mapped cache, and non-zero
162 for any other indexed based, multi-way associativity.
169 The "write_policy" will be 0 for write-back, and non-zero for
170 write-through caching.
176 - Section 5.2.27