Lines Matching full:memory
2 NUMA Memory Performance
8 Some platforms may have multiple types of memory attached to a compute
9 node. These disparate memory ranges may share some characteristics, such
13 A system supports such heterogeneous memory by grouping each memory type
15 characteristics. Some memory may share the same node as a CPU, and others
16 are provided as memory only nodes. While memory only nodes do not provide
19 nodes with local memory and a memory only node for each of compute node::
30 A "memory initiator" is a node containing one or more devices such as
31 CPUs or separate memory I/O devices that can initiate memory requests.
32 A "memory target" is a node containing one or more physical address
33 ranges accessible from one or more memory initiators.
35 When multiple memory initiators exist, they may not all have the same
36 performance when accessing a given memory target. Each initiator-target
42 memory targets.
44 To aid applications matching memory targets with their initiators, the
46 relationship for the access class "0" memory initiators and targets::
54 A memory initiator may have multiple memory targets in the same access
55 class. The target memory's initiators in a given class indicate the
68 Applications may wish to consider which node they want their memory to
72 memory node's access class 0 initiators as follows::
97 memory activity.
102 System memory may be constructed in a hierarchy of elements with various
104 slower performing memory cached by a smaller higher performing memory. The
105 system physical addresses memory initiators are aware of are provided
106 by the last memory level in the hierarchy. The system meanwhile uses
107 higher performing memory to transparently cache access to progressively
110 The term "far memory" is used to denote the last level memory in the
112 initiator access, and the term "near memory" represents the fastest
117 performing. In contrast, the memory cache level is centric to the last
118 level memory, so the higher numbered cache level corresponds to memory
119 nearer to the CPU, and further from far memory.
121 The memory-side caches are not directly addressable by software. When
123 near memory cache if it is present. If it is not present, the system
124 accesses the next level of memory until there is either a hit in that
125 cache level, or it reaches far memory.
128 to use the system. Software may optionally query the memory cache
131 for example with ACPI HMAT (Heterogeneous Memory Attribute Table),
132 the kernel will append these attributes to the NUMA node memory target.
134 When the kernel first registers a memory cache with a node, the kernel
140 a memory-side cache, or that information is not accessible to the kernel.