Lines Matching refs:signal

70     Mapping of the incoming bits in the signal to the colour bits of the pixels.
88     pixel clock is running and the DE signal is moving.
129     If the incoming video signal does not contain synchronization VSYNC and
132     (pixels with deasserted Data Enable signal) are necessary to generate the
136     If the incoming video signal does not contain synchronization VSYNC and
139     (pixels with deasserted Data Enable signal) are necessary to generate the
153     Width of the HSYNC signal in PCLK clock ticks.
159     Width of the VSYNC signal in PCLK clock ticks.
165     Number of PCLK pulses between deassertion of the HSYNC signal and the first
173     line (marked by DE=1) and assertion of the HSYNC signal.
179     Number of video lines between deassertion of the VSYNC signal and the video
187     by DE=1) and assertion of the VSYNC signal.
241     Output video signal frame rate limit in frames per second. Due to
244     Using this parameter one can limit the frame rate by "crippling" the signal
246     the signal appears like having the exact frame rate to the connected display.
250     HSYNC signal polarity.
256     VSYNC signal polarity.
262     DE signal polarity.
278     Width of the HSYNC signal in pixels. The default value is 40.
281     Width of the VSYNC signal in video lines. The default value is 20.
284     Number of PCLK pulses between deassertion of the HSYNC signal and the first
289     line (marked by DE=1) and assertion of the HSYNC signal. The default value
293     Number of video lines between deassertion of the VSYNC signal and the video
298     by DE=1) and assertion of the VSYNC signal. The default value is 30.
363 signal level status capability. The following scan elements are available:
376 The iio device can operate either in "raw" mode where you can fetch the signal
378 In the triggered buffer mode you can follow the signal level changes (activity