Lines Matching +full:video +full:- +full:mode
1 .. SPDX-License-Identifier: GPL-2.0
7 ---------------
9 The mgb4 driver provides a sysfs interface, that is used to configure video
11 device can be opened) and obtain the video device/stream status.
13 There are two types of parameters - global / PCI card related, found under
23 | 0 - No module present
24 | 1 - FPDL3
25 | 2 - GMSL (one serializer, two daisy chained deserializers)
26 | 3 - GMSL (one serializer, two deserializers)
27 | 4 - GMSL (two deserializers with two daisy chain outputs)
35 | 1 - FPDL3
36 | 2 - GMSL
44 PRODUCT-REVISION-SERIES-SERIAL
57 | 0 - single
58 | 1 - dual (default)
63 | 0 - OLDI/JEIDA
64 | 1 - SPWG/VESA (default)
67 Video link status. If the link is locked, chips are properly connected and
69 an active video stream.
74 | 0 - unlocked
75 | 1 - locked
78 Video stream status. A stream is detected if the link is locked, the input
84 | 0 - not detected
85 | 1 - detected
88 Video stream width. This is the actual width as detected by the HW.
94 Video stream height. This is the actual height as detected by the HW.
100 The type of VSYNC pulses as detected by the video format detector.
105 | 0 - active low
106 | 1 - active high
107 | 2 - not available
110 The type of HSYNC pulses as detected by the video format detector.
115 | 0 - active low
116 | 1 - active high
117 | 2 - not available
120 If the incoming video signal does not contain synchronization VSYNC and
127 If the incoming video signal does not contain synchronization VSYNC and
157 valid pixel in the video line (marked by DE=1).
163 Number of PCLK pulses between the end of the last valid pixel in the video
170 Number of video lines between deassertion of the VSYNC signal and the video
177 Number of video lines between the end of the last valid pixel line (marked
189 | 0 - PLL < 50MHz (default)
190 | 1 - PLL >= 50MHz
202 Output video source. If set to 0 or 1, the source is the corresponding card
204 is the corresponding v4l2 video output device. The default is
207 | 0 - input 0
208 | 1 - input 1
209 | 2 - v4l2 output 0
210 | 3 - v4l2 output 1
232 Output video signal frame rate limit in frames per second. Due to
243 | 0 - active low (default)
244 | 1 - active high
249 | 0 - active low (default)
250 | 1 - active high
255 | 0 - active low
256 | 1 - active high (default)
259 Output pixel clock frequency. Allowed values are between 25000-190000(kHz)
260 and there is a non-linear stepping between two consecutive allowed
272 Width of the VSYNC signal in video lines. The default value is 20.
276 valid pixel in the video line (marked by DE=1). The default value is 50.
279 Number of PCLK pulses between the end of the last valid pixel in the video
284 Number of video lines between deassertion of the VSYNC signal and the video
288 Number of video lines between the end of the last valid pixel line (marked
297 | 0 - auto (default)
298 | 1 - single
299 | 2 - dual
307 | 0 - auto (default)
308 | 1 - single
309 | 2 - dual
315 GMSL speed mode.
317 | 0 - 12Gb/s (default)
318 | 1 - 6Gb/s
319 | 2 - 3Gb/s
320 | 3 - 1.5Gb/s
323 The GMSL multi-stream contains up to four video streams. This parameter
324 selects which stream is captured by the video input. The value is the
325 zero-based index of the stream. The default stream id is 0.
333 | 0 - disabled
334 | 1 - enabled (default)
337 --------------
340 - mgb4-fw.X - FPGA firmware.
341 - mgb4-data.X - Factory settings, e.g. card serial number.
343 The *mgb4-fw* partition is writable and is used for FW updates, *mgb4-data* is
344 read-only. The *X* attached to the partition name represents the card number.
346 also have a third partition named *mgb4-flash* available in the system. This
351 --------------
359 | bit 1 - trigger 1 pending
360 | bit 2 - trigger 2 pending
361 | bit 5 - trigger 1 level
362 | bit 6 - trigger 2 level
367 The iio device can operate either in "raw" mode where you can fetch the signal
368 levels (activity bits 5 and 6) using sysfs access or in triggered buffer mode.
369 In the triggered buffer mode you can follow the signal level changes (activity
371 will also get the exact trigger event time that can be matched to a video frame
372 (every mgb4 video frame has a timestamp with the same clock source).
375 no sense to get the pending bits in raw mode or the level bits in the triggered
376 buffer mode - the values do not represent valid data in such case.*