Lines Matching +full:input +full:- +full:clock +full:- +full:frequency
1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| 2023 - 2025 Digiteq Automotive
12 card capable of capturing and generating FPD-Link III and GMSL2/3 video streams
16 ---------------
22 There are two types of parameters - global / PCI card related, found under
32 | 0 - No module present
33 | 1 - FPDL3
34 | 2 - GMSL (one serializer, two daisy chained deserializers)
35 | 3 - GMSL (one serializer, two deserializers)
36 | 4 - GMSL (two deserializers with two daisy chain outputs)
44 | 1 - FPDL3
45 | 2 - GMSL
53 PRODUCT-REVISION-SERIES-SERIAL
57 Common FPDL3/GMSL input parameters
61 Input number ID, zero based.
66 | 0 - single
67 | 1 - dual (default)
72 | 0 - OLDI/JEIDA
73 | 1 - SPWG/VESA (default)
83 | 0 - unlocked
84 | 1 - locked
87 Video stream status. A stream is detected if the link is locked, the input
88 pixel clock is running and the DE signal is moving.
93 | 0 - not detected
94 | 1 - detected
114 | 0 - active low
115 | 1 - active high
116 | 2 - not available
124 | 0 - active low
125 | 1 - active high
126 | 2 - not available
144 Input pixel clock frequency in kHz.
150 a valid frequency here.*
153 Width of the HSYNC signal in PCLK clock ticks.
159 Width of the VSYNC signal in PCLK clock ticks.
193 PLL frequency range of the OLDI input clock generator. The PLL frequency is
194 derived from the Pixel Clock Frequency (PCLK) and is equal to PCLK if
198 | 0 - PLL < 50MHz (default)
199 | 1 - PLL >= 50MHz
201 *Note: This parameter can not be changed while the input v4l2 device is
212 input and the v4l2 output devices are disabled. If set to 2 or 3, the source
216 | 0 - input 0
217 | 1 - input 1
218 | 2 - v4l2 output 0
219 | 3 - v4l2 output 1
221 *Note: This parameter can not be changed while ANY of the input/output v4l2
242 the limited output pixel clock steps, the card can not always generate
252 | 0 - active low (default)
253 | 1 - active high
258 | 0 - active low (default)
259 | 1 - active high
264 | 0 - active low
265 | 1 - active high (default)
268 Output pixel clock frequency. Allowed values are between 25000-190000(kHz)
269 and there is a non-linear stepping between two consecutive allowed
270 frequencies. The driver finds the nearest allowed frequency to the given
272 frequency set by the driver. The default frequency is 61150kHz.
300 FPDL3 specific input parameters
304 Number of deserializer input lines.
306 | 0 - auto (default)
307 | 1 - single
308 | 2 - dual
316 | 0 - auto (default)
317 | 1 - single
318 | 2 - dual
320 GMSL specific input parameters
326 | 0 - 12Gb/s (default)
327 | 1 - 6Gb/s
328 | 2 - 3Gb/s
329 | 3 - 1.5Gb/s
332 The GMSL multi-stream contains up to four video streams. This parameter
333 selects which stream is captured by the video input. The value is the
334 zero-based index of the stream. The default stream id is 0.
336 *Note: This parameter can not be changed while the input v4l2 device is
342 | 0 - disabled
343 | 1 - enabled (default)
346 --------------
349 - mgb4-fw.X - FPGA firmware.
350 - mgb4-data.X - Factory settings, e.g. card serial number.
352 The *mgb4-fw* partition is writable and is used for FW updates, *mgb4-data* is
353 read-only. The *X* attached to the partition name represents the card number.
355 also have a third partition named *mgb4-flash* available in the system. This
360 --------------
368 | bit 1 - trigger 1 pending
369 | bit 2 - trigger 2 pending
370 | bit 5 - trigger 1 level
371 | bit 6 - trigger 2 level
381 (every mgb4 video frame has a timestamp with the same clock source).
385 buffer mode - the values do not represent valid data in such case.*