Lines Matching full:affected

8 Affected processors
23 Whether a processor is affected or not can be read out from the MDS
26 Not all processors are affected by all variants of MDS, but the mitigation
100      * - 'Not affected'
135 The kernel detects the affected CPUs and the presence of the microcode
138 If a CPU is affected and the microcode is available, then the kernel
148   The mitigation for MDS clears the affected CPU buffers on return to user
152   is only affected by MSBDS and not any other MDS variant, because the
155   For CPUs which are only affected by MSBDS the user space, guest and idle
156   transition mitigations are sufficient and SMT is not affected.
166   - CPU is affected by L1TF:
178   - CPU is not affected by L1TF:
188    Don't care   No    Don't care    N/A          Not affected
210   The XEON PHI processor family is affected by MSBDS which can be exploited
216   XEON PHI is not affected by the other MDS variants and MSBDS is mitigated
217   before the CPU enters a idle state. As XEON PHI is not affected by L1TF
226   means on CPUs which are affected by MFBDS or MLPDS it is necessary to
227   disable SMT for full protection. These are most of the affected CPUs; the
261 that are affected by both TAA (TSX Asynchronous Abort) and MDS,