Lines Matching +full:pci +full:- +full:ep

1 .. SPDX-License-Identifier: GPL-2.0
4 PCI NTB Function
9 PCI Non-Transparent Bridges (NTB) allow two host systems to communicate
16 PCI NTB Function allows two different systems (or hosts) to communicate
20 In the below diagram, PCI NTB function configures the SoC with multiple
21 PCI Endpoint (EP) instances in such a way that transactions from one EP
22 controller are routed to the other EP controller. Once PCI NTB function
23 configures the SoC with multiple EP instances, HOST1 and HOST2 can
26 .. code-block:: text
28 +-------------+ +-------------+
32 +------^------+ +------^------+
35 +---------|-------------------------------------------------|---------+
36 | +------v------+ +------v------+ |
38 | | EP | | EP | |
40 | | <-----------------------------------> | |
43 | | | SoC With Multiple EP Instances | | |
45 | +-------------+ +-------------+ |
46 +---------------------------------------------------------------------+
59 --------------
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74 +------------------------+
76 +------------------------+
78 +------------------------+
80 +------------------------+
82 +------------------------+
84 +------------------------+
86 +------------------------+
88 +------------------------+
90 +------------------------+
92 +------------------------+
94 +------------------------+
96 +------------------------+
98 +------------------------+
100 +------------------------+
102 +------------------------+
104 +------------------------+
106 +------------------------+
115 MSI/MSI-X vectors (i.e., initialize the MSI/MSI-X Capability in the
118 to the MSI/MSI-X address programmed by the host. The ARGUMENT
120 lower 16 bits) and if MSI or MSI-X should be configured (BIT 16).
132 bound to the EP device on the host side. Once the endpoint
178 in order to raise doorbell. EPF NTB can use either MSI or MSI-X to
179 ring doorbell (MSI-X support will be added later). MSI uses same
180 address for all the interrupts and MSI-X can provide different
181 addresses for different interrupts. The MSI/MSI-X address is provided
182 by the host and the address it gives is based on the MSI/MSI-X
184 using GIC ITS will have the same MSI-X address for all the interrupts.
186 for both MSI and MSI-X, EPF NTB allocates a separate region in the
188 be mapped to the MSI/MSI-X address provided by the host. If a host
197 This holds the MSI/MSI-X data that has to be written to MSI address
202 ---------------------
214 -------------------
219 --------------
233 If one 32-bit BAR is allocated for each of these regions, the scheme would
248 be enough BARs for all the regions in a platform that supports only 64-bit
272 ----------------------------------
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276 +-----------------+------->+------------------+ +-----------------+
278 +-----------------+----+ +------------------+<-------+-----------------+
280 +-----------------+ +-->+------------------+<-------+-----------------+
282 +-----------------+ +-----------------+
284 +-----------------+ +-----------------+
286 +-----------------+ +-----------------+
288 +-----------------+ +-----------------+
289 EP CONTROLLER 1 EP CONTROLLER 2
292 EP controller 1) allocated in local memory. The HOST1 can access the config
293 region and scratchpad region (self scratchpad) using BAR0 of EP controller 1.
294 The peer host (HOST2 connected to EP controller 2) can also access this
295 scratchpad region (peer scratchpad) using BAR1 of EP controller 2. This
300 ----------------------------------
302 .. code-block:: text
304 +-----------------+ +----->+----------------+-----------+-----------------+
305 | BAR0 | | | Doorbell 1 +-----------> MSI-X ADDRESS 1 |
306 +-----------------+ | +----------------+ +-----------------+
307 | BAR1 | | | Doorbell 2 +---------+ | |
308 +-----------------+----+ +----------------+ | | |
309 | BAR2 | | Doorbell 3 +-------+ | +-----------------+
310 +-----------------+----+ +----------------+ | +-> MSI-X ADDRESS 2 |
311 | BAR3 | | | Doorbell 4 +-----+ | +-----------------+
312 +-----------------+ | |----------------+ | | | |
313 | BAR4 | | | | | | +-----------------+
314 +-----------------+ | | MW1 +---+ | +-->+ MSI-X ADDRESS 3||
315 | BAR5 | | | | | | +-----------------+
316 +-----------------+ +----->-----------------+ | | | |
317 EP CONTROLLER 1 | | | | +-----------------+
318 | | | +---->+ MSI-X ADDRESS 4 |
319 +----------------+ | +-----------------+
320 EP CONTROLLER 2 | | |
322 +-------> MW1 |
325 +-----------------+
331 +-----------------+
332 PCI Address Space
338 memory window 1 regions are allocated in EP controller 2 outbound (OB) address
341 Mapping from EP controller 2 OB space to PCI address space is done when HOST2
345 ---------------------------------