Lines Matching +full:2 +full:x32 +full:- +full:bit
1 What: /sys/bus/platform/drivers/zynqmp_fpga_manager/firmware:zynqmp-firmware:pcap/status
7 of the FPGA device. Each bit position in the status value is
9 https://docs.xilinx.com/v/u/en-US/ug570-ultrascale-configuration
12 BIT(0) 0: No CRC error
15 BIT(1) 0: Decryptor security not set
18 BIT(2) 0: MMCMs/PLLs are not locked
21 BIT(3) 0: DCI not matched
24 BIT(4) 0: Start-up sequence has not finished
25 1: Start-up sequence has finished
27 BIT(5) 0: All I/Os are placed in High-Z state
30 BIT(6) 0: Flip-flops and block RAM are write disabled
31 1: Flip-flops and block RAM are write enabled
33 BIT(7) 0: GHIGH_B_STATUS asserted
36 BIT(8) to BIT(10) Status of the mode pins
38 BIT(11) 0: Initialization has not finished
41 BIT(12) Value on INIT_B_PIN pin
43 BIT(13) 0: Signal not released
46 BIT(14) Value on DONE_PIN pin.
48 BIT(15) 0: No IDCODE_ERROR
51 BIT(16) 0: No SECURITY_ERROR
54 BIT(17) System Monitor over-temperature if set
56 BIT(18) to BIT(20) Start-up state machine (0 to 7)
59 Phase 2 = 011
66 BIT(25) to BIT(26) Indicates the detected bus width
70 11 = x32