Lines Matching full:unit
111 dmar_pglvl_supported(struct dmar_unit *unit, int pglvl) in dmar_pglvl_supported() argument
118 if ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) in dmar_pglvl_supported()
153 dmar_maxaddr2mgaw(struct dmar_unit *unit, iommu_gaddr_t maxaddr, bool allow_less) in dmar_maxaddr2mgaw() argument
159 (DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) != 0) in dmar_maxaddr2mgaw()
165 } while ((DMAR_CAP_SAGAW(unit->hw_cap) & sagaw_bits[i].cap) in dmar_maxaddr2mgaw()
203 calc_am(struct dmar_unit *unit, iommu_gaddr_t base, iommu_gaddr_t size, in calc_am() argument
209 for (am = DMAR_CAP_MAMV(unit->hw_cap);; am--) { in calc_am()
224 dmar_flush_transl_to_ram(struct dmar_unit *unit, void *dst, size_t sz) in dmar_flush_transl_to_ram() argument
227 if (DMAR_IS_COHERENT(unit)) in dmar_flush_transl_to_ram()
237 dmar_flush_pte_to_ram(struct dmar_unit *unit, iommu_pte_t *dst) in dmar_flush_pte_to_ram() argument
240 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); in dmar_flush_pte_to_ram()
244 dmar_flush_ctx_to_ram(struct dmar_unit *unit, dmar_ctx_entry_t *dst) in dmar_flush_ctx_to_ram() argument
247 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); in dmar_flush_ctx_to_ram()
251 dmar_flush_root_to_ram(struct dmar_unit *unit, dmar_root_entry_t *dst) in dmar_flush_root_to_ram() argument
254 dmar_flush_transl_to_ram(unit, dst, sizeof(*dst)); in dmar_flush_root_to_ram()
262 dmar_load_root_entry_ptr(struct dmar_unit *unit) in dmar_load_root_entry_ptr() argument
271 DMAR_ASSERT_LOCKED(unit); in dmar_load_root_entry_ptr()
273 VM_OBJECT_RLOCK(unit->ctx_obj); in dmar_load_root_entry_ptr()
274 root_entry = vm_page_lookup(unit->ctx_obj, 0); in dmar_load_root_entry_ptr()
275 VM_OBJECT_RUNLOCK(unit->ctx_obj); in dmar_load_root_entry_ptr()
276 dmar_write8(unit, DMAR_RTADDR_REG, VM_PAGE_TO_PHYS(root_entry)); in dmar_load_root_entry_ptr()
277 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SRTP); in dmar_load_root_entry_ptr()
278 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_RTPS) in dmar_load_root_entry_ptr()
288 dmar_inv_ctx_glob(struct dmar_unit *unit) in dmar_inv_ctx_glob() argument
296 DMAR_ASSERT_LOCKED(unit); in dmar_inv_ctx_glob()
297 KASSERT(!unit->qi_enabled, ("QI enabled")); in dmar_inv_ctx_glob()
305 dmar_write8(unit, DMAR_CCMD_REG, DMAR_CCMD_ICC | DMAR_CCMD_CIRG_GLOB); in dmar_inv_ctx_glob()
306 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_CCMD_REG + 4) & DMAR_CCMD_ICC32) in dmar_inv_ctx_glob()
315 dmar_inv_iotlb_glob(struct dmar_unit *unit) in dmar_inv_iotlb_glob() argument
319 DMAR_ASSERT_LOCKED(unit); in dmar_inv_iotlb_glob()
320 KASSERT(!unit->qi_enabled, ("QI enabled")); in dmar_inv_iotlb_glob()
322 reg = 16 * DMAR_ECAP_IRO(unit->hw_ecap); in dmar_inv_iotlb_glob()
324 dmar_write8(unit, reg + DMAR_IOTLB_REG_OFF, DMAR_IOTLB_IVT | in dmar_inv_iotlb_glob()
326 DMAR_WAIT_UNTIL(((dmar_read4(unit, reg + DMAR_IOTLB_REG_OFF + 4) & in dmar_inv_iotlb_glob()
336 dmar_flush_write_bufs(struct dmar_unit *unit) in dmar_flush_write_bufs() argument
340 DMAR_ASSERT_LOCKED(unit); in dmar_flush_write_bufs()
345 KASSERT((unit->hw_cap & DMAR_CAP_RWBF) != 0, in dmar_flush_write_bufs()
346 ("dmar%d: no RWBF", unit->iommu.unit)); in dmar_flush_write_bufs()
348 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_WBF); in dmar_flush_write_bufs()
349 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_WBFS) in dmar_flush_write_bufs()
361 dmar_disable_protected_regions(struct dmar_unit *unit) in dmar_disable_protected_regions() argument
366 DMAR_ASSERT_LOCKED(unit); in dmar_disable_protected_regions()
369 if ((unit->hw_cap & (DMAR_CAP_PLMR | DMAR_CAP_PHMR)) == 0) in dmar_disable_protected_regions()
372 reg = dmar_read4(unit, DMAR_PMEN_REG); in dmar_disable_protected_regions()
377 dmar_write4(unit, DMAR_PMEN_REG, reg); in dmar_disable_protected_regions()
378 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_PMEN_REG) & DMAR_PMEN_PRS) in dmar_disable_protected_regions()
385 dmar_enable_translation(struct dmar_unit *unit) in dmar_enable_translation() argument
389 DMAR_ASSERT_LOCKED(unit); in dmar_enable_translation()
390 unit->hw_gcmd |= DMAR_GCMD_TE; in dmar_enable_translation()
391 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); in dmar_enable_translation()
392 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) in dmar_enable_translation()
398 dmar_disable_translation(struct dmar_unit *unit) in dmar_disable_translation() argument
402 DMAR_ASSERT_LOCKED(unit); in dmar_disable_translation()
403 unit->hw_gcmd &= ~DMAR_GCMD_TE; in dmar_disable_translation()
404 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); in dmar_disable_translation()
405 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_TES) in dmar_disable_translation()
411 dmar_load_irt_ptr(struct dmar_unit *unit) in dmar_load_irt_ptr() argument
416 DMAR_ASSERT_LOCKED(unit); in dmar_load_irt_ptr()
417 irta = unit->irt_phys; in dmar_load_irt_ptr()
418 if (DMAR_X2APIC(unit)) in dmar_load_irt_ptr()
420 s = fls(unit->irte_cnt) - 2; in dmar_load_irt_ptr()
421 KASSERT(unit->irte_cnt >= 2 && s <= DMAR_IRTA_S_MASK && in dmar_load_irt_ptr()
422 powerof2(unit->irte_cnt), in dmar_load_irt_ptr()
423 ("IRTA_REG_S overflow %x", unit->irte_cnt)); in dmar_load_irt_ptr()
425 dmar_write8(unit, DMAR_IRTA_REG, irta); in dmar_load_irt_ptr()
426 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd | DMAR_GCMD_SIRTP); in dmar_load_irt_ptr()
427 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRTPS) in dmar_load_irt_ptr()
433 dmar_enable_ir(struct dmar_unit *unit) in dmar_enable_ir() argument
437 DMAR_ASSERT_LOCKED(unit); in dmar_enable_ir()
438 unit->hw_gcmd |= DMAR_GCMD_IRE; in dmar_enable_ir()
439 unit->hw_gcmd &= ~DMAR_GCMD_CFI; in dmar_enable_ir()
440 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); in dmar_enable_ir()
441 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) in dmar_enable_ir()
447 dmar_disable_ir(struct dmar_unit *unit) in dmar_disable_ir() argument
451 DMAR_ASSERT_LOCKED(unit); in dmar_disable_ir()
452 unit->hw_gcmd &= ~DMAR_GCMD_IRE; in dmar_disable_ir()
453 dmar_write4(unit, DMAR_GCMD_REG, unit->hw_gcmd); in dmar_disable_ir()
454 DMAR_WAIT_UNTIL(((dmar_read4(unit, DMAR_GSTS_REG) & DMAR_GSTS_IRES) in dmar_disable_ir()
484 ("dmar%d barrier %d missing done", dmar->iommu.unit, in dmar_barrier_enter()
502 ("dmar%d barrier %d missed entry", dmar->iommu.unit, barrier_id)); in dmar_barrier_exit()