Lines Matching full:468
93 #define SPR_XER 0x001 /* 468 Fixed Point Exception Register */
97 #define SPR_LR 0x008 /* 468 Link Register */
98 #define SPR_CTR 0x009 /* 468 Count Register */
123 #define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */
124 #define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */
167 #define SPR_SPRG0 0x110 /* 468 SPR General 0 */
168 #define SPR_SPRG1 0x111 /* 468 SPR General 1 */
169 #define SPR_SPRG2 0x112 /* 468 SPR General 2 */
170 #define SPR_SPRG3 0x113 /* 468 SPR General 3 */
179 #define SPR_PVR 0x11f /* 468 Processor Version Register */
688 #define TBR_TBL 0x10c /* 468 Time Base Lower - read */
689 #define TBR_TBU 0x10d /* 468 Time Base Upper - read */
690 #define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */
691 #define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */