Lines Matching +full:- +full:- +full:enable +full:- +full:debug
1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
43 /* The following routines allow manipulation of the full 64-bit width
88 * architectures the SPR is valid on - 4 for 4xx series,
95 #define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */
96 #define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */
101 #define DSISR_DIRECT 0x80000000 /* Direct-store error exception */
104 #define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */
111 #define DSISR_MC_DERAT_MULTIHIT 0x00000800 /* D-ERAT multi-hit */
112 #define DSISR_MC_TLB_MULTIHIT 0x00000400 /* TLB multi-hit */
115 #define DSISR_MC_SLB_MULTIHIT 0x00000080 /* SLB Multi-hit detected (D-side) */
119 #define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */
120 #define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */
126 #define SRR1_ISI_NOEXECUTE 0x10000000 /* Memory marked no-execute */
151 #define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */
153 #define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */
161 #define FSCR_EBB 0x0000000000000080 /* Event-based branch available */
255 #define SPR_DBSR 0x130 /* ..8 Debug Status Register */
256 #define DBSR_IDE 0x80000000 /* Imprecise debug event. */
257 #define DBSR_UDE 0x40000000 /* Unconditional debug event. */
259 #define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */
260 #define DBSR_BRT 0x04000000 /* Branch taken debug event. */
261 #define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */
262 #define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */
271 #define DBSR_RET 0x00008000 /* Return debug event. */
284 #define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */
285 #define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */
286 #define SPR_DBCR2 0x136 /* ..8 Debug Control Register 2 */
302 #define LPCR_ILE (1ULL << 25) /* Interrupt Little-Endian (ISA 2.07) */
313 #define SPR_HMEER 0x151 /* Hypervisor Maintenance Exception Enable Register */
365 #define SPR_DBCR3 0x231 /* ..8 Debug Control Register 3 */
369 #define SPR_DBCR4 0x233 /* ..8 Debug Control Register 4 */
371 #define SPR_DBCR5 0x234 /* ..8 Debug Control Register 5 */
387 #define SPR_DBCR6 0x25b /* ..8 Debug Control Register 6 */
406 #define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */
407 #define SPR_MMCR0_PMAE 0x04000000 /* PM Alert Enable */
413 #define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */
415 #define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */
416 #define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */
420 #define SPR_MMCR0_FC56 0x00000010 /* Freeze Counters 5-6 */
435 #define SPR_MMCR1_P8_PMCNSEL_MASK(n) (0xffUL << ((3-(n))*8))
436 #define SPR_MMCR1_P8_PMCNSEL(n, v) ((unsigned long)(v) << ((3-(n))*8))
439 #define SPR_MMCR2_CNBIT(n, bit) ((bit) << (((5 - (n)) * 9) + 10))
453 #define M_TWB_L1TB 0xfffff000 /* level-1 translation base */
454 #define M_TWB_L1INDX 0x00000ffc /* level-1 index */
459 #define SPR_BESCRSU 0x321 /* .6. Branch Event Status and Control Set Register (upper 32-bit) */
461 #define SPR_BESCRRU 0x323 /* .6. Branch Event Status and Control Register (upper 32-bit) */
462 #define SPR_EBBHR 0x324 /* .6. Event-based Branch Handler Register */
463 #define SPR_EBBRR 0x325 /* .6. Event-based Branch Return Register */
466 #define SPR_LMSER 0x32e /* .6. Load Monitored Section Enable Register */
521 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
542 #define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */
543 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
544 #define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */
550 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
551 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
569 #define DBCR0_EDM 0x80000000 /* External Debug Mode */
570 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
576 #define DBCR0_IC 0x08000000 /* Instruction Completion debug event */
577 #define DBCR0_BT 0x04000000 /* Branch Taken debug event */
578 #define DBCR0_EDE 0x02000000 /* Exception Debug Event */
579 #define DBCR0_TDE 0x01000000 /* Trap Debug Event */
580 #define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */
581 #define DBCR0_IA2 0x00400000 /* IAC 2 debug event */
582 #define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */
584 #define DBCR0_IA3 0x00080000 /* IAC 3 debug event */
585 #define DBCR0_IA4 0x00040000 /* IAC 4 debug event */
586 #define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */
588 #define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */
589 #define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */
590 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
595 #define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */
596 #define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */
597 #define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */
598 #define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/
601 #define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */
602 #define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */
603 #define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */
604 #define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */
616 #define L2CR_L2E 0x80000000 /* 0: L2 enable */
617 #define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */
618 #define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */
623 #define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */
630 #define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */
634 #define L2CR_L2DO 0x00400000 /* 9: L2 data-only.
638 #define L2CR_L2IO_7450 0x00010000 /* 11: L2 instruction-only (MPC745x). */
639 #define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable).
641 L2ZZ (low-power mode) signal. */
642 #define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */
644 #define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */
645 #define L2CR_L2DO_7450 0x00010000 /* 15: L2 data-only (MPC745x). */
651 #define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */
653 #define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */
657 #define L3CR_L3E 0x80000000 /* 0: L3 enable */
658 #define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */
685 #define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */
689 #define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */
690 #define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */
693 #define TBR_TBL 0x10c /* 468 Time Base Lower - read */
694 #define TBR_TBU 0x10d /* 468 Time Base Upper - read */
695 #define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */
696 #define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */
701 /* The first five countable [non-]events are common to many PMC's */
719 #define MCSR_NMI 0x00100000 /* Non-maskable interrupt */
730 #define ESR_PIL 0x08000000 /* Program interrupt - illegal */
731 #define ESR_PPR 0x04000000 /* Program interrupt - privileged */
732 #define ESR_PTR 0x02000000 /* Program interrupt - trap */
743 #define SPR_DSRR0 0x23e /* ..8 574 Debug SRR0<E.ED> */
744 #define SPR_DSRR1 0x23f /* ..8 575 Debug SRR1<E.ED> */
823 #define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */
824 #define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */
825 #define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */
826 #define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */
827 #define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */
828 #define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */
829 #define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */
830 #define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */
831 #define SPR_MAS8 0x155 /* ..8 MMU Assist Register 8 Book-E/e500 */
839 #define DCR_L2DCDCRAI 0x0000 /* L2 D-Cache DCR Address Pointer */
840 #define DCR_L2DCDCRDI 0x0001 /* L2 D-Cache DCR Data Indirect */
845 #define L1CSR0_DCPE 0x00010000 /* Data Cache Parity Enable */
848 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
850 #define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */
854 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
858 #define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */
859 #define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */
864 #define BUCSR_BPEN 0x00000001 /* Branch Prediction Enable */