Lines Matching +full:interrupt +full:- +full:ranges
55 * MA 02110-1301, USA.
58 *------------------------------------------------------------------
61 /dts-v1/;
65 #address-cells = <2>;
66 #size-cells = <2>;
80 #address-cells = <1>;
81 #size-cells = <0>;
86 next-level-cache = <&L2>;
92 next-level-cache = <&L2>;
101 #address-cells = <2>;
102 #size-cells = <1>;
103 compatible = "fsl,elbc", "simple-bus";
106 interrupt-parent = <&mpic>;
108 ranges = <0x0 0x0 0x0 0xe8000000 0x08000000
117 #address-cells = <1>;
118 #size-cells = <1>;
119 compatible = "cfi-flash";
121 bank-width = <2>;
122 device-width = <1>;
126 read-only;
131 read-only;
136 read-only;
141 read-only;
150 read-only;
153 u-boot@7f80000 {
155 read-only;
160 #address-cells = <1>;
161 #size-cells = <1>;
162 compatible = "fsl,elbc-fcm-nand";
165 u-boot@0 {
167 read-only;
176 read-only;
185 read-only;
194 compatible = "fsl,elbc-fcm-nand";
199 compatible = "fsl,elbc-fcm-nand";
204 compatible = "fsl,elbc-fcm-nand";
210 #address-cells = <1>;
211 #size-cells = <1>;
213 compatible = "fsl,p2020-immr", "simple-bus";
214 ranges = <0x0 0 0xffe00000 0x100000>;
215 bus-frequency = <0>; // Filled out by uboot.
217 ecm-law@0 {
218 compatible = "fsl,ecm-law";
220 fsl,num-laws = <12>;
224 compatible = "fsl,p2020-ecm", "fsl,ecm";
227 interrupt-parent = <&mpic>;
230 memory-controller@2000 {
231 compatible = "fsl,p2020-memory-controller";
233 interrupt-parent = <&mpic>;
238 #address-cells = <1>;
239 #size-cells = <0>;
240 cell-index = <0>;
241 compatible = "fsl-i2c";
244 interrupt-parent = <&mpic>;
249 #address-cells = <1>;
250 #size-cells = <0>;
251 cell-index = <1>;
252 compatible = "fsl-i2c";
255 interrupt-parent = <&mpic>;
260 cell-index = <0>;
264 clock-frequency = <0>;
266 interrupt-parent = <&mpic>;
270 cell-index = <1>;
274 clock-frequency = <0>;
276 interrupt-parent = <&mpic>;
283 interrupt-parent = <&mpic>;
287 #address-cells = <1>;
288 #size-cells = <1>;
289 compatible = "fsl,eloplus-dma";
291 ranges = <0x0 0xc100 0x200>;
292 cell-index = <1>;
293 dma-channel@0 {
294 compatible = "fsl,eloplus-dma-channel";
296 cell-index = <0>;
297 interrupt-parent = <&mpic>;
300 dma-channel@80 {
301 compatible = "fsl,eloplus-dma-channel";
303 cell-index = <1>;
304 interrupt-parent = <&mpic>;
307 dma-channel@100 {
308 compatible = "fsl,eloplus-dma-channel";
310 cell-index = <2>;
311 interrupt-parent = <&mpic>;
314 dma-channel@180 {
315 compatible = "fsl,eloplus-dma-channel";
317 cell-index = <3>;
318 interrupt-parent = <&mpic>;
323 gpio: gpio-controller@f000 {
324 #gpio-cells = <2>;
325 compatible = "fsl,mpc8572-gpio";
328 interrupt-parent = <&mpic>;
329 gpio-controller;
332 L2: l2-cache-controller@20000 {
333 compatible = "fsl,p2020-l2-cache-controller";
335 cache-line-size = <32>; // 32 bytes
336 cache-size = <0x80000>; // L2, 512k
337 interrupt-parent = <&mpic>;
342 #address-cells = <1>;
343 #size-cells = <1>;
344 compatible = "fsl,eloplus-dma";
346 ranges = <0x0 0x21100 0x200>;
347 cell-index = <0>;
348 dma-channel@0 {
349 compatible = "fsl,eloplus-dma-channel";
351 cell-index = <0>;
352 interrupt-parent = <&mpic>;
355 dma-channel@80 {
356 compatible = "fsl,eloplus-dma-channel";
358 cell-index = <1>;
359 interrupt-parent = <&mpic>;
362 dma-channel@100 {
363 compatible = "fsl,eloplus-dma-channel";
365 cell-index = <2>;
366 interrupt-parent = <&mpic>;
369 dma-channel@180 {
370 compatible = "fsl,eloplus-dma-channel";
372 cell-index = <3>;
373 interrupt-parent = <&mpic>;
379 #address-cells = <1>;
380 #size-cells = <0>;
381 compatible = "fsl-usb2-dr";
383 interrupt-parent = <&mpic>;
389 #address-cells = <1>;
390 #size-cells = <1>;
391 cell-index = <0>;
396 ranges = <0x0 0x24000 0x1000>;
397 local-mac-address = [ 00 00 00 00 00 00 ];
399 interrupt-parent = <&mpic>;
400 tbi-handle = <&tbi0>;
401 phy-handle = <&phy0>;
402 phy-connection-type = "rgmii-id";
405 #address-cells = <1>;
406 #size-cells = <0>;
407 compatible = "fsl,gianfar-mdio";
410 phy0: ethernet-phy@0 {
411 interrupt-parent = <&mpic>;
415 phy1: ethernet-phy@1 {
416 interrupt-parent = <&mpic>;
420 phy2: ethernet-phy@2 {
421 interrupt-parent = <&mpic>;
425 tbi0: tbi-phy@11 {
427 device_type = "tbi-phy";
433 #address-cells = <1>;
434 #size-cells = <1>;
435 cell-index = <1>;
440 ranges = <0x0 0x25000 0x1000>;
441 local-mac-address = [ 00 00 00 00 00 00 ];
443 interrupt-parent = <&mpic>;
444 tbi-handle = <&tbi1>;
445 phy-handle = <&phy1>;
446 phy-connection-type = "rgmii-id";
449 #address-cells = <1>;
450 #size-cells = <0>;
451 compatible = "fsl,gianfar-tbi";
454 tbi1: tbi-phy@11 {
456 device_type = "tbi-phy";
462 #address-cells = <1>;
463 #size-cells = <1>;
464 cell-index = <2>;
469 ranges = <0x0 0x26000 0x1000>;
470 local-mac-address = [ 00 00 00 00 00 00 ];
472 interrupt-parent = <&mpic>;
473 tbi-handle = <&tbi2>;
474 phy-handle = <&phy2>;
475 phy-connection-type = "rgmii-id";
478 #address-cells = <1>;
479 #size-cells = <0>;
480 compatible = "fsl,gianfar-tbi";
483 tbi2: tbi-phy@11 {
485 device_type = "tbi-phy";
491 compatible = "fsl,p2020-esdhc", "fsl,esdhc";
494 interrupt-parent = <&mpic>;
495 /* Filled in by U-Boot */
496 clock-frequency = <0>;
504 interrupt-parent = <&mpic>;
505 fsl,num-channels = <4>;
506 fsl,channel-fifo-len = <24>;
507 fsl,exec-units-mask = <0xbfe>;
508 fsl,descriptor-types-mask = <0x3ab0ebf>;
512 interrupt-controller;
513 #address-cells = <0>;
514 #interrupt-cells = <2>;
516 compatible = "chrp,open-pic";
517 device_type = "open-pic";
521 compatible = "fsl,mpic-msi";
523 msi-available-ranges = <0 0x100>;
533 interrupt-parent = <&mpic>;
536 global-utilities@e0000 { //global utilities block
537 compatible = "fsl,p2020-guts";
539 fsl,has-rstcr;
544 compatible = "fsl,mpc8548-pcie";
546 #interrupt-cells = <1>;
547 #size-cells = <2>;
548 #address-cells = <3>;
550 bus-range = <0 255>;
551 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
553 clock-frequency = <33333333>;
554 interrupt-parent = <&mpic>;
556 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
557 interrupt-map = <
566 #size-cells = <2>;
567 #address-cells = <3>;
569 ranges = <0x2000000 0x0 0x80000000
580 compatible = "fsl,mpc8548-pcie";
582 #interrupt-cells = <1>;
583 #size-cells = <2>;
584 #address-cells = <3>;
586 bus-range = <0 255>;
587 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
589 clock-frequency = <33333333>;
590 interrupt-parent = <&mpic>;
592 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
593 interrupt-map = <
595 // IDSEL 0x11 func 0 - PCI slot 1
599 // IDSEL 0x11 func 1 - PCI slot 1
603 // IDSEL 0x11 func 2 - PCI slot 1
607 // IDSEL 0x11 func 3 - PCI slot 1
611 // IDSEL 0x11 func 4 - PCI slot 1
615 // IDSEL 0x11 func 5 - PCI slot 1
619 // IDSEL 0x11 func 6 - PCI slot 1
623 // IDSEL 0x11 func 7 - PCI slot 1
641 #size-cells = <2>;
642 #address-cells = <3>;
644 ranges = <0x2000000 0x0 0xa0000000
653 #size-cells = <2>;
654 #address-cells = <3>;
655 ranges = <0x2000000 0x0 0xa0000000
664 #interrupt-cells = <2>;
665 #size-cells = <1>;
666 #address-cells = <2>;
668 ranges = <0x1 0x0 0x1000000 0x0 0x0
670 interrupt-parent = <&i8259>;
672 i8259: interrupt-controller@20 {
676 interrupt-controller;
677 device_type = "interrupt-controller";
678 #address-cells = <0>;
679 #interrupt-cells = <2>;
682 interrupt-parent = <&mpic>;
686 #size-cells = <0>;
687 #address-cells = <1>;
690 interrupt-parent =
719 compatible = "fsl,mpc8548-pcie";
721 #interrupt-cells = <1>;
722 #size-cells = <2>;
723 #address-cells = <3>;
725 bus-range = <0 255>;
726 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
728 clock-frequency = <33333333>;
729 interrupt-parent = <&mpic>;
731 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
732 interrupt-map = <
741 #size-cells = <2>;
742 #address-cells = <3>;
744 ranges = <0x2000000 0x0 0xc0000000