Lines Matching +full:0 +full:x00b00000
55 #size-cells = <0>;
57 PowerPC,P1020@0 {
59 reg = <0x0>;
65 reg = <0x1>;
78 reg = <0 0xffe05000 0 0x1000>;
83 ranges = <0x0 0x0 0x0 0xef000000 0x01000000
84 0x1 0x0 0x0 0xffa00000 0x00040000
85 0x2 0x0 0x0 0xffb00000 0x00020000>;
87 nor@0,0 {
91 reg = <0x0 0x0 0x1000000>;
95 partition@0 {
98 reg = <0x0 0x00040000>;
105 reg = <0x00040000 0x00040000>;
112 reg = <0x00080000 0x00380000>;
119 reg = <0x00400000 0x00b00000>;
127 reg = <0x00f00000 0x00100000>;
133 nand@1,0 {
138 reg = <0x1 0x0 0x40000>;
140 partition@0 {
143 reg = <0x0 0x00100000>;
150 reg = <0x00100000 0x00100000>;
157 reg = <0x00200000 0x00400000>;
164 reg = <0x00600000 0x00400000>;
171 reg = <0x00a00000 0x00700000>;
177 reg = <0x01100000 0x00f00000>;
182 L2switch@2,0 {
186 reg = <0x2 0x0 0x20000>;
196 ranges = <0x0 0x0 0xffe00000 0x100000>;
197 bus-frequency = <0>; // Filled out by uboot.
199 ecm-law@0 {
201 reg = <0x0 0x1000>;
207 reg = <0x1000 0x1000>;
214 reg = <0x2000 0x1000>;
221 #size-cells = <0>;
222 cell-index = <0>;
224 reg = <0x3000 0x100>;
230 reg = <0x68>;
236 #size-cells = <0>;
239 reg = <0x3100 0x100>;
246 cell-index = <0>;
249 reg = <0x4500 0x100>;
250 clock-frequency = <0>;
259 reg = <0x4600 0x100>;
260 clock-frequency = <0>;
266 cell-index = <0>;
268 #size-cells = <0>;
270 reg = <0x7000 0x1000>;
271 interrupts = <59 0x2>;
275 fsl_m25p80@0 {
279 reg = <0>;
283 mode = <0>;
285 partition@0 {
287 reg = <0x0 0x00080000>;
294 reg = <0x00080000 0x00080000>;
301 reg = <0x00100000 0x00400000>;
308 reg = <0x00500000 0x00400000>;
315 reg = <0x00900000 0x00700000>;
324 reg = <0xf000 0x100>;
325 interrupts = <47 0x2>;
332 reg = <0x20000 0x1000>;
334 cache-size = <0x40000>; // L2,256K
343 reg = <0x21300 0x4>;
344 ranges = <0x0 0x21100 0x200>;
345 cell-index = <0>;
346 dma-channel@0 {
348 reg = <0x0 0x80>;
349 cell-index = <0>;
355 reg = <0x80 0x80>;
362 reg = <0x100 0x80>;
369 reg = <0x180 0x80>;
378 #size-cells = <0>;
380 reg = <0x24000 0x1000 0xb0030 0x4>;
382 phy0: ethernet-phy@0 {
385 reg = <0x0>;
391 reg = <0x1>;
397 #size-cells = <0>;
399 reg = <0x25000 0x1000 0xb1030 0x4>;
402 reg = <0x11>;
413 fsl,num_rx_queues = <0x8>;
414 fsl,num_tx_queues = <0x8>;
417 fixed-link = <1 1 1000 0 0>;
420 queue-group@0 {
423 reg = <0xb0000 0x1000>;
430 reg = <0xb4000 0x1000>;
441 fsl,num_rx_queues = <0x8>;
442 fsl,num_tx_queues = <0x8>;
449 queue-group@0 {
452 reg = <0xb1000 0x1000>;
459 reg = <0xb5000 0x1000>;
470 fsl,num_rx_queues = <0x8>;
471 fsl,num_tx_queues = <0x8>;
477 queue-group@0 {
480 reg = <0xb2000 0x1000>;
487 reg = <0xb6000 0x1000>;
494 #size-cells = <0>;
496 reg = <0x22000 0x1000>;
498 interrupts = <28 0x2>;
509 #size-cells = <0>;
511 reg = <0x23000 0x1000>;
513 interrupts = <46 0x2>;
520 reg = <0x2e000 0x1000>;
521 interrupts = <72 0x2>;
524 clock-frequency = <0>;
528 compatible = "fsl,sec3.1", "fsl,sec3.0", "fsl,sec2.4",
529 "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
530 reg = <0x30000 0x10000>;
535 fsl,exec-units-mask = <0xbfe>;
536 fsl,descriptor-types-mask = <0x3ab0ebf>;
541 #address-cells = <0>;
543 reg = <0x40000 0x40000>;
550 reg = <0x41600 0x80>;
551 msi-available-ranges = <0 0x100>;
553 0xe0 0
554 0xe1 0
555 0xe2 0
556 0xe3 0
557 0xe4 0
558 0xe5 0
559 0xe6 0
560 0xe7 0>;
566 reg = <0xe0000 0x1000>;
577 reg = <0 0xffe09000 0 0x1000>;
578 bus-range = <0 255>;
579 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
580 0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>;
584 pcie@0 {
585 reg = <0x0 0x0 0x0 0x0 0x0>;
589 ranges = <0x2000000 0x0 0xa0000000
590 0x2000000 0x0 0xa0000000
591 0x0 0x20000000
593 0x1000000 0x0 0x0
594 0x1000000 0x0 0x0
595 0x0 0x100000>;
605 reg = <0 0xffe0a000 0 0x1000>;
606 bus-range = <0 255>;
607 ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
608 0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>;
612 pcie@0 {
613 reg = <0x0 0x0 0x0 0x0 0x0>;
617 ranges = <0x2000000 0x0 0xc0000000
618 0x2000000 0x0 0xc0000000
619 0x0 0x20000000
621 0x1000000 0x0 0x0
622 0x1000000 0x0 0x0
623 0x0 0x100000>;