1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
10  * 1. Redistributions of source code must retain the above copyright
61 #define	IS_FDT	1
68 #define	DR_FE		(1 << 8)	/* Framing error */
69 #define	DR_PE		(1 << 9)	/* Parity error */
70 #define	DR_BE		(1 << 10)	/* Break error */
71 #define	DR_OE		(1 << 11)	/* Overrun error */
74 #define	FR_RXFE		(1 << 4)	/* Receive FIFO/reg empty */
75 #define	FR_TXFF		(1 << 5)	/* Transmit FIFO/reg full */
76 #define	FR_RXFF		(1 << 6)	/* Receive FIFO/reg full */
77 #define	FR_TXFE		(1 << 7)	/* Transmit FIFO/reg empty */
89 #define	LCR_H_FEN	(1 << 4)	/* FIFO mode enable */
90 #define	LCR_H_STP2	(1 << 3)	/* 2 stop frames at the end */
91 #define	LCR_H_EPS	(1 << 2)	/* Even parity select */
92 #define	LCR_H_PEN	(1 << 1)	/* Parity enable */
95 #define	CR_RXE		(1 << 9)	/* Receive enable */
96 #define	CR_TXE		(1 << 8)	/* Transmit enable */
97 #define	CR_UARTEN	(1 << 0)	/* UART enable */
103 #define	IFLS_LVL_1_8th	0		/* Interrupt at 1/8 full */
104 #define	IFLS_LVL_2_8th	1		/* Interrupt at 1/4 full */
105 #define	IFLS_LVL_4_8th	2		/* Interrupt at 1/2 full */
113 #define	UART_RXREADY	(1 << 4)	/* RX buffer full */
114 #define	UART_TXEMPTY	(1 << 5)	/* TX buffer empty */
115 #define	RIS_RTIM	(1 << 6)	/* Receive timeout */
116 #define	RIS_FE		(1 << 7)	/* Framing error interrupt status */
117 #define	RIS_PE		(1 << 8)	/* Parity error interrupt status */
118 #define	RIS_BE		(1 << 9)	/* Break error interrupt status */
119 #define	RIS_OE		(1 << 10)	/* Overrun interrupt status */
125 #define	UART_PIDREG_1	0x3f9		/* Peripheral ID register 1 */
145  * FIXME: actual register size is SoC-dependent, we need to handle it
148 	bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
150 	bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
153  * Low-level UART interface.
176 	 * Versions of QEMU before 41f7b58b634e (8.3) reported bogus values for  in uart_pl011_probe()
177 	 * this tabel. The PL011 IP is always 32-bits wide and should be shifted  in uart_pl011_probe()
178 	 * 2 to match the 4-byte size of the data. QEMU reported these values  in uart_pl011_probe()
180 	 * https://github.com/qemu/qemu/commit/41f7b58b634ec3b60ae874375d2bbb61d790971e  in uart_pl011_probe()
191 	if (bas->regshft == 0 || bas->regiowidth == 1) {  in uart_pl011_probe()
192 		bas->regshft = 2;  in uart_pl011_probe()
193 		bas->regiowidth = 4;  in uart_pl011_probe()
213 	/* As we know UART is disabled we may setup the line */  in uart_pl011_param()
241 	if (bas->rclk != 0 && baudrate != 0) {  in uart_pl011_param()
242 		baud = bas->rclk * 4 / baudrate;  in uart_pl011_param()
265 	if (bas->rclk == 0 && baudrate > 0 && bas->rclk_guess) {  in uart_pl011_param()
270 		bas->rclk = (div * baudrate) / 4;  in uart_pl011_param()
335  * High-level UART interface.
418 	bas = &sc->sc_bas;  in uart_pl011_bus_attach()
421 	psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY);  in uart_pl011_bus_attach()
422 	__uart_setreg(bas, UART_IMSC, psc->imsc);  in uart_pl011_bus_attach()
457 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_ioctl()
468 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_ioctl()
482 	bas = &sc->sc_bas;  in uart_pl011_bus_ipend()
484 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_ipend()
495 		if (sc->sc_txbusy)  in uart_pl011_bus_ipend()
499 		__uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY);  in uart_pl011_bus_ipend()
502 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_ipend()
512 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_param()
513 	uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity);  in uart_pl011_bus_param()
514 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_param()
531 	 * FIFOs.  We check for both the old freebsd-historic and the proper  in uart_pl011_bus_hwrev_fdt()
532 	 * bindings-defined compatible strings for bcm2835, and also check the  in uart_pl011_bus_hwrev_fdt()
536 	if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") ||  in uart_pl011_bus_hwrev_fdt()
537 	    ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) {  in uart_pl011_bus_hwrev_fdt()
540 		node = ofw_bus_get_node(sc->sc_dev);  in uart_pl011_bus_hwrev_fdt()
541 		if (OF_getencprop(node, "arm,primecell-periphid", &periphid,  in uart_pl011_bus_hwrev_fdt()
547 	return (-1);  in uart_pl011_bus_hwrev_fdt()
556 	hwrev = -1;  in uart_pl011_bus_probe()
562 		hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4;  in uart_pl011_bus_probe()
565 		sc->sc_rxfifosz = FIFO_RX_SIZE_R2;  in uart_pl011_bus_probe()
566 		sc->sc_txfifosz = FIFO_TX_SIZE_R2;  in uart_pl011_bus_probe()
568 		sc->sc_rxfifosz = FIFO_RX_SIZE_R3;  in uart_pl011_bus_probe()
569 		sc->sc_txfifosz = FIFO_TX_SIZE_R3;  in uart_pl011_bus_probe()
572 	device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)");  in uart_pl011_bus_probe()
584 	bas = &sc->sc_bas;  in uart_pl011_bus_receive()
585 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_receive()
592 			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;  in uart_pl011_bus_receive()
607 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_receive()
627 	bas = &sc->sc_bas;  in uart_pl011_bus_transmit()
628 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_transmit()
630 	for (i = 0; i < sc->sc_txdatasz; i++) {  in uart_pl011_bus_transmit()
631 		__uart_setreg(bas, UART_DR, sc->sc_txbuf[i]);  in uart_pl011_bus_transmit()
636 	sc->sc_txbusy = 1;  in uart_pl011_bus_transmit()
637 	__uart_setreg(bas, UART_IMSC, psc->imsc);  in uart_pl011_bus_transmit()
639 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_transmit()
651 	bas = &sc->sc_bas;  in uart_pl011_bus_grab()
654 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_grab()
655 	__uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL);  in uart_pl011_bus_grab()
656 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_grab()
666 	bas = &sc->sc_bas;  in uart_pl011_bus_ungrab()
669 	uart_lock(sc->sc_hwmtx);  in uart_pl011_bus_ungrab()
670 	__uart_setreg(bas, UART_IMSC, psc->imsc);  in uart_pl011_bus_ungrab()
671 	uart_unlock(sc->sc_hwmtx);  in uart_pl011_bus_ungrab()