Lines Matching +full:rclk +full:-

1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
145 * FIXME: actual register size is SoC-dependent, we need to handle it
148 bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg))
150 bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs(bas, reg), value)
153 * Low-level UART interface.
220 if (bas->rclk != 0 && baudrate != 0) { in uart_pl011_param()
221 baud = bas->rclk * 4 / baudrate; in uart_pl011_param()
236 * Loader tells us to infer the rclk when it sets xo to 0 in in uart_pl011_param()
238 * baudrate was set by the firmware, so calculate rclk from baudrate and in uart_pl011_param()
240 * will have us fall back to other rclk methods. This method should be in uart_pl011_param()
244 if (bas->rclk == 0 && baudrate > 0 && bas->rclk_guess) { in uart_pl011_param()
249 bas->rclk = (div * baudrate) / 4; in uart_pl011_param()
314 * High-level UART interface.
388 bas = &sc->sc_bas; in uart_pl011_bus_attach()
391 psc->imsc = (UART_RXREADY | RIS_RTIM | UART_TXEMPTY); in uart_pl011_bus_attach()
392 __uart_setreg(bas, UART_IMSC, psc->imsc); in uart_pl011_bus_attach()
427 uart_lock(sc->sc_hwmtx); in uart_pl011_bus_ioctl()
438 uart_unlock(sc->sc_hwmtx); in uart_pl011_bus_ioctl()
452 bas = &sc->sc_bas; in uart_pl011_bus_ipend()
454 uart_lock(sc->sc_hwmtx); in uart_pl011_bus_ipend()
465 if (sc->sc_txbusy) in uart_pl011_bus_ipend()
469 __uart_setreg(bas, UART_IMSC, psc->imsc & ~UART_TXEMPTY); in uart_pl011_bus_ipend()
472 uart_unlock(sc->sc_hwmtx); in uart_pl011_bus_ipend()
482 uart_lock(sc->sc_hwmtx); in uart_pl011_bus_param()
483 uart_pl011_param(&sc->sc_bas, baudrate, databits, stopbits, parity); in uart_pl011_bus_param()
484 uart_unlock(sc->sc_hwmtx); in uart_pl011_bus_param()
501 * FIFOs. We check for both the old freebsd-historic and the proper in uart_pl011_bus_hwrev_fdt()
502 * bindings-defined compatible strings for bcm2835, and also check the in uart_pl011_bus_hwrev_fdt()
506 if (ofw_bus_is_compatible(sc->sc_dev, "brcm,bcm2835-pl011") || in uart_pl011_bus_hwrev_fdt()
507 ofw_bus_is_compatible(sc->sc_dev, "broadcom,bcm2835-uart")) { in uart_pl011_bus_hwrev_fdt()
510 node = ofw_bus_get_node(sc->sc_dev); in uart_pl011_bus_hwrev_fdt()
511 if (OF_getencprop(node, "arm,primecell-periphid", &periphid, in uart_pl011_bus_hwrev_fdt()
517 return (-1); in uart_pl011_bus_hwrev_fdt()
526 hwrev = -1; in uart_pl011_bus_probe()
532 hwrev = __uart_getreg(&sc->sc_bas, UART_PIDREG_2) >> 4; in uart_pl011_bus_probe()
535 sc->sc_rxfifosz = FIFO_RX_SIZE_R2; in uart_pl011_bus_probe()
536 sc->sc_txfifosz = FIFO_TX_SIZE_R2; in uart_pl011_bus_probe()
538 sc->sc_rxfifosz = FIFO_RX_SIZE_R3; in uart_pl011_bus_probe()
539 sc->sc_txfifosz = FIFO_TX_SIZE_R3; in uart_pl011_bus_probe()
542 device_set_desc(sc->sc_dev, "PrimeCell UART (PL011)"); in uart_pl011_bus_probe()
554 bas = &sc->sc_bas; in uart_pl011_bus_receive()
555 uart_lock(sc->sc_hwmtx); in uart_pl011_bus_receive()
562 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; in uart_pl011_bus_receive()
577 uart_unlock(sc->sc_hwmtx); in uart_pl011_bus_receive()
597 bas = &sc->sc_bas; in uart_pl011_bus_transmit()
598 uart_lock(sc->sc_hwmtx); in uart_pl011_bus_transmit()
600 for (i = 0; i < sc->sc_txdatasz; i++) { in uart_pl011_bus_transmit()
601 __uart_setreg(bas, UART_DR, sc->sc_txbuf[i]); in uart_pl011_bus_transmit()
606 sc->sc_txbusy = 1; in uart_pl011_bus_transmit()
607 __uart_setreg(bas, UART_IMSC, psc->imsc); in uart_pl011_bus_transmit()
609 uart_unlock(sc->sc_hwmtx); in uart_pl011_bus_transmit()
621 bas = &sc->sc_bas; in uart_pl011_bus_grab()
624 uart_lock(sc->sc_hwmtx); in uart_pl011_bus_grab()
625 __uart_setreg(bas, UART_IMSC, psc->imsc & ~IMSC_MASK_ALL); in uart_pl011_bus_grab()
626 uart_unlock(sc->sc_hwmtx); in uart_pl011_bus_grab()
636 bas = &sc->sc_bas; in uart_pl011_bus_ungrab()
639 uart_lock(sc->sc_hwmtx); in uart_pl011_bus_ungrab()
640 __uart_setreg(bas, UART_IMSC, psc->imsc); in uart_pl011_bus_ungrab()
641 uart_unlock(sc->sc_hwmtx); in uart_pl011_bus_ungrab()