1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
71  * Low-level UART interface.
98 	    msg, bas->bsh,
129 	 * don't know what u-boot might have set up.  in imx_uart_getbaud()
133 	rate = bas->rclk / predivs[i];  in imx_uart_getbaud()
192 	 * separate pre-divider.  We simplify the problem of coming up with a  in imx_uart_init()
193 	 * workable pair of numbers by assuming a pre-divider and numerator of  in imx_uart_init()
196 	 * includes the 16x over-sampling (so a value of 16 means divide by 1);  in imx_uart_init()
197 	 * the register value is the numerator-1, so we have a hard-coded 15.  in imx_uart_init()
201 	if ((baudrate > 0) && (bas->rclk != 0)) {  in imx_uart_init()
202 		baseclk = bas->rclk;  in imx_uart_init()
207 		SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1);  in imx_uart_init()
211 	 * Program the tx lowater and rx hiwater levels at which fifo-service  in imx_uart_init()
217 	reg |= (IMX_FIFOSZ - IMX_TXFIFO_LEVEL) << IMXUART_UFCR_TXTL_SHIFT;  in imx_uart_init()
265  * High-level UART interface.
313 	{"fsl,imx6q-uart",	(uintptr_t)&uart_imx_class},
314 	{"fsl,imx53-uart",	(uintptr_t)&uart_imx_class},
315 	{"fsl,imx51-uart",	(uintptr_t)&uart_imx_class},
316 	{"fsl,imx31-uart",	(uintptr_t)&uart_imx_class},
317 	{"fsl,imx27-uart",	(uintptr_t)&uart_imx_class},
318 	{"fsl,imx25-uart",	(uintptr_t)&uart_imx_class},
319 	{"fsl,imx21-uart",	(uintptr_t)&uart_imx_class},
340 	bas = &sc->sc_bas;  in imx_uart_setup_clocks()
342 	if (clk_get_by_ofw_name(sc->sc_dev, 0, "ipg", &ipgclk) != 0)  in imx_uart_setup_clocks()
345 	if (clk_get_by_ofw_name(sc->sc_dev, 0, "per", &perclk) != 0) {  in imx_uart_setup_clocks()
351 		device_printf(sc->sc_dev, "cannot enable ipg clock\n");  in imx_uart_setup_clocks()
357 		device_printf(sc->sc_dev, "cannot get frequency\n");  in imx_uart_setup_clocks()
361 	bas->rclk = (uint32_t)freq;  in imx_uart_setup_clocks()
373 	bas = &sc->sc_bas;  in imx_uart_bus_attach()
380 	bas->rclk = imx_ccm_uart_hz();  in imx_uart_bus_attach()
383 	if (sc->sc_sysdev != NULL) {  in imx_uart_bus_attach()
384 		di = sc->sc_sysdev;  in imx_uart_bus_attach()
385 		imx_uart_init(bas, di->baudrate, di->databits, di->stopbits,  in imx_uart_bus_attach()
386 		    di->parity);  in imx_uart_bus_attach()
432 	SETREG(&sc->sc_bas, REG(UCR4), 0);  in imx_uart_bus_detach()
452 		old = sc->sc_hwsig;  in imx_uart_bus_getsig()
454 		uart_lock(sc->sc_hwmtx);  in imx_uart_bus_getsig()
455 		bes = GETREG(&sc->sc_bas, REG(USR2));  in imx_uart_bus_getsig()
456 		uart_unlock(sc->sc_hwmtx);  in imx_uart_bus_getsig()
460 	} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));  in imx_uart_bus_getsig()
471 	bas = &sc->sc_bas;  in imx_uart_bus_ioctl()
473 	uart_lock(sc->sc_hwmtx);  in imx_uart_bus_ioctl()
485 	uart_unlock(sc->sc_hwmtx);  in imx_uart_bus_ioctl()
498 	bas = &sc->sc_bas;  in imx_uart_bus_ipend()
501 	uart_lock(sc->sc_hwmtx);  in imx_uart_bus_ipend()
514 	/* If we have reached tx low-water, we can tx some more now. */  in imx_uart_bus_ipend()
521 	 * If we have reached the rx high-water, or if there are bytes in the rx  in imx_uart_bus_ipend()
536 	uart_unlock(sc->sc_hwmtx);  in imx_uart_bus_ipend()
546 	uart_lock(sc->sc_hwmtx);  in imx_uart_bus_param()
547 	imx_uart_init(&sc->sc_bas, baudrate, databits, stopbits, parity);  in imx_uart_bus_param()
548 	uart_unlock(sc->sc_hwmtx);  in imx_uart_bus_param()
557 	error = imx_uart_probe(&sc->sc_bas);  in imx_uart_bus_probe()
565 	 * when we get a tx-ready interrupt.  in imx_uart_bus_probe()
567 	sc->sc_rxfifosz = IMX_FIFOSZ;  in imx_uart_bus_probe()
568 	sc->sc_txfifosz = IMX_TXFIFO_LEVEL;  in imx_uart_bus_probe()
570 	device_set_desc(sc->sc_dev, "Freescale i.MX UART");  in imx_uart_bus_probe()
580 	bas = &sc->sc_bas;  in imx_uart_bus_receive()
581 	uart_lock(sc->sc_hwmtx);  in imx_uart_bus_receive()
585 	 * (the rx high-water level) is reached, but we set sc_rxfifosz to the  in imx_uart_bus_receive()
592 			sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;  in imx_uart_bus_receive()
611 	uart_unlock(sc->sc_hwmtx);  in imx_uart_bus_receive()
625 	struct uart_bas *bas = &sc->sc_bas;  in imx_uart_bus_transmit()
628 	bas = &sc->sc_bas;  in imx_uart_bus_transmit()
629 	uart_lock(sc->sc_hwmtx);  in imx_uart_bus_transmit()
634 	 * because we got the TRDY (low-water reached) interrupt we know at  in imx_uart_bus_transmit()
637 	for (i = 0; i < sc->sc_txdatasz; i++) {  in imx_uart_bus_transmit()
638 		SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff);  in imx_uart_bus_transmit()
640 	sc->sc_txbusy = 1;  in imx_uart_bus_transmit()
643 	uart_unlock(sc->sc_hwmtx);  in imx_uart_bus_transmit()
651 	struct uart_bas *bas = &sc->sc_bas;  in imx_uart_bus_grab()
653 	bas = &sc->sc_bas;  in imx_uart_bus_grab()
654 	uart_lock(sc->sc_hwmtx);  in imx_uart_bus_grab()
657 	uart_unlock(sc->sc_hwmtx);  in imx_uart_bus_grab()
663 	struct uart_bas *bas = &sc->sc_bas;  in imx_uart_bus_ungrab()
665 	bas = &sc->sc_bas;  in imx_uart_bus_ungrab()
666 	uart_lock(sc->sc_hwmtx);  in imx_uart_bus_ungrab()
669 	uart_unlock(sc->sc_hwmtx);  in imx_uart_bus_ungrab()