Lines Matching defs:sym_hcb
1446 struct sym_hcb { struct
1447 struct mtx mtx;
1456 struct sym_ccbh ccb_head;
1457 struct sym_tcbh tcb_head;
1458 struct sym_lcbh lcb_head;
1464 struct sym_actscr idletask, notask, bad_itl, bad_itlq;
1465 vm_offset_t idletask_ba, notask_ba, bad_itl_ba, bad_itlq_ba;
1471 u32 *badluntbl; /* Table physical address */
1472 u32 badlun_sa; /* SCRIPT handler BUS address */
1477 u32 hcb_ba;
1484 u32 scr_ram_seg;
1489 device_t device;
1496 u_char sv_scntl0, sv_scntl3, sv_dmode, sv_dcntl, sv_ctest3, sv_ctest4,
1497 sv_ctest5, sv_gpcntl, sv_stest2, sv_stest4, sv_scntl4,
1498 sv_stest1;
1505 u_char rv_scntl0, rv_scntl3, rv_dmode, rv_dcntl, rv_ctest3, rv_ctest4,
1506 rv_ctest5, rv_stest2, rv_ccntl0, rv_ccntl1, rv_scntl4;
1512 struct sym_tcb *target;
1514 struct sym_tcb target[SYM_CONF_MAX_TARGET];
1521 u32 *targtbl;
1522 u32 targtbl_ba;
1527 struct cam_sim *sim;
1528 struct cam_path *path;
1533 struct resource *irq_res;
1534 struct resource *io_res;
1535 struct resource *mmio_res;
1536 struct resource *ram_res;
1537 int ram_id;
1538 void *intr;
1555 bus_dma_tag_t bus_dmat; /* DMA tag from parent BUS */
1556 bus_dma_tag_t data_dmat; /* DMA tag for user data */
1560 vm_offset_t mmio_ba; /* MMIO BUS address */
1561 int mmio_ws; /* MMIO Window size */
1563 vm_offset_t ram_ba; /* RAM BUS address */
1564 int ram_ws; /* RAM window size */
1572 u_char *scripta0; /* Copies of script and scripth */
1573 u_char *scriptb0; /* Copies of script and scripth */
1574 vm_offset_t scripta_ba; /* Actual script and scripth */
1575 vm_offset_t scriptb_ba; /* bus addresses. */
1576 vm_offset_t scriptb0_ba;
1577 u_short scripta_sz; /* Actual size of script A */
1578 u_short scriptb_sz; /* Actual size of script B */
1584 struct sym_fwa_ba fwa_bas; /* Useful SCRIPTA bus addresses */
1585 struct sym_fwb_ba fwb_bas; /* Useful SCRIPTB bus addresses */
1586 void (*fw_setup)(hcb_p np, const struct sym_fw *fw);
1587 void (*fw_patch)(hcb_p np);
1588 const char *fw_name;
1593 u_short device_id; /* PCI device id */
1594 u_char revision_id; /* PCI device revision id */
1595 u_int features; /* Chip features map */
1596 u_char myaddr; /* SCSI id of the adapter */
1597 u_char maxburst; /* log base 2 of dwords burst */
1598 u_char maxwide; /* Maximum transfer width */
1599 u_char minsync; /* Min sync period factor (ST) */
1600 u_char maxsync; /* Max sync period factor (ST) */
1601 u_char maxoffs; /* Max scsi offset (ST) */
1602 u_char minsync_dt; /* Min sync period factor (DT) */
1603 u_char maxsync_dt; /* Max sync period factor (DT) */
1604 u_char maxoffs_dt; /* Max scsi offset (DT) */
1605 u_char multiplier; /* Clock multiplier (1,2,4) */
1606 u_char clock_divn; /* Number of clock divisors */
1607 u32 clock_khz; /* SCSI clock frequency in KHz */
1608 u32 pciclk_khz; /* Estimated PCI clock in KHz */
1615 u32 *squeue; /* Start queue virtual address */
1616 u32 squeue_ba; /* Start queue BUS address */
1617 u_short squeueput; /* Next free slot of the queue */
1618 u_short actccbs; /* Number of allocated CCBs */
1624 u_short dqueueget; /* Next position to scan */
1626 u32 *dqueue; /* Completion (done) queue */
1627 u32 dqueue_ba; /* Done queue BUS address */
1634 u_char msgout[8]; /* Buffer for MESSAGE OUT */
1635 u_char msgin [8]; /* Buffer for MESSAGE IN */
1636 u32 lastmsg; /* Last SCSI message sent */
1637 u_char scratch; /* Scratch for SCSI receive */
1642 u_char usrflags; /* Miscellaneous user flags */
1643 u_char scsi_mode; /* Current SCSI BUS mode */
1644 u_char verbose; /* Verbosity for this controller*/
1645 u32 cache; /* Used for cache test at init. */
1650 ccb_p ccbh[CCB_HASH_SIZE]; /* CCB hashed by DSA value */
1651 SYM_QUEHEAD free_ccbq; /* Queue of available CCBs */
1652 SYM_QUEHEAD busy_ccbq; /* Queue of busy CCBs */
1660 SYM_QUEHEAD comp_ccbq;
1665 SYM_QUEHEAD cam_ccbq;
1696 #define HCB_BA(np, lbl) (np->hcb_ba + offsetof(struct sym_hcb, lbl)) argument