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1 /*-
8 * 1. Redistributions of source code must retain the above copyright notice,
34 * Define common SLI-4 structures and function prototypes.
43 #define SLI_SUB_PAGE_MASK (SLI_PAGE_SIZE - 1)
53 uint32_t mask = page_size - 1; in sli_page_count()
70 shift = 16; in sli_page_count()
93 * Common SLI-4 register offsets and field definitions
97 * @brief SLI_INTF - SLI Interface Definition Register
112 #define SLI4_IF_TYPE_BE3_SKH_VF 1
119 * @brief ASIC_ID - SLI ASIC Type and Revision Register
135 * @brief BMBX - Bootstrap Mailbox Register
141 #define SLI4_BMBX_HI BIT(1)
150 * @brief EQCQ_DOORBELL - EQ and CQ Doorbell Register
157 #define SLI4_EQCQ_NUM_SHIFT 16
168 * @brief SLIPORT_CONTROL - SLI Port Control Register
179 * @brief SLI4_SLIPORT_ERROR1 - SLI Port Error Register
184 * @brief SLI4_SLIPORT_ERROR2 - SLI Port Error Register
213 ci:1, /* clear interrupt */ in sli_eq_doorbell()
214 qt:1, /* queue type */ in sli_eq_doorbell()
217 arm:1, in sli_eq_doorbell()
218 :1, in sli_eq_doorbell()
219 se:1; in sli_eq_doorbell()
225 eq_doorbell->eq_id_lo = id & SLI4_EQCQ_EQ_ID_MASK_LO; in sli_eq_doorbell()
226 eq_doorbell->qt = 1; /* EQ is type 1 (section 2.2.3.3 SLI Arch) */ in sli_eq_doorbell()
227 eq_doorbell->eq_id_hi = (id >> 9) & 0x1f; in sli_eq_doorbell()
228 eq_doorbell->number_popped = n_popped; in sli_eq_doorbell()
229 eq_doorbell->arm = arm; in sli_eq_doorbell()
230 eq_doorbell->ci = TRUE; in sli_eq_doorbell()
241 qt:1, /* queue type */ in sli_cq_doorbell()
244 arm:1, in sli_cq_doorbell()
245 :1, in sli_cq_doorbell()
246 se:1; in sli_cq_doorbell()
252 cq_doorbell->cq_id_lo = id & SLI4_EQCQ_CQ_ID_MASK_LO; in sli_cq_doorbell()
253 cq_doorbell->qt = 0; /* CQ is type 0 (section 2.2.3.3 SLI Arch) */ in sli_cq_doorbell()
254 cq_doorbell->cq_id_hi = (id >> 10) & 0x1f; in sli_cq_doorbell()
255 cq_doorbell->number_popped = n_popped; in sli_cq_doorbell()
256 cq_doorbell->arm = arm; in sli_cq_doorbell()
269 arm:1, in sli_iftype6_eq_doorbell()
270 :1, in sli_iftype6_eq_doorbell()
271 io:1; in sli_iftype6_eq_doorbell()
277 eq_doorbell->eq_id = id; in sli_iftype6_eq_doorbell()
278 eq_doorbell->number_popped = n_popped; in sli_iftype6_eq_doorbell()
279 eq_doorbell->arm = arm; in sli_iftype6_eq_doorbell()
289 uint32_t cq_id:16, in sli_iftype6_cq_doorbell()
291 arm:1, in sli_iftype6_cq_doorbell()
292 :1, in sli_iftype6_cq_doorbell()
293 se:1; in sli_iftype6_cq_doorbell()
299 cq_doorbell->cq_id = id; in sli_iftype6_cq_doorbell()
300 cq_doorbell->number_popped = n_popped; in sli_iftype6_cq_doorbell()
301 cq_doorbell->arm = arm; in sli_iftype6_cq_doorbell()
307 * @brief MQ_DOORBELL - MQ Doorbell Register
311 #define SLI4_MQ_DOORBELL_NUM_SHIFT 16
318 * @brief RQ_DOORBELL - RQ Doorbell Register
322 #define SLI4_RQ_DOORBELL_NUM_SHIFT 16
329 * @brief WQ_DOORBELL - WQ Doorbell Register
333 #define SLI4_WQ_DOORBELL_IDX_SHIFT 16
343 * @brief SLIPORT_SEMAPHORE - SLI Port Host and Port Status Register
345 #define SLI4_PORT_SEMAPHORE_REG_0 0x00ac /** register offset Interface Type 0 + 1 */
346 #define SLI4_PORT_SEMAPHORE_REG_1 0x0180 /** register offset Interface Type 0 + 1 */
351 #define SLI4_PORT_SEMAPHORE_HOST_SHIFT 16
355 #define SLI4_PORT_SEMAPHORE_SCR1 BIT(27) /** scratch area 1 */
368 * @brief SLIPORT_STATUS - SLI Port Status Register
386 #define SLI4_PHYDEV_CONTROL_FRST BIT(1) /** firmware reset */
394 * SLI-4 mailbox command formats and definitions
401 status:16; /** Port writes to indicate success / fail */
468 #define SLI4_BDE_TYPE_BDE_64 0x00 /** Generic 64-bit data */
473 * @brief Scatter-Gather Entry (SGE)
481 last:1;
489 * @brief T10 DIF Scatter-Gather Entry (SGE)
497 last:1;
505 * @brief T10 DIF Seed Scatter-Gather Entry (SGE)
511 uint32_t app_tag_repl:16,
513 hs:1,
514 ws:1,
515 ic:1,
516 ics:1,
517 atrt:1,
518 at:1,
519 fwd_app_tag:1,
520 repl_app_tag:1,
521 head_insert:1,
523 last:1;
524 uint32_t app_tag_cmp:16,
526 auto_incr_ref_tag:1,
527 check_app_tag:1,
528 check_ref_tag:1,
529 check_crc:1,
530 new_ref_tag:1,
539 * @brief List Segment Pointer Scatter-Gather Entry (SGE)
547 last:1;
586 uint32_t maxbbc:8, /** Max buffer-to-buffer credit */
589 n_port_id:16,
599 bbscn:4, /** buffer-to-buffer state change number */
600 cscn:1, /** configure BBSCN */
616 uint32_t wki_selection:16,
617 :16;
627 * @brief FW_INITIALIZE - initialize a SLI port
635 * @brief FW_DEINITIALIZE - deinitialize a SLI port
643 * @brief INIT_LINK - initialize the link for a FC/FCoE port
646 uint32_t loopback:1,
649 #define FC_TOPOLOGY_P2P 1
651 unfair:1,
652 skip_lirp_lilp:1,
653 gen_loop_validity_check:1,
654 skip_lisa:1,
655 enable_topology_failover:1,
656 fixed_speed:1,
658 select_hightest_al_pa:1,
659 :16; /* pad to 32 bits */
671 #define SLI4_INIT_LINK_F_P2P_ONLY 1
675 #define SLI4_INIT_LINK_F_P2P_FAIL_OVER 1
684 #define FC_LINK_SPEED_1G 1
698 #define FC_LINK_SPEED_10G 16
711 * @brief INIT_VFI - initialize the VFI resource
716 uint32_t vfi:16,
718 vp:1,
719 vf:1,
720 vt:1,
721 vr:1;
722 uint32_t fcfi:16,
723 vpi:16;
726 :16;
735 * @brief INIT_VPI - initialize the VPI resource
740 uint32_t vpi:16,
741 vfi:16;
748 * @brief POST_XRI - post XRI resources to the SLI Port
753 uint32_t xri_base:16,
755 enx:1,
756 dl:1,
757 di:1,
758 val:1;
765 * @brief RELEASE_XRI - Release XRI resources from the SLI Port
775 uint32_t xri_tag0:16,
776 xri_tag1:16;
784 * @brief READ_CONFIG - read SLI port configuration parameters
794 ext:1; /** Resource Extents */
797 tf:1,
798 ptv:1,
801 uint32_t e_d_tov:16,
802 :16;
804 uint32_t r_a_tov:16,
805 :16;
808 uint32_t lmt:16, /** Link Module Type */
809 :16;
812 uint32_t xri_base:16,
813 xri_count:16;
814 uint32_t rpi_base:16,
815 rpi_count:16;
816 uint32_t vpi_base:16,
817 vpi_count:16;
818 uint32_t vfi_base:16,
819 vfi_count:16;
820 uint32_t :16,
821 fcfi_count:16;
822 uint32_t rq_count:16,
823 eq_count:16;
824 uint32_t wq_count:16,
825 cq_count:16;
834 #define SLI4_READ_CFG_TOPO_FC_DA 0x2 /** FC Direct Attach (non FC-AL) topology */
835 #define SLI4_READ_CFG_TOPO_FC_AL 0x3 /** FC-AL topology */
838 * @brief READ_NVPARMS - read SLI port configuration parameters
857 * @brief WRITE_NVPARMS - write SLI port configuration parameters
876 * @brief READ_REV - read the Port revision levels
881 uint32_t :16,
883 fcoem:1,
886 vpd:1,
898 char first_fw_name[16];
900 char second_fw_name[16];
914 * @brief READ_SPARM64 - read the Port service parameters
922 uint32_t vpi:16,
923 :16;
924 uint32_t port_name_start:16,
925 port_name_length:16;
926 uint32_t node_name_start:16,
927 node_name_length:16;
946 tf:1,
947 lu:1;
954 * @brief READ_TOPOLOGY - read the link event information
961 il:1,
962 pb_recvd:1,
979 lp_tov:16;
982 pb:1,
983 specified_al_pa:16;
1011 * @brief REG_FCFI - activate a FC Forwarder
1017 uint32_t fcf_index:16,
1018 fcfi:16;
1019 uint32_t rq_id_1:16,
1020 rq_id_0:16;
1021 uint32_t rq_id_3:16,
1022 rq_id_2:16;
1030 vv:1,
1040 #define SLI4_CMD_REG_FCFI_SET_MRQ_MODE 1
1045 uint32_t fcf_index:16,
1046 fcfi:16;
1048 uint32_t rq_id_1:16,
1049 rq_id_0:16;
1051 uint32_t rq_id_3:16,
1052 rq_id_2:16;
1062 vv:1,
1063 mode:1,
1069 :16;
1074 * @brief REG_RPI - register a Remote Port Indicator
1079 uint32_t rpi:16,
1080 :16;
1082 upd:1,
1084 etow:1,
1085 :1,
1086 terp:1,
1087 :1,
1088 ci:1;
1090 uint32_t vpi:16,
1091 :16;
1099 * @brief REG_VFI - register a Virtual Fabric Indicator
1104 uint32_t vfi:16,
1106 vp:1,
1107 upd:1,
1109 uint32_t fcfi:16,
1110 vpi:16; /* vp=TRUE */
1123 * @brief REG_VPI - register a Virtual Port Indicator
1130 upd:1,
1134 uint32_t vpi:16,
1135 vfi:16;
1142 * @brief REQUEST_FEATURES - request / query SLI features
1147 uint32_t iaab:1, /** inhibit auto-ABTS originator */
1148 npiv:1, /** NPIV support */
1149 dif:1, /** DIF/DIX support */
1150 vf:1, /** virtual fabric support */
1151 fcpi:1, /** FCP initiator support */
1152 fcpt:1, /** FCP target support */
1153 fcpc:1, /** combined FCP initiator/target */
1154 :1,
1155 rqd:1, /** recovery qualified delay */
1156 iaar:1, /** inhibit auto-ABTS responder */
1157 hlm:1, /** High Login Mode */
1158 perfh:1, /** performance hints */
1159 rxseq:1, /** RX Sequence Coalescing */
1160 rxri:1, /** Release XRI variant of Coalescing */
1161 dcl2:1, /** Disable Class 2 */
1162 rsco:1, /** Receive Sequence Coalescing Optimizations */
1163 mrqp:1, /** Multi RQ Pair Mode Support */
1175 uint32_t qry:1,
1185 * @brief SLI_CONFIG - submit a configuration command to Port
1201 uint32_t emb:1,
1219 * @brief READ_STATUS - read tx/rx status of a particular port
1226 uint32_t cc:1,
1250 * @brief READ_LNK_STAT - read link status of a particular port
1257 uint32_t rec:1,
1258 gec:1,
1259 w02of:1,
1260 w03of:1,
1261 w04of:1,
1262 w05of:1,
1263 w06of:1,
1264 w07of:1,
1265 w08of:1,
1266 w09of:1,
1267 w10of:1,
1268 w11of:1,
1269 w12of:1,
1270 w13of:1,
1271 w14of:1,
1272 w15of:1,
1273 w16of:1,
1274 w17of:1,
1275 w18of:1,
1276 w19of:1,
1277 w20of:1,
1278 w21of:1,
1280 clrc:1,
1281 clof:1;
1312 * PHWQ works by over-writing part of Word 10 in the WQE with the WQ ID.
1326 * Set Word 10, bits 15:1 to the WQ ID in sli_set_wq_id_association()
1330 wqe[10] |= q_id << 1; in sli_set_wq_id_association()
1337 * @brief UNREG_FCFI - unregister a FCFI
1343 uint32_t fcfi:16,
1344 :16;
1351 * @brief UNREG_RPI - unregister one or more RPI
1356 uint32_t index:16,
1358 dp:1,
1373 * @brief UNREG_VFI - unregister one or more VFI
1379 uint32_t index:16,
1398 * @brief UNREG_VPI - unregister one or more VPI
1404 uint32_t index:16,
1417 * @brief AUTO_XFER_RDY - Configure the auto-generate XFER-RDY feature.
1434 uint32_t esoc:1,
1436 uint32_t block_size:16,
1437 :16;
1444 * SLI-4 common configuration command formats and definitions
1522 :16;
1539 :16;
1542 :16;
1553 * Resets the Port, returning it to a power-on state. This configuration
1573 uint32_t num_pages:16,
1574 :16;
1577 nodelay:1,
1580 valid:1,
1581 :1,
1582 evt:1;
1585 :1,
1586 arm:1;
1605 uint32_t num_pages:16,
1610 nodelay:1,
1611 autovalid:1,
1615 valid:1,
1616 :1,
1617 evt:1;
1618 uint32_t eq_id:16,
1620 arm:1;
1621 uint32_t cqe_count:16,
1622 :16;
1623 uint32_t rsvd[1];
1641 uint32_t num_pages:16,
1646 nodelay:1,
1647 autovalid:1,
1650 valid:1,
1651 :1,
1652 evt:1;
1653 uint32_t num_cq_req:16,
1655 arm:1;
1656 uint16_t eq_id[16];
1670 #define SLI4_CQ_CNT_512 1
1684 uint32_t q_id:16,
1688 uint32_t db_rs:16,
1689 db_fmt:16;
1698 uint32_t q_id:16,
1699 num_q_allocated:16;
1711 uint32_t cq_id:16,
1712 :16;
1745 uint32_t num_pages:16,
1746 :16;
1748 autovalid:1,
1749 valid:1,
1750 :1,
1751 eqesz:1;
1755 arm:1;
1770 #define SLI4_EQ_CNT_512 1
1776 #define SLI4_EQE_SIZE_16 1
1784 uint32_t eq_id:16,
1785 :16;
1799 uint32_t num_pages:16,
1800 cq_id_v1:16;
1802 uint32_t async_cq_id_v1:16,
1807 val:1;
1808 uint32_t acqv:1,
1826 #define SLI4_ASYNC_EVT_LINK_STATE BIT(1)
1831 #define SLI4_ASYNC_EVT_FC BIT(16)
1860 uint32_t mq_id:16,
1861 :16;
1880 :16;
1895 uint32_t max_cdb_length:16,
1901 uint32_t default_link_down_timeout:16,
1913 uint32_t pci_vendor_id:16,
1914 pci_device_id:16;
1915 uint32_t pci_sub_vendor_id:16,
1916 pci_sub_system_id:16;
1964 uint8_t ipl_file_name[16];
1997 uint32_t resource_type:16,
1998 :16;
2013 uint32_t resource_extent_count:16,
2014 resource_extent_size:16;
2029 uint32_t ft:1,
2044 uint32_t eqe_count_mask:16,
2045 :16;
2054 uint32_t cqe_count_mask:16,
2055 :16;
2062 uint32_t mqe_count_mask:16,
2063 :16;
2072 uint32_t wqe_count_mask:16,
2073 :16;
2082 uint32_t rqe_count_mask:16,
2085 uint32_t fcoe:1,
2086 ext:1,
2087 hdrr:1,
2088 sglr:1,
2089 fbrr:1,
2090 areg:1,
2091 tgt:1,
2092 terp:1,
2093 assi:1,
2094 wchn:1,
2095 tcca:1,
2096 trty:1,
2097 trir:1,
2098 phoff:1,
2099 phon:1,
2100 phwq:1, /** Performance Hint WQ_ID Association */
2101 boundary_4ga:1,
2102 rxc:1,
2103 hlm:1,
2104 ipr:1,
2105 rxri:1,
2106 sglc:1,
2107 timm:1,
2108 tsmm:1,
2109 :1,
2110 oas:1,
2111 lc:1,
2112 agxf:1,
2120 uint32_t min_rq_buffer_size:16,
2121 :16;
2123 uint32_t physical_xri_max:16,
2124 physical_rpi_max:16;
2125 uint32_t physical_vpi_max:16,
2126 physical_vfi_max:16;
2128 uint32_t frag_num_field_offset:16, /* dword 20 */
2129 frag_num_field_size:16;
2130 uint32_t sgl_index_field_offset:16, /* dword 21 */
2131 sgl_index_field_size:16;
2343 function_id:16;
2348 uint8_t string_data[16];
2385 * by the SFF-8472 specification).
2431 eof:1;
2445 noc:1,
2446 eof:1;
2506 fdb:1,
2507 blp:1,
2508 qry:1;
2557 uint32_t seed:16,
2558 :16;
2566 uint32_t tmm:1,
2575 uint32_t isr:1, /*<< Include Sequence Reporting */
2576 agxfe:1, /*<< Auto Generate XFER-RDY Feature Enabled */
2588 uint32_t rtc:1,
2589 atv:1,
2590 tmm:1,
2591 :1,
2595 uint32_t app_tag:16,
2596 :16;
2604 uint32_t hck:1,
2605 qry:1,
2623 topo_failover:1,
2685 :16;
2693 imm:1,
2694 nosv:1;
2695 uint32_t :16,
2703 uint32_t number_of_vfs:16,
2704 :16;
2707 pchg:1,
2708 schg:1,
2709 xchg:1,
2711 uint32_t rsvd2[16];
2717 :16;
2718 uint32_t iscsi_tgt:1,
2719 iscsi_ini:1,
2720 iscsi_dif:1,
2723 uint32_t fcoe_tgt:1,
2724 fcoe_ini:1,
2725 fcoe_dif:1,
2779 isap:1;
2863 fd:1;
2921 fd:1;
2938 uint32_t watchdog_timeout:16,
2939 :16;
2960 uint32_t vld:1, /** valid */
2963 resource_id:16;
2970 #define SLI4_MAJOR_CODE_SENTINEL 1
2979 uint32_t completion_status:16, /** values are protocol specific */
2980 extended_status:16;
2984 con:1, /** consumed - command now being executed */
2985 cmp:1, /** completed - command still executing if clear */
2986 :1,
2987 ae:1, /** async event - this is an ACQE */
2988 val:1; /** valid - contents of CQE are valid */
3006 ae:1, /** async event - this is an ACQE */
3007 val:1; /** valid - contents of CQE are valid */
3062 #define SLI_USER_MQ_COUNT 1 /** User specified max mail queues */
3063 #define SLI_MAX_CQ_SET_COUNT 16
3064 #define SLI_MAX_RQ_SET_COUNT 16
3103 uint32_t is_mq:1,/** CQ contains MQ/Async completions */
3104 is_hdr:1,/** is a RQ for packet headers */
3105 rq_batch:1;/** RQ index incremented by 8 */
3113 ocs_lock(&q->lock); in sli_queue_lock()
3119 ocs_unlock(&q->lock); in sli_queue_unlock()
3140 SLI_LINK_TOPO_NPORT = 1, /** fabric or point-to-point */
3198 SLI4_ASIC_TYPE_BE3 = 1,
3207 SLI4_ASIC_REV_FPGA = 1,
3244 tf:1,
3245 ptv:1,
3250 uint8_t fw_name[2][16];
3251 char ipl_name[16];
3273 uint32_t has_extents:1,
3274 auto_reg:1,
3275 auto_xfer_rdy:1,
3276 hdr_template_req:1,
3277 perf_hint:1,
3278 perf_wq_id_association:1,
3281 high_login_mode:1,
3282 sgl_pre_registered:1,
3283 sgl_pre_registration_required:1,
3284 t10_dif_inline_capable:1,
3285 t10_dif_separate_capable:1;
3303 /* Save pointer to physical memory descriptor for non-embedded SLI_CONFIG
3324 return sli4->config.extent[rsrc].size; in sli_get_max_rsrc()
3333 return sli4->config.max_qcount[qtype]; in sli_get_max_queue()
3340 return sli4->config.max_qentries[qtype]; in sli_get_max_qentries()
3346 return sli4->config.sge_supported_length; in sli_get_max_sge()
3353 if (sli4->config.sgl_page_sizes != 1) { in sli_get_max_sgl()
3354 ocs_log_test(sli4->os, "unsupported SGL page sizes %#x\n", in sli_get_max_sgl()
3355 sli4->config.sgl_page_sizes); in sli_get_max_sgl()
3359 return ((sli4->config.max_sgl_pages * SLI_PAGE_SIZE) / sizeof(sli4_sge_t)); in sli_get_max_sgl()
3365 switch (sli4->config.topology) { in sli_get_medium()
3380 sli4_sgl_chaining_params_t *cparms = &sli4->config.sgl_chaining_params; in sli_skh_chain_sge_build()
3383 sge->sge_type = SLI4_SGE_TYPE_CHAIN; in sli_skh_chain_sge_build()
3384 sge->buffer_address_high = (uint32_t)cparms->chain_sge_initial_value_hi; in sli_skh_chain_sge_build()
3385 sge->buffer_address_low = in sli_skh_chain_sge_build()
3386 (uint32_t)((cparms->chain_sge_initial_value_lo | in sli_skh_chain_sge_build()
3387 (((uintptr_t)(xri_index & cparms->sgl_index_field_mask)) << in sli_skh_chain_sge_build()
3388 cparms->sgl_index_field_offset) | in sli_skh_chain_sge_build()
3389 (((uintptr_t)(frag_num & cparms->frag_num_field_mask)) << in sli_skh_chain_sge_build()
3390 cparms->frag_num_field_offset) | in sli_skh_chain_sge_build()
3397 return sli4->sli_rev; in sli_get_sli_rev()
3403 return sli4->sli_family; in sli_get_sli_family()
3409 return sli4->if_type; in sli_get_if_type()
3415 return sli4->config.wwpn; in sli_get_wwn_port()
3421 return sli4->config.wwnn; in sli_get_wwn_node()
3427 return sli4->vpd.data.virt; in sli_get_vpd()
3433 return sli4->vpd.length; in sli_get_vpd_len()
3439 return sli4->config.fw_rev[which]; in sli_get_fw_revision()
3445 return sli4->config.fw_name[which]; in sli_get_fw_name()
3451 return sli4->config.ipl_name; in sli_get_ipl_name()
3457 return sli4->config.hw_rev[which]; in sli_get_hw_revision()
3463 return sli4->config.auto_xfer_rdy; in sli_get_auto_xfer_rdy_capable()
3469 return sli4->config.features.flag.dif; in sli_get_dif_capable()
3475 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_inline_capable; in sli_is_dif_inline_capable()
3481 return sli_get_dif_capable(sli4) && sli4->config.t10_dif_separate_capable; in sli_is_dif_separate_capable()
3487 return sli4->config.dual_ulp_capable; in sli_get_is_dual_ulp_capable()
3493 return sli4->config.sgl_chaining_params.chaining_capable; in sli_get_is_sgl_chaining_capable()
3499 return sli4->config.is_ulp_fc[ulp]; in sli_get_is_ulp_enabled()
3505 return sli4->config.features.flag.hlm; in sli_get_hlm_capable()
3511 if (value && !sli4->config.features.flag.hlm) { in sli_set_hlm()
3512 ocs_log_test(sli4->os, "HLM not supported\n"); in sli_set_hlm()
3513 return -1; in sli_set_hlm()
3516 sli4->config.high_login_mode = value != 0 ? TRUE : FALSE; in sli_set_hlm()
3524 return sli4->config.high_login_mode; in sli_get_hlm()
3530 return sli4->config.sgl_pre_registration_required; in sli_get_sgl_preregister_required()
3536 return sli4->config.sgl_pre_registered; in sli_get_sgl_preregister()
3542 if ((value == 0) && sli4->config.sgl_pre_registration_required) { in sli_set_sgl_preregister()
3543 ocs_log_test(sli4->os, "SGL pre-registration required\n"); in sli_set_sgl_preregister()
3544 return -1; in sli_set_sgl_preregister()
3547 sli4->config.sgl_pre_registered = value != 0 ? TRUE : FALSE; in sli_set_sgl_preregister()
3555 return sli4->asic_type; in sli_get_asic_type()
3561 return sli4->asic_rev; in sli_get_asic_rev()
3574 sli4->config.topology = value; in sli_set_topology()
3577 ocs_log_test(sli4->os, "unsupported topology %#x\n", value); in sli_set_topology()
3578 rc = -1; in sli_set_topology()
3587 sli4->config.pt = req->persistent_topo; in sli_config_persistent_topology()
3588 sli4->config.tf = req->topo_failover; in sli_config_persistent_topology()
3594 return sli4->config.link_module_type; in sli_get_link_module_type()
3600 return sli4->config.port_name; in sli_get_portnum()
3606 return sli4->config.bios_version_string; in sli_get_bios_version_string()
3615 count = 1 << ocs_lg2(mask); in sli_convert_mask_to_count()
3616 count *= 16; in sli_convert_mask_to_count()
3630 ocs_log_err(NULL, "unsupported FC-AL speed (speed_code: %d)\n", link_speed); in sli_fcal_is_speed_supported()
3772 * Note that although most commands provide a 16 bit field for the FCFI,
3775 * 1 << 6 or 64.
3782 * The SLI-4 specification uses a 16 bit field in most places for the FCF
3789 * SLI-4 FC/FCoE mailbox command formats and definitions.
3823 dua:1,
3825 cq_id:16;
3827 uint32_t bqu:1,
3830 :16;
3839 * Create a version 1 Work Queue for FC/FCoE use.
3844 uint32_t num_pages:16,
3845 cq_id:16;
3849 wqe_count:16;
3867 uint32_t wq_id:16,
3868 :16;
3882 uint32_t xri_start:16,
3883 xri_count:16;
3903 uint32_t num_pages:16,
3904 dua:1,
3905 bqu:1,
3908 uint32_t :16,
3912 uint32_t buffer_size:16,
3913 cq_id:16;
3928 * Create a version 1 Receive Queue for FC/FCoE use.
3933 uint32_t num_pages:16,
3935 dim:1,
3936 dfd:1,
3937 dnb:1;
3941 rqe_count:16;
3943 uint32_t :16,
3944 cq_id:16;
3960 uint32_t num_pages:16,
3963 dim:1,
3964 dfd:1,
3965 dnb:1;
3969 rqe_count:16;
3970 uint32_t hdr_buffer_size:16,
3971 payload_buffer_size:16;
3972 uint32_t base_cq_id:16,
3973 :16;
4007 uint32_t rq_id:16,
4008 :16;
4023 uint32_t fcf_index:16,
4024 :16;
4030 /* A FCF index of -1 on the request means return the first valid entry */
4048 uint8_t val:1,
4049 fc:1,
4051 sol:1;
4052 uint32_t fcf_index:16,
4053 fcf_state:16;
4068 uint32_t next_index:16,
4069 :16;
4076 /* A next FCF index of -1 in the response means this is the last valid entry */
4085 uint32_t rpi_offset:16,
4086 page_count:16;
4101 uint32_t fcf_count:16,
4102 :16;
4104 uint16_t fcf_index[16];
4151 #define SLI4_WQE_BYTES (16 * sizeof(uint32_t))
4163 uint32_t xri_tag:16,
4164 context_tag:16;
4170 :1,
4175 uint32_t request_tag:16,
4176 :16;
4180 qosd:1,
4181 :1,
4182 xbl:1,
4183 hlm:1,
4184 iod:1,
4185 dbde:1,
4186 wqes:1,
4188 pv:1,
4189 eat:1,
4190 xc:1,
4191 :1,
4192 ccpe:1,
4196 wqec:1,
4198 cq_id:16;
4212 uint32_t ia:1,
4213 ir:1,
4216 :16;
4219 uint32_t xri_tag:16,
4220 context_tag:16;
4226 :1,
4231 uint32_t request_tag:16,
4232 :16;
4236 qosd:1,
4237 :1,
4238 xbl:1,
4239 :1,
4240 iod:1,
4241 dbde:1,
4242 wqes:1,
4244 pv:1,
4245 eat:1,
4246 xc:1,
4247 :1,
4248 ccpe:1,
4252 wqec:1,
4254 cq_id:16;
4280 sp:1,
4284 uint32_t xri_tag:16,
4285 context_tag:16;
4291 ar:1,
4296 uint32_t request_tag:16,
4297 temporary_rpi:16;
4301 qosd:1,
4302 :1,
4303 xbl:1,
4304 hlm:1,
4305 iod:1,
4306 dbde:1,
4307 wqes:1,
4309 pv:1,
4310 eat:1,
4311 xc:1,
4312 :1,
4313 ccpe:1,
4317 wqec:1,
4319 cq_id:16;
4354 uint32_t payload_offset_length:16,
4355 fcp_cmd_buffer_length:16;
4359 uint32_t xri_tag:16,
4360 context_tag:16;
4364 :1,
4367 :1,
4369 erp:1,
4370 lnk:1,
4373 uint32_t request_tag:16,
4374 :16;
4378 qosd:1,
4379 :1,
4380 xbl:1,
4381 hlm:1,
4382 iod:1,
4383 dbde:1,
4384 wqes:1,
4386 pv:1,
4387 eat:1,
4388 xc:1,
4389 :1,
4390 ccpe:1,
4394 wqec:1,
4396 cq_id:16;
4412 uint32_t payload_offset_length:16,
4413 fcp_cmd_buffer_length:16;
4417 uint32_t xri_tag:16,
4418 context_tag:16;
4422 :1,
4425 :1,
4427 erp:1,
4428 lnk:1,
4431 uint32_t request_tag:16,
4432 :16;
4436 qosd:1,
4437 :1,
4438 xbl:1,
4439 hlm:1,
4440 iod:1,
4441 dbde:1,
4442 wqes:1,
4444 pv:1,
4445 eat:1,
4446 xc:1,
4447 :1,
4448 ccpe:1,
4452 wqec:1,
4454 cq_id:16;
4468 uint32_t payload_offset_length:16,
4469 fcp_cmd_buffer_length:16;
4472 uint32_t xri_tag:16,
4473 context_tag:16;
4477 :1,
4480 :1,
4482 erp:1,
4483 lnk:1,
4486 uint32_t request_tag:16,
4487 :16;
4491 qosd:1,
4492 :1,
4493 xbl:1,
4494 hlm:1,
4495 iod:1,
4496 dbde:1,
4497 wqes:1,
4499 pv:1,
4500 eat:1,
4501 xc:1,
4502 :1,
4503 ccpe:1,
4507 wqec:1,
4509 cq_id:16;
4533 * the remote N_Port ID (HLM=1), or if implementing the Skyhawk
4534 * T10-PI workaround, the secondary xri tag
4537 uint32_t sec_xri_tag:16,
4538 :16;
4541 uint32_t xri_tag:16,
4542 context_tag:16;
4546 :1,
4549 ar:1,
4551 conf:1,
4552 lnk:1,
4555 uint32_t request_tag:16,
4556 remote_xid:16;
4558 :1,
4559 app_id_valid:1,
4560 :1,
4562 qosd:1,
4563 wchn:1,
4564 xbl:1,
4565 hlm:1,
4566 iod:1,
4567 dbde:1,
4568 wqes:1,
4570 pv:1,
4571 eat:1,
4572 xc:1,
4573 sr:1,
4574 ccpe:1,
4578 wqec:1,
4580 cq_id:16;
4600 * the remote N_Port ID (HLM=1)
4603 uint32_t xri_tag:16,
4604 rpi:16;
4607 dnrx:1,
4611 ag:1,
4613 conf:1,
4614 lnk:1,
4617 uint32_t request_tag:16,
4618 remote_xid:16;
4620 :1,
4621 app_id_valid:1,
4622 :1,
4624 qosd:1,
4625 wchn:1,
4626 xbl:1,
4627 hlm:1,
4628 iod:1,
4629 dbde:1,
4630 wqes:1,
4632 pv:1,
4633 eat:1,
4634 xc:1,
4635 sr:1,
4636 ccpe:1,
4640 wqec:1,
4642 cq_id:16;
4662 * the remote N_Port ID (HLM=1)
4665 uint32_t xri_tag:16,
4666 rpi:16;
4670 :1,
4673 ar:1,
4675 conf:1,
4676 lnk:1,
4679 uint32_t request_tag:16,
4680 remote_xid:16;
4682 :1,
4683 app_id_valid:1,
4684 :1,
4686 qosd:1,
4687 wchn:1,
4688 xbl:1,
4689 hlm:1,
4690 iod:1,
4691 dbde:1,
4692 wqes:1,
4694 pv:1,
4695 eat:1,
4696 xc:1,
4697 sr:1,
4698 ccpe:1,
4702 wqec:1,
4704 cq_id:16;
4714 #define SLI4_IO_AUTO_GOOD_RESPONSE BIT(1) /** Automatically generate a good RSP frame */
4720 #define SLI4_DIF_PASS_THROUGH 1
4736 uint32_t xri_tag:16,
4737 context_tag:16;
4743 :1,
4748 uint32_t request_tag:16,
4749 :16;
4753 qosd:1,
4754 :1,
4755 xbl:1,
4756 hlm:1,
4757 iod:1,
4758 dbde:1,
4759 wqes:1,
4761 pv:1,
4762 eat:1,
4763 xc:1,
4764 :1,
4765 ccpe:1,
4769 wqec:1,
4771 cq_id:16;
4790 uint32_t xri_tag:16,
4791 context_tag:16;
4797 :1,
4802 uint32_t request_tag:16,
4808 qosd:1,
4809 wchn:1,
4810 xbl:1,
4811 hlm:1,
4812 iod:1,
4813 dbde:1,
4814 wqes:1,
4816 pv:1,
4817 eat:1,
4818 xc:1,
4819 :1,
4820 ccpe:1,
4824 wqec:1,
4826 cq_id:16;
4843 si:1,
4844 ft:1,
4846 xo:1,
4847 ls:1,
4851 uint32_t xri_tag:16,
4852 context_tag:16;
4856 :1,
4859 :1,
4864 uint32_t request_tag:16,
4865 remote_xid:16;
4869 qosd:1,
4870 :1,
4871 xbl:1,
4872 hlm:1,
4873 iod:1,
4874 dbde:1,
4875 wqes:1,
4877 pv:1,
4878 eat:1,
4879 xc:1,
4880 sr:1,
4881 ccpe:1,
4885 wqec:1,
4887 cq_id:16;
4908 uint32_t xri_tag:16,
4909 context_tag:16;
4915 :1,
4920 uint32_t request_tag:16,
4921 :16;
4925 qosd:1,
4926 wchn:1,
4927 xbl:1,
4928 hlm:1,
4929 iod:1,
4930 dbde:1,
4931 wqes:1,
4933 pv:1,
4934 eat:1,
4935 xc:1,
4936 :1,
4937 ccpe:1,
4941 wqec:1,
4943 cq_id:16;
4965 uint32_t xri_tag:16,
4966 context_tag:16;
4972 :1,
4977 uint32_t request_tag:16,
4978 temporary_rpi:16;
4982 qosd:1,
4983 :1,
4984 xbl:1,
4985 hlm:1,
4986 iod:1,
4987 dbde:1,
4988 wqes:1,
4990 pv:1,
4991 eat:1,
4992 xc:1,
4993 :1,
4994 ccpe:1,
4998 wqec:1,
5000 cq_id:16;
5016 uint32_t rx_id:16,
5017 ox_id:16;
5018 uint32_t high_seq_cnt:16,
5019 low_seq_cnt:16;
5025 ar:1,
5026 xo:1;
5027 uint32_t xri_tag:16,
5028 context_tag:16;
5034 :1,
5039 uint32_t request_tag:16,
5040 :16;
5044 qosd:1,
5045 :1,
5046 xbl:1,
5047 hlm:1,
5048 iod:1,
5049 dbde:1,
5050 wqes:1,
5052 pv:1,
5053 eat:1,
5054 xc:1,
5055 :1,
5056 ccpe:1,
5060 wqec:1,
5062 cq_id:16;
5063 uint32_t temporary_rpi:16,
5064 :16;
5087 :16;
5110 sp:1,
5114 uint32_t xri_tag:16,
5115 context_tag:16;
5121 :1,
5126 uint32_t request_tag:16,
5127 ox_id:16;
5131 qosd:1,
5132 :1,
5133 xbl:1,
5134 hlm:1,
5135 iod:1,
5136 dbde:1,
5137 wqes:1,
5139 pv:1,
5140 eat:1,
5141 xc:1,
5142 :1,
5143 ccpe:1,
5147 wqec:1,
5149 cq_id:16;
5150 uint32_t temporary_rpi:16,
5151 :16;
5172 logical_link_speed:16;
5178 ae:1, /** async event - this is an ACQE */
5179 val:1; /** valid - contents of CQE are valid */
5215 logical_link_speed:16;
5221 ae:1, /** async event - this is an ACQE */
5222 val:1; /** valid - contents of CQE are valid */
5266 uint32_t fcf_count:16,
5267 fcoe_event_type:16;
5273 ae:1, /** async event - this is an ACQE */
5274 val:1; /** valid - contents of CQE are valid */
5287 request_tag:16;
5291 qx:1,
5294 pv:1,
5295 xb:1,
5297 vld:1;
5310 uint32_t wqe_index:16,
5311 wq_id:16;
5312 uint32_t :16,
5315 vld:1;
5355 #define SLI4_FC_DI_ERROR_GE (1 << 0) /* Guard Error */
5356 #define SLI4_FC_DI_ERROR_AE (1 << 1) /* Application Tag Error */
5357 #define SLI4_FC_DI_ERROR_RE (1 << 2) /* Reference Tag Error */
5358 #define SLI4_FC_DI_ERROR_TDPV (1 << 3) /* Total Data Placed Valid */
5359 #define SLI4_FC_DI_ERROR_UDB (1 << 4) /* Uninitialized DIF Block */
5360 #define SLI4_FC_DI_ERROR_EDIR (1 << 5) /* Error direction */
5424 payload_data_placement_length:16;
5429 :1,
5430 vld:1;
5444 uint32_t rq_id:16,
5445 payload_data_placement_length:16;
5450 :1,
5451 vld:1;
5470 uint32_t rq_id:16,
5471 sequence_reporting_placement_length:16;
5472 uint32_t :16,
5475 vld:1;
5489 iv:1;
5492 oox:1,
5493 agxr:1,
5494 xri:16;
5495 uint32_t rq_id:16,
5496 payload_data_placement_length:16;
5497 uint32_t rpi:16,
5500 :1,
5501 vld:1;
5511 xri:16;
5514 uint32_t :16,
5517 pv:1,
5518 xb:1,
5519 rha:1,
5520 :1,
5521 vld:1;
5531 :16;
5533 uint32_t xri:16,
5534 remote_xid:16;
5535 uint32_t :16,
5537 xr:1,
5539 eo:1,
5540 br:1,
5541 ia:1,
5542 vld:1;
5620 * @return Returns 0 on success, or a non-zero value on failure.
5629 if (SLI4_FC_ASYNC_RQ_SUCCESS == rcqe->status) { in sli_fc_rqe_length()
5630 *len_hdr = rcqe->header_data_placement_length; in sli_fc_rqe_length()
5631 *len_data = rcqe->payload_data_placement_length; in sli_fc_rqe_length()
5634 return -1; in sli_fc_rqe_length()
5656 fcfi = rcqe->fcfi; in sli_fc_rqe_fcfi()
5661 fcfi = rcqev1->fcfi; in sli_fc_rqe_fcfi()
5666 fcfi = opt_wr->fcfi; in sli_fc_rqe_fcfi()