Lines Matching +full:0 +full:x8
32 MLX5_EVENT_TYPE_NOTIFY_ANY = 0x0,
33 MLX5_EVENT_TYPE_COMP = 0x0,
34 MLX5_EVENT_TYPE_PATH_MIG = 0x1,
35 MLX5_EVENT_TYPE_COMM_EST = 0x2,
36 MLX5_EVENT_TYPE_SQ_DRAINED = 0x3,
37 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
38 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
39 MLX5_EVENT_TYPE_DCT_DRAINED = 0x1c,
40 MLX5_EVENT_TYPE_DCT_KEY_VIOLATION = 0x1d,
41 MLX5_EVENT_TYPE_CQ_ERROR = 0x4,
42 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x5,
43 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x7,
44 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
45 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
46 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
47 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
48 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x8,
49 MLX5_EVENT_TYPE_PORT_CHANGE = 0x9,
50 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
51 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT = 0x16,
52 MLX5_EVENT_TYPE_TEMP_WARN_EVENT = 0x17,
53 MLX5_EVENT_TYPE_XRQ_ERROR = 0x18,
54 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
55 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT = 0x1e,
56 MLX5_EVENT_TYPE_CODING_PPS_EVENT = 0x25,
57 MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT = 0x22,
58 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
59 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
60 MLX5_EVENT_TYPE_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
61 MLX5_EVENT_TYPE_CMD = 0xa,
62 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
63 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
64 MLX5_EVENT_TYPE_FPGA_ERROR = 0x20,
65 MLX5_EVENT_TYPE_FPGA_QP_ERROR = 0x21,
66 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
70 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
71 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
72 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
73 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3,
74 MLX5_MODIFY_TIR_BITMASK_SELF_LB_EN = 0x4
78 MLX5_MODIFY_RQT_BITMASK_RQN_LIST = 0x1,
82 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
83 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
87 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
88 MLX5_OBJ_TYPE_MKEY = 0xff01,
89 MLX5_OBJ_TYPE_QP = 0xff02,
90 MLX5_OBJ_TYPE_PSV = 0xff03,
91 MLX5_OBJ_TYPE_RMP = 0xff04,
92 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05,
93 MLX5_OBJ_TYPE_RQ = 0xff06,
94 MLX5_OBJ_TYPE_SQ = 0xff07,
95 MLX5_OBJ_TYPE_TIR = 0xff08,
96 MLX5_OBJ_TYPE_TIS = 0xff09,
97 MLX5_OBJ_TYPE_DCT = 0xff0a,
98 MLX5_OBJ_TYPE_XRQ = 0xff0b,
99 MLX5_OBJ_TYPE_RQT = 0xff0e,
100 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f,
101 MLX5_OBJ_TYPE_CQ = 0xff10,
105 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
106 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
107 MLX5_CMD_OP_INIT_HCA = 0x102,
108 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
109 MLX5_CMD_OP_ENABLE_HCA = 0x104,
110 MLX5_CMD_OP_DISABLE_HCA = 0x105,
111 MLX5_CMD_OP_QUERY_PAGES = 0x107,
112 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
113 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
114 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
115 MLX5_CMD_OP_SET_ISSI = 0x10b,
116 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
117 MLX5_CMD_OP_QUERY_OTHER_HCA_CAP = 0x10e,
118 MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP = 0x10f,
119 MLX5_CMD_OP_CREATE_MKEY = 0x200,
120 MLX5_CMD_OP_QUERY_MKEY = 0x201,
121 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
122 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
123 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
124 MLX5_CMD_OP_CREATE_EQ = 0x301,
125 MLX5_CMD_OP_DESTROY_EQ = 0x302,
126 MLX5_CMD_OP_QUERY_EQ = 0x303,
127 MLX5_CMD_OP_GEN_EQE = 0x304,
128 MLX5_CMD_OP_CREATE_CQ = 0x400,
129 MLX5_CMD_OP_DESTROY_CQ = 0x401,
130 MLX5_CMD_OP_QUERY_CQ = 0x402,
131 MLX5_CMD_OP_MODIFY_CQ = 0x403,
132 MLX5_CMD_OP_CREATE_QP = 0x500,
133 MLX5_CMD_OP_DESTROY_QP = 0x501,
134 MLX5_CMD_OP_RST2INIT_QP = 0x502,
135 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
136 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
137 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
138 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
139 MLX5_CMD_OP_2ERR_QP = 0x507,
140 MLX5_CMD_OP_2RST_QP = 0x50a,
141 MLX5_CMD_OP_QUERY_QP = 0x50b,
142 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
143 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
144 MLX5_CMD_OP_CREATE_PSV = 0x600,
145 MLX5_CMD_OP_DESTROY_PSV = 0x601,
146 MLX5_CMD_OP_CREATE_SRQ = 0x700,
147 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
148 MLX5_CMD_OP_QUERY_SRQ = 0x702,
149 MLX5_CMD_OP_ARM_RQ = 0x703,
150 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
151 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
152 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
153 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
154 MLX5_CMD_OP_CREATE_DCT = 0x710,
155 MLX5_CMD_OP_DESTROY_DCT = 0x711,
156 MLX5_CMD_OP_DRAIN_DCT = 0x712,
157 MLX5_CMD_OP_QUERY_DCT = 0x713,
158 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
159 MLX5_CMD_OP_SET_DC_CNAK_TRACE = 0x715,
160 MLX5_CMD_OP_QUERY_DC_CNAK_TRACE = 0x716,
161 MLX5_CMD_OP_CREATE_XRQ = 0x717,
162 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
163 MLX5_CMD_OP_QUERY_XRQ = 0x719,
164 MLX5_CMD_OP_ARM_XRQ = 0x71a,
165 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725,
166 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726,
167 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727,
168 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729,
169 MLX5_CMD_OP_MODIFY_XRQ = 0x72a,
171 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
172 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
173 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
174 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
175 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
176 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
177 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
178 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
179 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
180 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
181 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
182 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
183 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f,
184 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
185 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
186 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
187 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
188 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
189 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
190 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
191 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
192 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
193 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
194 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
195 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
196 MLX5_CMD_OP_ALLOC_PD = 0x800,
197 MLX5_CMD_OP_DEALLOC_PD = 0x801,
198 MLX5_CMD_OP_ALLOC_UAR = 0x802,
199 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
200 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
201 MLX5_CMD_OP_ACCESS_REG = 0x805,
202 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
203 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
204 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
205 MLX5_CMD_OP_MAD_IFC = 0x50d,
206 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
207 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
208 MLX5_CMD_OP_NOP = 0x80d,
209 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
210 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
211 MLX5_CMD_OP_SET_BURST_SIZE = 0x812,
212 MLX5_CMD_OP_QUERY_BURST_SIZE = 0x813,
213 MLX5_CMD_OP_ACTIVATE_TRACER = 0x814,
214 MLX5_CMD_OP_DEACTIVATE_TRACER = 0x815,
215 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
216 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
217 MLX5_CMD_OP_QUERY_DIAGNOSTIC_PARAMS = 0x819,
218 MLX5_CMD_OP_SET_DIAGNOSTICS = 0x820,
219 MLX5_CMD_OP_QUERY_DIAGNOSTICS = 0x821,
220 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
221 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
222 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
223 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
224 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
225 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
226 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
227 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
228 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
229 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
230 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
231 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
232 MLX5_CMD_OP_CREATE_LAG = 0x840,
233 MLX5_CMD_OP_MODIFY_LAG = 0x841,
234 MLX5_CMD_OP_QUERY_LAG = 0x842,
235 MLX5_CMD_OP_DESTROY_LAG = 0x843,
236 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
237 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
238 MLX5_CMD_OP_CREATE_TIR = 0x900,
239 MLX5_CMD_OP_MODIFY_TIR = 0x901,
240 MLX5_CMD_OP_DESTROY_TIR = 0x902,
241 MLX5_CMD_OP_QUERY_TIR = 0x903,
242 MLX5_CMD_OP_CREATE_SQ = 0x904,
243 MLX5_CMD_OP_MODIFY_SQ = 0x905,
244 MLX5_CMD_OP_DESTROY_SQ = 0x906,
245 MLX5_CMD_OP_QUERY_SQ = 0x907,
246 MLX5_CMD_OP_CREATE_RQ = 0x908,
247 MLX5_CMD_OP_MODIFY_RQ = 0x909,
248 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
249 MLX5_CMD_OP_QUERY_RQ = 0x90b,
250 MLX5_CMD_OP_CREATE_RMP = 0x90c,
251 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
252 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
253 MLX5_CMD_OP_QUERY_RMP = 0x90f,
254 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
255 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS = 0x911,
256 MLX5_CMD_OP_CREATE_TIS = 0x912,
257 MLX5_CMD_OP_MODIFY_TIS = 0x913,
258 MLX5_CMD_OP_DESTROY_TIS = 0x914,
259 MLX5_CMD_OP_QUERY_TIS = 0x915,
260 MLX5_CMD_OP_CREATE_RQT = 0x916,
261 MLX5_CMD_OP_MODIFY_RQT = 0x917,
262 MLX5_CMD_OP_DESTROY_RQT = 0x918,
263 MLX5_CMD_OP_QUERY_RQT = 0x919,
264 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
265 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
266 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
267 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
268 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
269 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
270 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
271 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
272 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
273 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
274 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
275 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
276 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
277 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
278 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d,
279 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e,
280 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f,
281 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
282 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
283 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942,
284 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
285 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
286 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
287 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
288 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
289 MLX5_CMD_OP_CREATE_GENERAL_OBJ = 0xa00,
290 MLX5_CMD_OP_MODIFY_GENERAL_OBJ = 0xa01,
291 MLX5_CMD_OP_QUERY_GENERAL_OBJ = 0xa02,
292 MLX5_CMD_OP_DESTROY_GENERAL_OBJ = 0xa03,
293 MLX5_CMD_OP_CREATE_UCTX = 0xa04,
294 MLX5_CMD_OP_DESTROY_UCTX = 0xa06,
295 MLX5_CMD_OP_CREATE_UMEM = 0xa08,
296 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a,
301 MLX5_CMD_OP_GENERAL_START = 0xb00,
302 MLX5_CMD_OP_GENERAL_END = 0xd00,
306 MLX5_FT_NIC_RX_2_NIC_RX_RDMA = BIT(0),
311 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_QUERY_FW_INFO = 0x8007,
312 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_CAPABILITY = 0x8400,
313 MLX5_ICMD_CMDS_OPCODE_ICMD_ACCESS_REGISTER = 0x9001,
314 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_VIRTUAL_MAC = 0x9003,
315 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_VIRTUAL_MAC = 0x9004,
316 MLX5_ICMD_CMDS_OPCODE_ICMD_QUERY_WOL_ROL = 0x9005,
317 MLX5_ICMD_CMDS_OPCODE_ICMD_SET_WOL_ROL = 0x9006,
318 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_INIT = 0x9007,
319 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_HEADER_STATUS = 0x9008,
320 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_QUERY_ETOC_STATUS = 0x9009,
321 MLX5_ICMD_CMDS_OPCODE_ICMD_OCBB_SET_EVENT = 0x900a,
322 MLX5_ICMD_CMDS_OPCODE_ICMD_OPCODE_INIT_OCSD = 0xf004
326 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = 1ULL << 0x13,
330 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc,
331 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13,
335 MLX5_HCA_CAP_GENERAL_OBJ_TYPES_ENCRYPTION_KEY = 1 << 0xc,
339 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0,
340 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1,
344 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1,
345 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2,
349 u8 outer_dmac[0x1];
350 u8 outer_smac[0x1];
351 u8 outer_ether_type[0x1];
352 u8 outer_ip_version[0x1];
353 u8 outer_first_prio[0x1];
354 u8 outer_first_cfi[0x1];
355 u8 outer_first_vid[0x1];
356 u8 reserved_1[0x1];
357 u8 outer_second_prio[0x1];
358 u8 outer_second_cfi[0x1];
359 u8 outer_second_vid[0x1];
360 u8 outer_ipv6_flow_label[0x1];
361 u8 outer_sip[0x1];
362 u8 outer_dip[0x1];
363 u8 outer_frag[0x1];
364 u8 outer_ip_protocol[0x1];
365 u8 outer_ip_ecn[0x1];
366 u8 outer_ip_dscp[0x1];
367 u8 outer_udp_sport[0x1];
368 u8 outer_udp_dport[0x1];
369 u8 outer_tcp_sport[0x1];
370 u8 outer_tcp_dport[0x1];
371 u8 outer_tcp_flags[0x1];
372 u8 outer_gre_protocol[0x1];
373 u8 outer_gre_key[0x1];
374 u8 outer_vxlan_vni[0x1];
375 u8 outer_geneve_vni[0x1];
376 u8 outer_geneve_oam[0x1];
377 u8 outer_geneve_protocol_type[0x1];
378 u8 outer_geneve_opt_len[0x1];
379 u8 reserved_2[0x1];
380 u8 source_eswitch_port[0x1];
382 u8 inner_dmac[0x1];
383 u8 inner_smac[0x1];
384 u8 inner_ether_type[0x1];
385 u8 inner_ip_version[0x1];
386 u8 inner_first_prio[0x1];
387 u8 inner_first_cfi[0x1];
388 u8 inner_first_vid[0x1];
389 u8 reserved_4[0x1];
390 u8 inner_second_prio[0x1];
391 u8 inner_second_cfi[0x1];
392 u8 inner_second_vid[0x1];
393 u8 inner_ipv6_flow_label[0x1];
394 u8 inner_sip[0x1];
395 u8 inner_dip[0x1];
396 u8 inner_frag[0x1];
397 u8 inner_ip_protocol[0x1];
398 u8 inner_ip_ecn[0x1];
399 u8 inner_ip_dscp[0x1];
400 u8 inner_udp_sport[0x1];
401 u8 inner_udp_dport[0x1];
402 u8 inner_tcp_sport[0x1];
403 u8 inner_tcp_dport[0x1];
404 u8 inner_tcp_flags[0x1];
405 u8 reserved_5[0x9];
407 u8 reserved_6[0x1a];
408 u8 bth_dst_qp[0x1];
409 u8 reserved_7[0x4];
410 u8 source_sqn[0x1];
412 u8 reserved_8[0x20];
416 u8 ingress_general_high[0x20];
418 u8 ingress_general_low[0x20];
420 u8 ingress_policy_engine_high[0x20];
422 u8 ingress_policy_engine_low[0x20];
424 u8 ingress_vlan_membership_high[0x20];
426 u8 ingress_vlan_membership_low[0x20];
428 u8 ingress_tag_frame_type_high[0x20];
430 u8 ingress_tag_frame_type_low[0x20];
432 u8 egress_vlan_membership_high[0x20];
434 u8 egress_vlan_membership_low[0x20];
436 u8 loopback_filter_high[0x20];
438 u8 loopback_filter_low[0x20];
440 u8 egress_general_high[0x20];
442 u8 egress_general_low[0x20];
444 u8 reserved_at_1c0[0x40];
446 u8 egress_hoq_high[0x20];
448 u8 egress_hoq_low[0x20];
450 u8 port_isolation_high[0x20];
452 u8 port_isolation_low[0x20];
454 u8 egress_policy_engine_high[0x20];
456 u8 egress_policy_engine_low[0x20];
458 u8 ingress_tx_link_down_high[0x20];
460 u8 ingress_tx_link_down_low[0x20];
462 u8 egress_stp_filter_high[0x20];
464 u8 egress_stp_filter_low[0x20];
466 u8 egress_hoq_stall_high[0x20];
468 u8 egress_hoq_stall_low[0x20];
470 u8 reserved_at_340[0x440];
474 u8 ft_support[0x1];
475 u8 reserved_at_1[0x1];
476 u8 flow_counter[0x1];
477 u8 flow_modify_en[0x1];
478 u8 modify_root[0x1];
479 u8 identified_miss_table_mode[0x1];
480 u8 flow_table_modify[0x1];
481 u8 reformat[0x1];
482 u8 decap[0x1];
483 u8 reserved_at_9[0x1];
484 u8 pop_vlan[0x1];
485 u8 push_vlan[0x1];
486 u8 reserved_at_c[0x1];
487 u8 pop_vlan_2[0x1];
488 u8 push_vlan_2[0x1];
489 u8 reformat_and_vlan_action[0x1];
490 u8 reserved_at_10[0x1];
491 u8 sw_owner[0x1];
492 u8 reformat_l3_tunnel_to_l2[0x1];
493 u8 reformat_l2_to_l3_tunnel[0x1];
494 u8 reformat_and_modify_action[0x1];
495 u8 ignore_flow_level[0x1];
496 u8 reserved_at_16[0x1];
497 u8 table_miss_action_domain[0x1];
498 u8 termination_table[0x1];
499 u8 reformat_and_fwd_to_table[0x1];
500 u8 reserved_at_1a[0x2];
501 u8 ipsec_encrypt[0x1];
502 u8 ipsec_decrypt[0x1];
503 u8 sw_owner_v2[0x1];
504 u8 reserved_at_1f[0x1];
505 u8 termination_table_raw_traffic[0x1];
506 u8 reserved_at_21[0x1];
507 u8 log_max_ft_size[0x6];
508 u8 log_max_modify_header_context[0x8];
509 u8 max_modify_header_actions[0x8];
510 u8 max_ft_level[0x8];
512 u8 reformat_add_esp_trasport[0x1];
513 u8 reformat_l2_to_l3_esp_tunnel[0x1];
514 u8 reformat_add_esp_transport_over_udp[0x1];
515 u8 reformat_del_esp_trasport[0x1];
516 u8 reformat_l3_esp_tunnel_to_l2[0x1];
517 u8 reformat_del_esp_transport_over_udp[0x1];
518 u8 execute_aso[0x1];
519 u8 reserved_at_47[0x19];
520 u8 reserved_at_60[0x2];
521 u8 reformat_insert[0x1];
522 u8 reformat_remove[0x1];
523 u8 macsec_encrypt[0x1];
524 u8 macsec_decrypt[0x1];
525 u8 reserved_at_66[0x2];
526 u8 reformat_add_macsec[0x1];
527 u8 reformat_remove_macsec[0x1];
528 u8 reserved_at_6a[0xe];
529 u8 log_max_ft_num[0x8];
530 u8 reserved_at_80[0x10];
531 u8 log_max_flow_counter[0x8];
532 u8 log_max_destination[0x8];
533 u8 reserved_at_a0[0x18];
534 u8 log_max_flow[0x8];
535 u8 reserved_at_c0[0x40];
542 u8 send[0x1];
543 u8 receive[0x1];
544 u8 write[0x1];
545 u8 read[0x1];
546 u8 atomic[0x1];
547 u8 srq_receive[0x1];
548 u8 reserved_0[0x1a];
552 u8 reserved_0[0x10];
553 u8 flow_counter_id[0x10];
555 u8 reserved_1[0x20];
559 u8 destination_type[0x8];
560 u8 destination_id[0x18];
562 u8 destination_eswitch_owner_vhca_id_valid[0x1];
563 u8 packet_reformat[0x1];
564 u8 reserved_at_22[0x6];
565 u8 destination_table_type[0x8];
566 u8 destination_eswitch_owner_vhca_id[0x10];
570 u8 reserved_at_0[0x60];
572 u8 ipv4[0x20];
576 u8 ipv6[16][0x8];
582 u8 reserved_at_0[0x80];
586 u8 smac_47_16[0x20];
588 u8 smac_15_0[0x10];
589 u8 ethertype[0x10];
591 u8 dmac_47_16[0x20];
593 u8 dmac_15_0[0x10];
594 u8 first_prio[0x3];
595 u8 first_cfi[0x1];
596 u8 first_vid[0xc];
598 u8 ip_protocol[0x8];
599 u8 ip_dscp[0x6];
600 u8 ip_ecn[0x2];
601 u8 cvlan_tag[0x1];
602 u8 svlan_tag[0x1];
603 u8 frag[0x1];
604 u8 ip_version[0x4];
605 u8 tcp_flags[0x9];
607 u8 tcp_sport[0x10];
608 u8 tcp_dport[0x10];
610 u8 reserved_2[0x20];
612 u8 udp_sport[0x10];
613 u8 udp_dport[0x10];
621 u8 hi[0x18];
622 u8 lo[0x8];
627 u8 key[0x20];
631 u8 gre_c_present[0x1];
632 u8 reserved_at_1[0x1];
633 u8 gre_k_present[0x1];
634 u8 gre_s_present[0x1];
635 u8 source_vhca_port[0x4];
636 u8 source_sqn[0x18];
638 u8 source_eswitch_owner_vhca_id[0x10];
639 u8 source_port[0x10];
641 u8 outer_second_prio[0x3];
642 u8 outer_second_cfi[0x1];
643 u8 outer_second_vid[0xc];
644 u8 inner_second_prio[0x3];
645 u8 inner_second_cfi[0x1];
646 u8 inner_second_vid[0xc];
648 u8 outer_second_cvlan_tag[0x1];
649 u8 inner_second_cvlan_tag[0x1];
650 u8 outer_second_svlan_tag[0x1];
651 u8 inner_second_svlan_tag[0x1];
652 u8 reserved_at_64[0xc];
653 u8 gre_protocol[0x10];
657 u8 vxlan_vni[0x18];
658 u8 bth_opcode[0x8];
660 u8 geneve_vni[0x18];
661 u8 reserved_at_d8[0x6];
662 u8 geneve_tlv_option_0_exist[0x1];
663 u8 geneve_oam[0x1];
665 u8 reserved_at_e0[0xc];
666 u8 outer_ipv6_flow_label[0x14];
668 u8 reserved_at_100[0xc];
669 u8 inner_ipv6_flow_label[0x14];
671 u8 reserved_at_120[0xa];
672 u8 geneve_opt_len[0x6];
673 u8 geneve_protocol_type[0x10];
675 u8 reserved_at_140[0x8];
676 u8 bth_dst_qp[0x18];
677 u8 inner_esp_spi[0x20];
678 u8 outer_esp_spi[0x20];
679 u8 reserved_at_1a0[0x60];
683 u8 mpls_label[0x14];
684 u8 mpls_exp[0x3];
685 u8 mpls_s_bos[0x1];
686 u8 mpls_ttl[0x8];
698 u8 metadata_reg_c_7[0x20];
700 u8 metadata_reg_c_6[0x20];
702 u8 metadata_reg_c_5[0x20];
704 u8 metadata_reg_c_4[0x20];
706 u8 metadata_reg_c_3[0x20];
708 u8 metadata_reg_c_2[0x20];
710 u8 metadata_reg_c_1[0x20];
712 u8 metadata_reg_c_0[0x20];
714 u8 metadata_reg_a[0x20];
716 u8 reserved_at_1a0[0x8];
718 u8 macsec_syndrome[0x8];
719 u8 ipsec_syndrome[0x8];
720 u8 reserved_at_1b8[0x8];
722 u8 reserved_at_1c0[0x40];
726 u8 inner_tcp_seq_num[0x20];
728 u8 outer_tcp_seq_num[0x20];
730 u8 inner_tcp_ack_num[0x20];
732 u8 outer_tcp_ack_num[0x20];
734 u8 reserved_at_80[0x8];
735 u8 outer_vxlan_gpe_vni[0x18];
737 u8 outer_vxlan_gpe_next_protocol[0x8];
738 u8 outer_vxlan_gpe_flags[0x8];
739 u8 reserved_at_b0[0x10];
741 u8 icmp_header_data[0x20];
743 u8 icmpv6_header_data[0x20];
745 u8 icmp_type[0x8];
746 u8 icmp_code[0x8];
747 u8 icmpv6_type[0x8];
748 u8 icmpv6_code[0x8];
750 u8 geneve_tlv_option_0_data[0x20];
752 u8 gtpu_teid[0x20];
754 u8 gtpu_msg_type[0x8];
755 u8 gtpu_msg_flags[0x8];
756 u8 reserved_at_170[0x10];
758 u8 gtpu_dw_2[0x20];
760 u8 gtpu_first_ext_dw_0[0x20];
762 u8 gtpu_dw_0[0x20];
764 u8 reserved_at_1e0[0x20];
768 u8 prog_sample_field_value_0[0x20];
770 u8 prog_sample_field_id_0[0x20];
772 u8 prog_sample_field_value_1[0x20];
774 u8 prog_sample_field_id_1[0x20];
776 u8 prog_sample_field_value_2[0x20];
778 u8 prog_sample_field_id_2[0x20];
780 u8 prog_sample_field_value_3[0x20];
782 u8 prog_sample_field_id_3[0x20];
784 u8 reserved_at_100[0x100];
788 u8 macsec_tag_0[0x20];
790 u8 macsec_tag_1[0x20];
792 u8 macsec_tag_2[0x20];
794 u8 macsec_tag_3[0x20];
796 u8 tunnel_header_0[0x20];
798 u8 tunnel_header_1[0x20];
800 u8 tunnel_header_2[0x20];
802 u8 tunnel_header_3[0x20];
804 u8 reserved_at_100[0x100];
808 u8 pa_h[0x20];
810 u8 pa_l[0x14];
811 u8 reserved_0[0xc];
815 u8 hi[0x20];
817 u8 lo[0x20];
821 u8 reserved_0[0x8];
822 u8 priority[0x3];
823 u8 reserved_1[0x2];
824 u8 sel[0x3];
825 u8 protocol_id[0x10];
829 u8 reserved_0[0x8];
830 u8 ring_pi[0x10];
831 u8 reserved_1[0x8];
835 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
836 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
837 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
838 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
839 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
840 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
841 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
842 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
843 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
844 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
848 u8 fl[0x1];
849 u8 free_ar[0x1];
850 u8 reserved_0[0xe];
851 u8 pkey_index[0x10];
853 u8 reserved_1[0x8];
854 u8 grh[0x1];
855 u8 mlid[0x7];
856 u8 rlid[0x10];
858 u8 ack_timeout[0x5];
859 u8 reserved_2[0x3];
860 u8 src_addr_index[0x8];
861 u8 log_rtm[0x4];
862 u8 stat_rate[0x4];
863 u8 hop_limit[0x8];
865 u8 reserved_3[0x4];
866 u8 tclass[0x8];
867 u8 flow_label[0x14];
869 u8 rgid_rip[16][0x8];
871 u8 reserved_4[0x4];
872 u8 f_dscp[0x1];
873 u8 f_ecn[0x1];
874 u8 reserved_5[0x1];
875 u8 f_eth_prio[0x1];
876 u8 ecn[0x2];
877 u8 dscp[0x6];
878 u8 udp_sport[0x10];
880 u8 dei_cfi[0x1];
881 u8 eth_prio[0x3];
882 u8 sl[0x4];
883 u8 port[0x8];
884 u8 rmac_47_32[0x10];
886 u8 rmac_31_0[0x20];
890 u8 sync[0x1];
891 u8 reserved_0[0xf];
892 u8 counter_id[0x10];
896 u8 reserved_0[0x18];
897 u8 log_max_samples[0x8];
899 u8 single[0x1];
900 u8 repetitive[0x1];
901 u8 health_mon_rx_activity[0x1];
902 u8 reserved_1[0x15];
903 u8 log_min_sample_period[0x8];
905 u8 reserved_2[0x1c0];
907 struct mlx5_ifc_diagnostic_counter_cap_bits diagnostic_counter[0x1f0];
911 u8 packet_pacing[0x1];
912 u8 esw_scheduling[0x1];
913 u8 esw_bw_share[0x1];
914 u8 esw_rate_limit[0x1];
915 u8 hll[0x1];
916 u8 packet_pacing_burst_bound[0x1];
917 u8 packet_pacing_typical_size[0x1];
918 u8 reserved_at_7[0x19];
920 u8 reserved_at_20[0xA];
921 u8 qos_remap_pp[0x1];
922 u8 reserved_at_2b[0x15];
924 u8 packet_pacing_max_rate[0x20];
926 u8 packet_pacing_min_rate[0x20];
928 u8 reserved_at_80[0x10];
929 u8 packet_pacing_rate_table_size[0x10];
931 u8 esw_element_type[0x10];
932 u8 esw_tsar_type[0x10];
934 u8 reserved_at_c0[0x10];
935 u8 max_qos_para_vport[0x10];
937 u8 max_tsar_bw_share[0x20];
939 u8 reserved_at_100[0x700];
943 u8 reserved_0[0x1d];
944 u8 suspend_qp_uc[0x1];
945 u8 suspend_qp_ud[0x1];
946 u8 suspend_qp_rc[0x1];
948 u8 reserved_1[0x1c];
949 u8 restore_pd[0x1];
950 u8 restore_uar[0x1];
951 u8 restore_mkey[0x1];
952 u8 restore_qp[0x1];
954 u8 reserved_2[0x1e];
955 u8 named_mkey[0x1];
956 u8 named_qp[0x1];
958 u8 reserved_3[0x7a0];
962 u8 vport_svlan_strip[0x1];
963 u8 vport_cvlan_strip[0x1];
964 u8 vport_svlan_insert[0x1];
965 u8 vport_cvlan_insert_if_not_exist[0x1];
966 u8 vport_cvlan_insert_overwrite[0x1];
967 u8 reserved_at_5[0x1];
968 u8 vport_cvlan_insert_always[0x1];
969 u8 esw_shared_ingress_acl[0x1];
970 u8 esw_uplink_ingress_acl[0x1];
971 u8 root_ft_on_other_esw[0x1];
972 u8 reserved_at_a[0xf];
973 u8 esw_functions_changed[0x1];
974 u8 reserved_at_1a[0x1];
975 u8 ecpf_vport_exists[0x1];
976 u8 counter_eswitch_affinity[0x1];
977 u8 merged_eswitch[0x1];
978 u8 nic_vport_node_guid_modify[0x1];
979 u8 nic_vport_port_guid_modify[0x1];
981 u8 vxlan_encap_decap[0x1];
982 u8 nvgre_encap_decap[0x1];
983 u8 reserved_at_22[0x1];
984 u8 log_max_fdb_encap_uplink[0x5];
985 u8 reserved_at_21[0x3];
986 u8 log_max_packet_reformat_context[0x5];
987 u8 reserved_2b[0x6];
988 u8 max_encap_header_size[0xa];
990 u8 reserved_at_40[0xb];
991 u8 log_max_esw_sf[0x5];
992 u8 esw_sf_base_id[0x10];
994 u8 reserved_at_60[0x7a0];
999 u8 reserved_0[0x200];
1007 u8 reserved_1[0x7800];
1011 u8 nic_rx_multi_path_tirs[0x1];
1012 u8 nic_rx_multi_path_tirs_fts[0x1];
1013 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
1014 u8 reserved_at_3[0x4];
1015 u8 sw_owner_reformat_supported[0x1];
1016 u8 reserved_at_8[0x18];
1018 u8 encap_general_header[0x1];
1019 u8 reserved_at_21[0xa];
1020 u8 log_max_packet_reformat_context[0x5];
1021 u8 reserved_at_30[0x6];
1022 u8 max_encap_header_size[0xa];
1023 u8 reserved_at_40[0x1c0];
1037 u8 reserved_1[0x7200];
1041 u8 reserved_at_0[0x10];
1042 u8 port_select_flow_table[0x1];
1043 u8 reserved_at_11[0x1];
1044 u8 port_select_flow_table_bypass[0x1];
1045 u8 reserved_at_13[0xd];
1047 u8 reserved_at_20[0x1e0];
1051 u8 reserved_at_400[0x7c00];
1055 u8 cable_technology[0x8];
1056 u8 cable_breakout[0x8];
1057 u8 ext_ethernet_compliance_code[0x8];
1058 u8 ethernet_compliance_code[0x8];
1060 u8 cable_type[0x4];
1061 u8 cable_vendor[0x4];
1062 u8 cable_length[0x8];
1063 u8 cable_identifier[0x8];
1064 u8 cable_power_class[0x8];
1066 u8 reserved_at_40[0x8];
1067 u8 cable_rx_amp[0x8];
1068 u8 cable_rx_emphasis[0x8];
1069 u8 cable_tx_equalization[0x8];
1071 u8 reserved_at_60[0x8];
1072 u8 cable_attenuation_12g[0x8];
1073 u8 cable_attenuation_7g[0x8];
1074 u8 cable_attenuation_5g[0x8];
1076 u8 reserved_at_80[0x8];
1077 u8 rx_cdr_cap[0x4];
1078 u8 tx_cdr_cap[0x4];
1079 u8 reserved_at_90[0x4];
1080 u8 rx_cdr_state[0x4];
1081 u8 reserved_at_98[0x4];
1082 u8 tx_cdr_state[0x4];
1084 u8 vendor_name[16][0x8];
1086 u8 vendor_pn[16][0x8];
1088 u8 vendor_rev[0x20];
1090 u8 fw_version[0x20];
1092 u8 vendor_sn[16][0x8];
1094 u8 temperature[0x10];
1095 u8 voltage[0x10];
1097 u8 rx_power_lane0[0x10];
1098 u8 rx_power_lane1[0x10];
1100 u8 rx_power_lane2[0x10];
1101 u8 rx_power_lane3[0x10];
1103 u8 reserved_at_2c0[0x40];
1105 u8 tx_power_lane0[0x10];
1106 u8 tx_power_lane1[0x10];
1108 u8 tx_power_lane2[0x10];
1109 u8 tx_power_lane3[0x10];
1111 u8 reserved_at_340[0x40];
1113 u8 tx_bias_lane0[0x10];
1114 u8 tx_bias_lane1[0x10];
1116 u8 tx_bias_lane2[0x10];
1117 u8 tx_bias_lane3[0x10];
1119 u8 reserved_at_3c0[0x40];
1121 u8 temperature_high_th[0x10];
1122 u8 temperature_low_th[0x10];
1124 u8 voltage_high_th[0x10];
1125 u8 voltage_low_th[0x10];
1127 u8 rx_power_high_th[0x10];
1128 u8 rx_power_low_th[0x10];
1130 u8 tx_power_high_th[0x10];
1131 u8 tx_power_low_th[0x10];
1133 u8 tx_bias_high_th[0x10];
1134 u8 tx_bias_low_th[0x10];
1136 u8 reserved_at_4a0[0x10];
1137 u8 wavelength[0x10];
1139 u8 reserved_at_4c0[0x300];
1143 u8 csum_cap[0x1];
1144 u8 vlan_cap[0x1];
1145 u8 lro_cap[0x1];
1146 u8 lro_psh_flag[0x1];
1147 u8 lro_time_stamp[0x1];
1148 u8 lro_max_msg_sz_mode[0x2];
1149 u8 wqe_vlan_insert[0x1];
1150 u8 self_lb_en_modifiable[0x1];
1151 u8 self_lb_mc[0x1];
1152 u8 self_lb_uc[0x1];
1153 u8 max_lso_cap[0x5];
1154 u8 multi_pkt_send_wqe[0x2];
1155 u8 wqe_inline_mode[0x2];
1156 u8 rss_ind_tbl_cap[0x4];
1157 u8 reg_umr_sq[0x1];
1158 u8 scatter_fcs[0x1];
1159 u8 enhanced_multi_pkt_send_wqe[0x1];
1160 u8 tunnel_lso_const_out_ip_id[0x1];
1161 u8 tunnel_lro_gre[0x1];
1162 u8 tunnel_lro_vxlan[0x1];
1163 u8 tunnel_statless_gre[0x1];
1164 u8 tunnel_stateless_vxlan[0x1];
1166 u8 swp[0x1];
1167 u8 swp_csum[0x1];
1168 u8 swp_lso[0x1];
1169 u8 reserved_2[0x1b];
1170 u8 max_geneve_opt_len[0x1];
1171 u8 tunnel_stateless_geneve_rx[0x1];
1173 u8 reserved_3[0x10];
1174 u8 lro_min_mss_size[0x10];
1176 u8 reserved_4[0x120];
1178 u8 lro_timer_supported_periods[4][0x20];
1180 u8 reserved_5[0x600];
1184 MLX5_ROCE_CAP_L3_TYPE_GRH = 0x1,
1185 MLX5_ROCE_CAP_L3_TYPE_IPV4 = 0x2,
1186 MLX5_ROCE_CAP_L3_TYPE_IPV6 = 0x4,
1190 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1191 MLX5_QP_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1192 MLX5_QP_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1196 u8 roce_apm[0x1];
1197 u8 rts2rts_primary_eth_prio[0x1];
1198 u8 roce_rx_allow_untagged[0x1];
1199 u8 rts2rts_src_addr_index_for_vlan_valid_vlan_id[0x1];
1200 u8 reserved_at_4[0x1a];
1201 u8 qp_ts_format[0x2];
1203 u8 reserved_1[0x60];
1205 u8 reserved_2[0xc];
1206 u8 l3_type[0x4];
1207 u8 reserved_3[0x8];
1208 u8 roce_version[0x8];
1210 u8 reserved_4[0x10];
1211 u8 r_roce_dest_udp_port[0x10];
1213 u8 r_roce_max_src_udp_port[0x10];
1214 u8 r_roce_min_src_udp_port[0x10];
1216 u8 reserved_5[0x10];
1217 u8 roce_address_table_size[0x10];
1219 u8 reserved_6[0x700];
1223 u8 user_affiliated_events[4][0x40];
1225 u8 user_unaffiliated_events[4][0x40];
1229 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x1,
1230 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
1231 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
1232 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
1233 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
1234 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
1235 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
1236 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
1237 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
1241 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
1242 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
1243 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
1244 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
1245 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
1246 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
1247 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
1248 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
1249 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
1253 u8 reserved_0[0x40];
1255 u8 atomic_req_8B_endianess_mode[0x2];
1256 u8 reserved_1[0x4];
1257 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
1259 u8 reserved_2[0x19];
1261 u8 reserved_3[0x20];
1263 u8 reserved_4[0x10];
1264 u8 atomic_operations[0x10];
1266 u8 reserved_5[0x10];
1267 u8 atomic_size_qp[0x10];
1269 u8 reserved_6[0x10];
1270 u8 atomic_size_dc[0x10];
1272 u8 reserved_7[0x720];
1276 u8 reserved_0[0x40];
1278 u8 sig[0x1];
1279 u8 reserved_1[0x1f];
1281 u8 reserved_2[0x20];
1293 u8 reserved_3[0x6e0];
1297 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
1298 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
1299 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
1300 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
1301 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
1305 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
1306 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
1307 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
1308 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
1309 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
1310 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
1314 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
1315 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
1319 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
1320 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
1321 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
1325 MLX5_UCTX_CAP_RAW_TX = 1UL << 0,
1330 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1331 MLX5_SQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1332 MLX5_SQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1336 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0,
1337 MLX5_RQ_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1,
1338 MLX5_RQ_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2,
1342 u8 reserved_0[0x20];
1344 u8 hca_cap_2[0x1];
1345 u8 create_lag_when_not_master_up[0x1];
1346 u8 dtor[0x1];
1347 u8 event_on_vhca_state_teardown_request[0x1];
1348 u8 event_on_vhca_state_in_use[0x1];
1349 u8 event_on_vhca_state_active[0x1];
1350 u8 event_on_vhca_state_allocated[0x1];
1351 u8 event_on_vhca_state_invalid[0x1];
1352 u8 reserved_at_28[0x8];
1353 u8 vhca_id[0x10];
1355 u8 reserved_at_40[0x40];
1357 u8 log_max_srq_sz[0x8];
1358 u8 log_max_qp_sz[0x8];
1359 u8 event_cap[0x1];
1360 u8 reserved_1[0xa];
1361 u8 log_max_qp[0x5];
1363 u8 reserved_2[0xb];
1364 u8 log_max_srq[0x5];
1365 u8 reserved_3[0x10];
1367 u8 reserved_4[0x8];
1368 u8 log_max_cq_sz[0x8];
1369 u8 relaxed_ordering_write_umr[0x1];
1370 u8 relaxed_ordering_read_umr[0x1];
1371 u8 reserved_5[0x9];
1372 u8 log_max_cq[0x5];
1374 u8 log_max_eq_sz[0x8];
1375 u8 relaxed_ordering_write[0x1];
1376 u8 relaxed_ordering_read[0x1];
1377 u8 log_max_mkey[0x6];
1378 u8 reserved_7[0xb];
1379 u8 fast_teardown[0x1];
1380 u8 log_max_eq[0x4];
1382 u8 max_indirection[0x8];
1383 u8 reserved_8[0x1];
1384 u8 log_max_mrw_sz[0x7];
1385 u8 force_teardown[0x1];
1386 u8 reserved_9[0x1];
1387 u8 log_max_bsf_list_size[0x6];
1388 u8 reserved_10[0x2];
1389 u8 log_max_klm_list_size[0x6];
1391 u8 reserved_11[0xa];
1392 u8 log_max_ra_req_dc[0x6];
1393 u8 reserved_12[0xa];
1394 u8 log_max_ra_res_dc[0x6];
1396 u8 reserved_13[0xa];
1397 u8 log_max_ra_req_qp[0x6];
1398 u8 reserved_14[0xa];
1399 u8 log_max_ra_res_qp[0x6];
1401 u8 pad_cap[0x1];
1402 u8 cc_query_allowed[0x1];
1403 u8 cc_modify_allowed[0x1];
1404 u8 start_pad[0x1];
1405 u8 cache_line_128byte[0x1];
1406 u8 reserved_at_165[0xa];
1407 u8 qcam_reg[0x1];
1408 u8 gid_table_size[0x10];
1410 u8 out_of_seq_cnt[0x1];
1411 u8 vport_counters[0x1];
1412 u8 retransmission_q_counters[0x1];
1413 u8 debug[0x1];
1414 u8 modify_rq_counters_set_id[0x1];
1415 u8 rq_delay_drop[0x1];
1416 u8 max_qp_cnt[0xa];
1417 u8 pkey_table_size[0x10];
1419 u8 vport_group_manager[0x1];
1420 u8 vhca_group_manager[0x1];
1421 u8 ib_virt[0x1];
1422 u8 eth_virt[0x1];
1423 u8 reserved_17[0x1];
1424 u8 ets[0x1];
1425 u8 nic_flow_table[0x1];
1426 u8 eswitch_flow_table[0x1];
1427 u8 reserved_18[0x1];
1428 u8 mcam_reg[0x1];
1429 u8 pcam_reg[0x1];
1430 u8 local_ca_ack_delay[0x5];
1431 u8 port_module_event[0x1];
1432 u8 reserved_19[0x5];
1433 u8 port_type[0x2];
1434 u8 num_ports[0x8];
1436 u8 snapshot[0x1];
1437 u8 reserved_20[0x2];
1438 u8 log_max_msg[0x5];
1439 u8 reserved_21[0x4];
1440 u8 max_tc[0x4];
1441 u8 temp_warn_event[0x1];
1442 u8 dcbx[0x1];
1443 u8 general_notification_event[0x1];
1444 u8 reserved_at_1d3[0x2];
1445 u8 fpga[0x1];
1446 u8 rol_s[0x1];
1447 u8 rol_g[0x1];
1448 u8 reserved_23[0x1];
1449 u8 wol_s[0x1];
1450 u8 wol_g[0x1];
1451 u8 wol_a[0x1];
1452 u8 wol_b[0x1];
1453 u8 wol_m[0x1];
1454 u8 wol_u[0x1];
1455 u8 wol_p[0x1];
1457 u8 stat_rate_support[0x10];
1458 u8 reserved_24[0xc];
1459 u8 cqe_version[0x4];
1461 u8 compact_address_vector[0x1];
1462 u8 striding_rq[0x1];
1463 u8 reserved_25[0x1];
1464 u8 ipoib_enhanced_offloads[0x1];
1465 u8 ipoib_ipoib_offloads[0x1];
1466 u8 reserved_26[0x8];
1467 u8 dc_connect_qp[0x1];
1468 u8 dc_cnak_trace[0x1];
1469 u8 drain_sigerr[0x1];
1470 u8 cmdif_checksum[0x2];
1471 u8 sigerr_cqe[0x1];
1472 u8 reserved_27[0x1];
1473 u8 wq_signature[0x1];
1474 u8 sctr_data_cqe[0x1];
1475 u8 reserved_28[0x1];
1476 u8 sho[0x1];
1477 u8 tph[0x1];
1478 u8 rf[0x1];
1479 u8 dct[0x1];
1480 u8 qos[0x1];
1481 u8 eth_net_offloads[0x1];
1482 u8 roce[0x1];
1483 u8 atomic[0x1];
1484 u8 reserved_30[0x1];
1486 u8 cq_oi[0x1];
1487 u8 cq_resize[0x1];
1488 u8 cq_moderation[0x1];
1489 u8 cq_period_mode_modify[0x1];
1490 u8 cq_invalidate[0x1];
1491 u8 reserved_at_225[0x1];
1492 u8 cq_eq_remap[0x1];
1493 u8 pg[0x1];
1494 u8 block_lb_mc[0x1];
1495 u8 exponential_backoff[0x1];
1496 u8 scqe_break_moderation[0x1];
1497 u8 cq_period_start_from_cqe[0x1];
1498 u8 cd[0x1];
1499 u8 atm[0x1];
1500 u8 apm[0x1];
1501 u8 imaicl[0x1];
1502 u8 reserved_32[0x6];
1503 u8 qkv[0x1];
1504 u8 pkv[0x1];
1505 u8 set_deth_sqpn[0x1];
1506 u8 reserved_33[0x3];
1507 u8 xrc[0x1];
1508 u8 ud[0x1];
1509 u8 uc[0x1];
1510 u8 rc[0x1];
1512 u8 uar_4k[0x1];
1513 u8 reserved_at_241[0x9];
1514 u8 uar_sz[0x6];
1515 u8 reserved_35[0x8];
1516 u8 log_pg_sz[0x8];
1518 u8 bf[0x1];
1519 u8 driver_version[0x1];
1520 u8 pad_tx_eth_packet[0x1];
1521 u8 reserved_36[0x8];
1522 u8 log_bf_reg_size[0x5];
1523 u8 reserved_37[0x10];
1525 u8 num_of_diagnostic_counters[0x10];
1526 u8 max_wqe_sz_sq[0x10];
1528 u8 reserved_38[0x10];
1529 u8 max_wqe_sz_rq[0x10];
1531 u8 reserved_39[0x10];
1532 u8 max_wqe_sz_sq_dc[0x10];
1534 u8 reserved_40[0x7];
1535 u8 max_qp_mcg[0x19];
1537 u8 reserved_41[0x10];
1538 u8 flow_counter_bulk_alloc[0x8];
1539 u8 log_max_mcg[0x8];
1541 u8 reserved_42[0x3];
1542 u8 log_max_transport_domain[0x5];
1543 u8 reserved_43[0x3];
1544 u8 log_max_pd[0x5];
1545 u8 reserved_44[0xb];
1546 u8 log_max_xrcd[0x5];
1548 u8 nic_receive_steering_discard[0x1];
1549 u8 reserved_45[0x7];
1550 u8 log_max_flow_counter_bulk[0x8];
1551 u8 max_flow_counter[0x10];
1553 u8 reserved_46[0x3];
1554 u8 log_max_rq[0x5];
1555 u8 reserved_47[0x3];
1556 u8 log_max_sq[0x5];
1557 u8 reserved_48[0x3];
1558 u8 log_max_tir[0x5];
1559 u8 reserved_49[0x3];
1560 u8 log_max_tis[0x5];
1562 u8 basic_cyclic_rcv_wqe[0x1];
1563 u8 reserved_50[0x2];
1564 u8 log_max_rmp[0x5];
1565 u8 reserved_51[0x3];
1566 u8 log_max_rqt[0x5];
1567 u8 reserved_52[0x3];
1568 u8 log_max_rqt_size[0x5];
1569 u8 reserved_53[0x3];
1570 u8 log_max_tis_per_sq[0x5];
1572 u8 reserved_54[0x3];
1573 u8 log_max_stride_sz_rq[0x5];
1574 u8 reserved_55[0x3];
1575 u8 log_min_stride_sz_rq[0x5];
1576 u8 reserved_56[0x3];
1577 u8 log_max_stride_sz_sq[0x5];
1578 u8 reserved_57[0x3];
1579 u8 log_min_stride_sz_sq[0x5];
1581 u8 reserved_58[0x1b];
1582 u8 log_max_wq_sz[0x5];
1584 u8 nic_vport_change_event[0x1];
1585 u8 disable_local_lb_uc[0x1];
1586 u8 disable_local_lb_mc[0x1];
1587 u8 reserved_59[0x8];
1588 u8 log_max_vlan_list[0x5];
1589 u8 reserved_60[0x3];
1590 u8 log_max_current_mc_list[0x5];
1591 u8 reserved_61[0x3];
1592 u8 log_max_current_uc_list[0x5];
1594 u8 general_obj_types[0x40];
1596 u8 sq_ts_format[0x2];
1597 u8 rq_ts_format[0x2];
1598 u8 reserved_at_444[0x4];
1599 u8 create_qp_start_hint[0x18];
1601 u8 reserved_at_460[0x3];
1602 u8 log_max_uctx[0x5];
1603 u8 reserved_at_468[0x2];
1604 u8 ipsec_offload[0x1];
1605 u8 log_max_umem[0x5];
1606 u8 max_num_eqs[0x10];
1608 u8 reserved_at_480[0x1];
1609 u8 tls_tx[0x1];
1610 u8 tls_rx[0x1];
1611 u8 log_max_l2_table[0x5];
1612 u8 reserved_64[0x8];
1613 u8 log_uar_page_sz[0x10];
1615 u8 reserved_65[0x20];
1617 u8 device_frequency_mhz[0x20];
1619 u8 device_frequency_khz[0x20];
1621 u8 reserved_at_500[0x20];
1622 u8 num_of_uars_per_page[0x20];
1623 u8 reserved_at_540[0x40];
1625 u8 log_max_atomic_size_qp[0x8];
1626 u8 reserved_67[0x10];
1627 u8 log_max_atomic_size_dc[0x8];
1629 u8 reserved_at_5a0[0x13];
1630 u8 log_max_dek[0x5];
1631 u8 reserved_at_5b8[0x4];
1632 u8 mini_cqe_resp_stride_index[0x1];
1633 u8 cqe_128_always[0x1];
1634 u8 cqe_compression_128b[0x1];
1636 u8 cqe_compression[0x1];
1638 u8 cqe_compression_timeout[0x10];
1639 u8 cqe_compression_max_num[0x10];
1641 u8 reserved_5e0[0xc0];
1643 u8 uctx_cap[0x20];
1645 u8 reserved_6c0[0xc0];
1647 u8 vhca_tunnel_commands[0x40];
1648 u8 reserved_at_7c0[0x40];
1652 u8 reserved_at_0[0x80];
1654 u8 migratable[0x1];
1655 u8 reserved_at_81[0x1f];
1657 u8 max_reformat_insert_size[0x8];
1658 u8 max_reformat_insert_offset[0x8];
1659 u8 max_reformat_remove_size[0x8];
1660 u8 max_reformat_remove_offset[0x8];
1662 u8 reserved_at_c0[0x8];
1663 u8 migration_multi_load[0x1];
1664 u8 migration_tracking_state[0x1];
1665 u8 reserved_at_ca[0x16];
1667 u8 reserved_at_e0[0xc0];
1669 u8 flow_table_type_2_type[0x8];
1670 u8 reserved_at_1a8[0x3];
1671 u8 log_min_mkey_entity_size[0x5];
1672 u8 reserved_at_1b0[0x10];
1674 u8 reserved_at_1c0[0x60];
1676 u8 reserved_at_220[0x1];
1677 u8 sw_vhca_id_valid[0x1];
1678 u8 sw_vhca_id[0xe];
1679 u8 reserved_at_230[0x10];
1681 u8 reserved_at_240[0xb];
1682 u8 ts_cqe_metadata_size2wqe_counter[0x5];
1683 u8 reserved_at_250[0x10];
1685 u8 reserved_at_260[0x5a0];
1689 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1690 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1691 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2,
1692 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6,
1693 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8,
1694 MLX5_IFC_FLOW_DESTINATION_TYPE_TABLE_TYPE = 0xA,
1706 u8 packet_reformat_id[0x20];
1708 u8 reserved_at_60[0x20];
1714 u8 reserved_0[0x40];
1732 u8 reserved_at_e00[0x200];
1736 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1737 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1738 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1739 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1740 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1744 u8 l3_prot_type[0x1];
1745 u8 l4_prot_type[0x1];
1746 u8 selected_fields[0x1e];
1750 u8 tls_1_2_aes_gcm_128[0x1];
1751 u8 tls_1_3_aes_gcm_128[0x1];
1752 u8 tls_1_2_aes_gcm_256[0x1];
1753 u8 tls_1_3_aes_gcm_256[0x1];
1754 u8 reserved_at_4[0x1c];
1756 u8 reserved_at_20[0x7e0];
1760 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1761 MLX5_WQ_TYPE_CYCLIC = 0x1,
1762 MLX5_WQ_TYPE_STRQ_LINKED_LIST = 0x2,
1763 MLX5_WQ_TYPE_STRQ_CYCLIC = 0x3,
1772 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1773 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1777 u8 wq_type[0x4];
1778 u8 wq_signature[0x1];
1779 u8 end_padding_mode[0x2];
1780 u8 cd_slave[0x1];
1781 u8 reserved_0[0x18];
1783 u8 hds_skip_first_sge[0x1];
1784 u8 log2_hds_buf_size[0x3];
1785 u8 reserved_1[0x7];
1786 u8 page_offset[0x5];
1787 u8 lwm[0x10];
1789 u8 reserved_2[0x8];
1790 u8 pd[0x18];
1792 u8 reserved_3[0x8];
1793 u8 uar_page[0x18];
1795 u8 dbr_addr[0x40];
1797 u8 hw_counter[0x20];
1799 u8 sw_counter[0x20];
1801 u8 reserved_4[0xc];
1802 u8 log_wq_stride[0x4];
1803 u8 reserved_5[0x3];
1804 u8 log_wq_pg_sz[0x5];
1805 u8 reserved_6[0x3];
1806 u8 log_wq_sz[0x5];
1808 u8 dbr_umem_valid[0x1];
1809 u8 wq_umem_valid[0x1];
1810 u8 reserved_7[0x13];
1811 u8 single_wqe_log_num_of_strides[0x3];
1812 u8 two_byte_shift_en[0x1];
1813 u8 reserved_8[0x4];
1814 u8 single_stride_log_num_of_bytes[0x3];
1816 u8 reserved_9[0x4c0];
1818 struct mlx5_ifc_cmd_pas_bits pas[0];
1822 u8 reserved_0[0x8];
1823 u8 rq_num[0x18];
1827 u8 reserved_0[0x10];
1828 u8 mac_addr_47_32[0x10];
1830 u8 mac_addr_31_0[0x20];
1834 u8 reserved_0[0xa0];
1836 u8 min_time_between_cnps[0x20];
1838 u8 reserved_1[0x12];
1839 u8 cnp_dscp[0x6];
1840 u8 reserved_2[0x4];
1841 u8 cnp_prio_mode[0x1];
1842 u8 cnp_802p_prio[0x3];
1844 u8 reserved_3[0x720];
1848 u8 reserved_0[0x60];
1850 u8 reserved_1[0x4];
1851 u8 clamp_tgt_rate[0x1];
1852 u8 reserved_2[0x3];
1853 u8 clamp_tgt_rate_after_time_inc[0x1];
1854 u8 reserved_3[0x17];
1856 u8 reserved_4[0x20];
1858 u8 rpg_time_reset[0x20];
1860 u8 rpg_byte_reset[0x20];
1862 u8 rpg_threshold[0x20];
1864 u8 rpg_max_rate[0x20];
1866 u8 rpg_ai_rate[0x20];
1868 u8 rpg_hai_rate[0x20];
1870 u8 rpg_gd[0x20];
1872 u8 rpg_min_dec_fac[0x20];
1874 u8 rpg_min_rate[0x20];
1876 u8 reserved_5[0xe0];
1878 u8 rate_to_set_on_first_cnp[0x20];
1880 u8 dce_tcp_g[0x20];
1882 u8 dce_tcp_rtt[0x20];
1884 u8 rate_reduce_monitor_period[0x20];
1886 u8 reserved_6[0x20];
1888 u8 initial_alpha_value[0x20];
1890 u8 reserved_7[0x4a0];
1894 u8 reserved_0[0x80];
1896 u8 rppp_max_rps[0x20];
1898 u8 rpg_time_reset[0x20];
1900 u8 rpg_byte_reset[0x20];
1902 u8 rpg_threshold[0x20];
1904 u8 rpg_max_rate[0x20];
1906 u8 rpg_ai_rate[0x20];
1908 u8 rpg_hai_rate[0x20];
1910 u8 rpg_gd[0x20];
1912 u8 rpg_min_dec_fac[0x20];
1914 u8 rpg_min_rate[0x20];
1916 u8 reserved_1[0x640];
1920 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1921 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1922 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1926 u8 resize_field_select[0x20];
1930 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1931 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1932 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1933 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1934 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD_MODE = 0x10,
1935 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_STATUS = 0x20,
1939 u8 modify_field_select[0x20];
1943 u8 field_select_r_roce_np[0x20];
1947 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE = 0x2,
1948 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_CLAMP_TGT_RATE_AFTER_TIME_INC = 0x4,
1949 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_TIME_RESET = 0x8,
1950 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_BYTE_RESET = 0x10,
1951 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_THRESHOLD = 0x20,
1952 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MAX_RATE = 0x40,
1953 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_AI_RATE = 0x80,
1954 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_HAI_RATE = 0x100,
1955 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_DEC_FAC = 0x200,
1956 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RPG_MIN_RATE = 0x400,
1957 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_TO_SET_ON_FIRST_CNP = 0x800,
1958 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_G = 0x1000,
1959 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_DCE_TCP_RTT = 0x2000,
1960 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_RATE_REDUCE_MONITOR_PERIOD = 0x4000,
1961 MLX5_FIELD_SELECT_R_ROCE_RP_FIELD_SELECT_R_ROCE_RP_INITIAL_ALPHA_VALUE = 0x8000,
1965 u8 field_select_r_roce_rp[0x20];
1969 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1970 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1971 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1972 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1973 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1974 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1975 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1976 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1977 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1978 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1982 u8 field_select_8021qaurp[0x20];
1986 u8 reserved_at_0[0x2];
1987 u8 mm[0x2];
1988 u8 reserved_at_4[0x4];
1989 u8 local_port[0x8];
1990 u8 reserved_at_10[0x6];
1991 u8 cm[0x1];
1992 u8 um[0x1];
1993 u8 pm[0x8];
1995 u8 prio_x_buff[0x20];
1997 u8 pm_msb[0x8];
1998 u8 reserved_at_48[0x10];
1999 u8 ctrl_buff[0x4];
2000 u8 untagged_buff[0x4];
2004 u8 reserved_0[0x8];
2005 u8 port_number[0x8];
2006 u8 reserved_1[0x10];
2008 u8 reserved_2[0x1a];
2009 u8 num_app_prio[0x6];
2011 u8 reserved_3[0x40];
2013 struct mlx5_ifc_application_prio_entry_bits app_prio[0];
2017 u8 dcbx_cee_cap[0x1];
2018 u8 dcbx_ieee_cap[0x1];
2019 u8 dcbx_standby_cap[0x1];
2020 u8 reserved_0[0x5];
2021 u8 port_number[0x8];
2022 u8 reserved_1[0xa];
2023 u8 max_application_table_size[0x6];
2025 u8 reserved_2[0x15];
2026 u8 version_oper[0x3];
2027 u8 reserved_3[0x5];
2028 u8 version_admin[0x3];
2030 u8 willing_admin[0x1];
2031 u8 reserved_4[0x3];
2032 u8 pfc_cap_oper[0x4];
2033 u8 reserved_5[0x4];
2034 u8 pfc_cap_admin[0x4];
2035 u8 reserved_6[0x4];
2036 u8 num_of_tc_oper[0x4];
2037 u8 reserved_7[0x4];
2038 u8 num_of_tc_admin[0x4];
2040 u8 remote_willing[0x1];
2041 u8 reserved_8[0x3];
2042 u8 remote_pfc_cap[0x4];
2043 u8 reserved_9[0x14];
2044 u8 remote_num_of_tc[0x4];
2046 u8 reserved_10[0x18];
2047 u8 error[0x8];
2049 u8 reserved_11[0x160];
2053 u8 reserved_at_0[0x8];
2054 u8 local_port[0x8];
2055 u8 reserved_at_10[0x10];
2057 u8 reserved_at_20[0x1b];
2058 u8 hll_time[0x5];
2060 u8 stall_en[0x1];
2061 u8 reserved_at_41[0x1c];
2062 u8 stall_cnt[0x3];
2066 u8 operation_type[0x2];
2067 u8 cap_local_admin[0x1];
2068 u8 cap_remote_admin[0x1];
2069 u8 reserved_0[0x4];
2070 u8 port_number[0x8];
2071 u8 reserved_1[0x10];
2073 u8 reserved_2[0x20];
2075 u8 tc[8][0x40];
2077 u8 global_configuration[0x40];
2081 u8 queue_address_63_32[0x20];
2083 u8 queue_address_31_12[0x14];
2084 u8 reserved_0[0x6];
2085 u8 log_size[0x6];
2089 u8 reserved_1[0x8];
2090 u8 queue_number[0x18];
2092 u8 q_key[0x20];
2094 u8 reserved_2[0x10];
2095 u8 pkey_index[0x10];
2097 u8 reserved_3[0x40];
2101 u8 reserved_0[0x8];
2102 u8 cq_ci[0x10];
2103 u8 reserved_1[0x8];
2107 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_INFINIBAND = 0x0,
2108 MLX5_NODNIC_EVENT_WORD_LINK_TYPE_ETHERNET = 0x1,
2112 MLX5_NODNIC_EVENT_WORD_PORT_STATE_DOWN = 0x0,
2113 MLX5_NODNIC_EVENT_WORD_PORT_STATE_INITIALIZE = 0x1,
2114 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ARMED = 0x2,
2115 MLX5_NODNIC_EVENT_WORD_PORT_STATE_ACTIVE = 0x3,
2119 u8 driver_reset_needed[0x1];
2120 u8 port_management_change_event[0x1];
2121 u8 reserved_0[0x19];
2122 u8 link_type[0x1];
2123 u8 port_state[0x4];
2127 u8 reserved_0[0x10];
2128 u8 vport_num[0x10];
2130 u8 reserved_1[0xc0];
2134 u8 reserved_0[0x10];
2135 u8 function_id[0x10];
2137 u8 num_pages[0x20];
2139 u8 reserved_1[0xa0];
2143 u8 command_completion_vector[0x20];
2145 u8 reserved_0[0xc0];
2149 u8 reserved_0[0x18];
2150 u8 port_num[0x1];
2151 u8 reserved_1[0x3];
2152 u8 vl[0x4];
2154 u8 reserved_2[0xa0];
2158 u8 event_subtype[0x8];
2159 u8 reserved_0[0x8];
2160 u8 congestion_level[0x8];
2161 u8 reserved_1[0x8];
2163 u8 reserved_2[0xa0];
2167 u8 reserved_0[0x60];
2169 u8 gpio_event_hi[0x20];
2171 u8 gpio_event_lo[0x20];
2173 u8 reserved_1[0x40];
2177 u8 reserved_0[0x40];
2179 u8 port_num[0x4];
2180 u8 reserved_1[0x1c];
2182 u8 reserved_2[0x80];
2186 u8 reserved_0[0xe0];
2190 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
2191 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
2195 u8 reserved_0[0x8];
2196 u8 cqn[0x18];
2198 u8 reserved_1[0x20];
2200 u8 reserved_2[0x18];
2201 u8 syndrome[0x8];
2203 u8 reserved_3[0x80];
2207 u8 bytes_commited[0x20];
2209 u8 r_key[0x20];
2211 u8 reserved_0[0x10];
2212 u8 packet_len[0x10];
2214 u8 rdma_op_len[0x20];
2216 u8 rdma_va[0x40];
2218 u8 reserved_1[0x5];
2219 u8 rdma[0x1];
2220 u8 write[0x1];
2221 u8 requestor[0x1];
2222 u8 qp_number[0x18];
2226 u8 bytes_committed[0x20];
2228 u8 reserved_0[0x10];
2229 u8 wqe_index[0x10];
2231 u8 reserved_1[0x10];
2232 u8 len[0x10];
2234 u8 reserved_2[0x60];
2236 u8 reserved_3[0x5];
2237 u8 rdma[0x1];
2238 u8 write_read[0x1];
2239 u8 requestor[0x1];
2240 u8 qpn[0x18];
2244 MLX5_QP_EVENTS_TYPE_QP = 0x0,
2245 MLX5_QP_EVENTS_TYPE_RQ = 0x1,
2246 MLX5_QP_EVENTS_TYPE_SQ = 0x2,
2250 u8 reserved_0[0xa0];
2252 u8 type[0x8];
2253 u8 reserved_1[0x18];
2255 u8 reserved_2[0x8];
2256 u8 qpn_rqn_sqn[0x18];
2260 u8 reserved_0[0xc0];
2262 u8 reserved_1[0x8];
2263 u8 dct_number[0x18];
2267 u8 reserved_0[0xc0];
2269 u8 reserved_1[0x8];
2270 u8 cq_number[0x18];
2274 u8 major[0x10];
2275 u8 reserved_0[0x10];
2277 u8 minor[0x10];
2278 u8 subminor[0x10];
2280 u8 second[0x8];
2281 u8 minute[0x8];
2282 u8 hour[0x8];
2283 u8 reserved_1[0x8];
2285 u8 year[0x10];
2286 u8 month[0x8];
2287 u8 day[0x8];
2291 MLX5_QPC_STATE_RST = 0x0,
2292 MLX5_QPC_STATE_INIT = 0x1,
2293 MLX5_QPC_STATE_RTR = 0x2,
2294 MLX5_QPC_STATE_RTS = 0x3,
2295 MLX5_QPC_STATE_SQER = 0x4,
2296 MLX5_QPC_STATE_SQD = 0x5,
2297 MLX5_QPC_STATE_ERR = 0x6,
2298 MLX5_QPC_STATE_SUSPENDED = 0x9,
2302 MLX5_QPC_ST_RC = 0x0,
2303 MLX5_QPC_ST_UC = 0x1,
2304 MLX5_QPC_ST_UD = 0x2,
2305 MLX5_QPC_ST_XRC = 0x3,
2306 MLX5_QPC_ST_DCI = 0x5,
2307 MLX5_QPC_ST_QP0 = 0x7,
2308 MLX5_QPC_ST_QP1 = 0x8,
2309 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2310 MLX5_QPC_ST_REG_UMR = 0xc,
2314 MLX5_QP_PM_ARMED = 0x0,
2315 MLX5_QP_PM_REARM = 0x1,
2316 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2317 MLX5_QP_PM_MIGRATED = 0x3,
2321 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2322 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2326 MLX5_QPC_MTU_256_BYTES = 0x1,
2327 MLX5_QPC_MTU_512_BYTES = 0x2,
2328 MLX5_QPC_MTU_1K_BYTES = 0x3,
2329 MLX5_QPC_MTU_2K_BYTES = 0x4,
2330 MLX5_QPC_MTU_4K_BYTES = 0x5,
2331 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2335 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2336 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2337 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2338 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2339 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2340 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2341 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2342 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2346 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2347 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2348 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2352 MLX5_QPC_CS_RES_DISABLE = 0x0,
2353 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2354 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2358 MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2359 MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
2360 MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
2364 u8 state[0x4];
2365 u8 lag_tx_port_affinity[0x4];
2366 u8 st[0x8];
2367 u8 reserved_1[0x3];
2368 u8 pm_state[0x2];
2369 u8 reserved_2[0x7];
2370 u8 end_padding_mode[0x2];
2371 u8 reserved_3[0x2];
2373 u8 wq_signature[0x1];
2374 u8 block_lb_mc[0x1];
2375 u8 atomic_like_write_en[0x1];
2376 u8 latency_sensitive[0x1];
2377 u8 reserved_4[0x1];
2378 u8 drain_sigerr[0x1];
2379 u8 reserved_5[0x2];
2380 u8 pd[0x18];
2382 u8 mtu[0x3];
2383 u8 log_msg_max[0x5];
2384 u8 reserved_6[0x1];
2385 u8 log_rq_size[0x4];
2386 u8 log_rq_stride[0x3];
2387 u8 no_sq[0x1];
2388 u8 log_sq_size[0x4];
2389 u8 reserved_at_55[0x3];
2390 u8 ts_format[0x2];
2391 u8 reserved_at_5a[0x1];
2392 u8 rlky[0x1];
2393 u8 ulp_stateless_offload_mode[0x4];
2395 u8 counter_set_id[0x8];
2396 u8 uar_page[0x18];
2398 u8 reserved_8[0x8];
2399 u8 user_index[0x18];
2401 u8 reserved_9[0x3];
2402 u8 log_page_size[0x5];
2403 u8 remote_qpn[0x18];
2409 u8 log_ack_req_freq[0x4];
2410 u8 reserved_10[0x4];
2411 u8 log_sra_max[0x3];
2412 u8 reserved_11[0x2];
2413 u8 retry_count[0x3];
2414 u8 rnr_retry[0x3];
2415 u8 reserved_12[0x1];
2416 u8 fre[0x1];
2417 u8 cur_rnr_retry[0x3];
2418 u8 cur_retry_count[0x3];
2419 u8 reserved_13[0x5];
2421 u8 reserved_14[0x20];
2423 u8 reserved_15[0x8];
2424 u8 next_send_psn[0x18];
2426 u8 reserved_16[0x8];
2427 u8 cqn_snd[0x18];
2429 u8 reserved_at_400[0x8];
2431 u8 deth_sqpn[0x18];
2432 u8 reserved_17[0x20];
2434 u8 reserved_18[0x8];
2435 u8 last_acked_psn[0x18];
2437 u8 reserved_19[0x8];
2438 u8 ssn[0x18];
2440 u8 reserved_20[0x8];
2441 u8 log_rra_max[0x3];
2442 u8 reserved_21[0x1];
2443 u8 atomic_mode[0x4];
2444 u8 rre[0x1];
2445 u8 rwe[0x1];
2446 u8 rae[0x1];
2447 u8 reserved_22[0x1];
2448 u8 page_offset[0x6];
2449 u8 reserved_23[0x3];
2450 u8 cd_slave_receive[0x1];
2451 u8 cd_slave_send[0x1];
2452 u8 cd_master[0x1];
2454 u8 reserved_24[0x3];
2455 u8 min_rnr_nak[0x5];
2456 u8 next_rcv_psn[0x18];
2458 u8 reserved_25[0x8];
2459 u8 xrcd[0x18];
2461 u8 reserved_26[0x8];
2462 u8 cqn_rcv[0x18];
2464 u8 dbr_addr[0x40];
2466 u8 q_key[0x20];
2468 u8 reserved_27[0x5];
2469 u8 rq_type[0x3];
2470 u8 srqn_rmpn[0x18];
2472 u8 reserved_28[0x8];
2473 u8 rmsn[0x18];
2475 u8 hw_sq_wqebb_counter[0x10];
2476 u8 sw_sq_wqebb_counter[0x10];
2478 u8 hw_rq_counter[0x20];
2480 u8 sw_rq_counter[0x20];
2482 u8 reserved_29[0x20];
2484 u8 reserved_30[0xf];
2485 u8 cgs[0x1];
2486 u8 cs_req[0x8];
2487 u8 cs_res[0x8];
2489 u8 dc_access_key[0x40];
2491 u8 reserved_at_680[0x3];
2492 u8 dbr_umem_valid[0x1];
2494 u8 reserved_at_684[0xbc];
2498 u8 source_l3_address[16][0x8];
2500 u8 reserved_0[0x3];
2501 u8 vlan_valid[0x1];
2502 u8 vlan_id[0xc];
2503 u8 source_mac_47_32[0x10];
2505 u8 source_mac_31_0[0x20];
2507 u8 reserved_1[0x14];
2508 u8 roce_l3_type[0x4];
2509 u8 roce_version[0x8];
2511 u8 reserved_2[0x20];
2515 u8 reserved_0[0x1c];
2516 u8 type[0x4];
2518 u8 reserved_1[0x20];
2520 u8 reserved_2[0x8];
2521 u8 psn[0x18];
2523 u8 rkey[0x20];
2525 u8 address[0x40];
2527 u8 byte_count[0x20];
2529 u8 reserved_3[0x20];
2531 u8 atomic_resp[32][0x8];
2535 u8 ethtype[0x10];
2536 u8 prio[0x3];
2537 u8 cfi[0x1];
2538 u8 vid[0xc];
2542 MLX5_FLOW_METER_COLOR_RED = 0x0,
2543 MLX5_FLOW_METER_COLOR_YELLOW = 0x1,
2544 MLX5_FLOW_METER_COLOR_GREEN = 0x2,
2545 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3,
2549 MLX5_EXE_ASO_FLOW_METER = 0x2,
2553 u8 return_reg_id[0x4];
2554 u8 aso_type[0x4];
2555 u8 reserved_at_8[0x14];
2556 u8 action[0x1];
2557 u8 init_color[0x2];
2558 u8 meter_id[0x1];
2566 u8 valid[0x1];
2567 u8 reserved_at_1[0x7];
2568 u8 aso_object_id[0x18];
2574 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0,
2580 u8 group_id[0x20];
2582 u8 reserved_at_40[0x8];
2583 u8 flow_tag[0x18];
2585 u8 reserved_at_60[0x10];
2586 u8 action[0x10];
2588 u8 extended_destination[0x1];
2589 u8 reserved_at_81[0x1];
2590 u8 flow_source[0x2];
2591 u8 encrypt_decrypt_type[0x4];
2592 u8 destination_list_size[0x18];
2594 u8 reserved_at_a0[0x8];
2595 u8 flow_counter_list_size[0x18];
2597 u8 packet_reformat_id[0x20];
2599 u8 modify_header_id[0x20];
2603 u8 encrypt_decrypt_obj_id[0x20];
2604 u8 reserved_at_140[0xc0];
2610 u8 reserved_at_1300[0x500];
2616 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2617 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2621 u8 state[0x4];
2622 u8 log_xrc_srq_size[0x4];
2623 u8 reserved_0[0x18];
2625 u8 wq_signature[0x1];
2626 u8 cont_srq[0x1];
2627 u8 reserved_1[0x1];
2628 u8 rlky[0x1];
2629 u8 basic_cyclic_rcv_wqe[0x1];
2630 u8 log_rq_stride[0x3];
2631 u8 xrcd[0x18];
2633 u8 page_offset[0x6];
2634 u8 reserved_at_46[0x1];
2635 u8 dbr_umem_valid[0x1];
2636 u8 cqn[0x18];
2638 u8 reserved_3[0x20];
2640 u8 reserved_4[0x2];
2641 u8 log_page_size[0x6];
2642 u8 user_index[0x18];
2644 u8 reserved_5[0x20];
2646 u8 reserved_6[0x8];
2647 u8 pd[0x18];
2649 u8 lwm[0x10];
2650 u8 wqe_cnt[0x10];
2652 u8 reserved_7[0x40];
2654 u8 db_record_addr_h[0x20];
2656 u8 db_record_addr_l[0x1e];
2657 u8 reserved_8[0x2];
2659 u8 reserved_9[0x80];
2663 u8 counter_error_queues[0x20];
2665 u8 total_error_queues[0x20];
2667 u8 send_queue_priority_update_flow[0x20];
2669 u8 reserved_at_60[0x20];
2671 u8 nic_receive_steering_discard[0x40];
2673 u8 receive_discard_vport_down[0x40];
2675 u8 transmit_discard_vport_down[0x40];
2677 u8 reserved_at_140[0xec0];
2681 u8 packets[0x40];
2683 u8 octets[0x40];
2687 u8 strict_lag_tx_port_affinity[0x1];
2688 u8 tls_en[0x1];
2689 u8 reserved_at_2[0x2];
2690 u8 lag_tx_port_affinity[0x04];
2692 u8 reserved_at_8[0x4];
2693 u8 prio[0x4];
2694 u8 reserved_1[0x10];
2696 u8 reserved_2[0x100];
2698 u8 reserved_3[0x8];
2699 u8 transport_domain[0x18];
2701 u8 reserved_4[0x8];
2702 u8 underlay_qpn[0x18];
2704 u8 reserved_5[0x8];
2705 u8 pd[0x18];
2707 u8 reserved_6[0x380];
2711 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2712 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2716 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2717 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2721 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0,
2722 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1,
2723 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2,
2727 MLX5_TIRC_SELF_LB_EN_ENABLE_UNICAST = 0x1,
2728 MLX5_TIRC_SELF_LB_EN_ENABLE_MULTICAST = 0x2,
2732 u8 reserved_0[0x20];
2734 u8 disp_type[0x4];
2735 u8 tls_en[0x1];
2736 u8 reserved_at_25[0x1b];
2738 u8 reserved_2[0x40];
2740 u8 reserved_3[0x4];
2741 u8 lro_timeout_period_usecs[0x10];
2742 u8 lro_enable_mask[0x4];
2743 u8 lro_max_msg_sz[0x8];
2745 u8 reserved_4[0x40];
2747 u8 reserved_5[0x8];
2748 u8 inline_rqn[0x18];
2750 u8 rx_hash_symmetric[0x1];
2751 u8 reserved_6[0x1];
2752 u8 tunneled_offload_en[0x1];
2753 u8 reserved_7[0x5];
2754 u8 indirect_table[0x18];
2756 u8 rx_hash_fn[0x4];
2757 u8 reserved_8[0x2];
2758 u8 self_lb_en[0x2];
2759 u8 transport_domain[0x18];
2761 u8 rx_hash_toeplitz_key[10][0x20];
2767 u8 reserved_9[0x4c0];
2771 MLX5_SRQC_STATE_GOOD = 0x0,
2772 MLX5_SRQC_STATE_ERROR = 0x1,
2776 u8 state[0x4];
2777 u8 log_srq_size[0x4];
2778 u8 reserved_0[0x18];
2780 u8 wq_signature[0x1];
2781 u8 cont_srq[0x1];
2782 u8 reserved_1[0x1];
2783 u8 rlky[0x1];
2784 u8 reserved_2[0x1];
2785 u8 log_rq_stride[0x3];
2786 u8 xrcd[0x18];
2788 u8 page_offset[0x6];
2789 u8 reserved_3[0x2];
2790 u8 cqn[0x18];
2792 u8 reserved_4[0x20];
2794 u8 reserved_5[0x2];
2795 u8 log_page_size[0x6];
2796 u8 reserved_6[0x18];
2798 u8 reserved_7[0x20];
2800 u8 reserved_8[0x8];
2801 u8 pd[0x18];
2803 u8 lwm[0x10];
2804 u8 wqe_cnt[0x10];
2806 u8 reserved_9[0x40];
2808 u8 dbr_addr[0x40];
2810 u8 reserved_10[0x80];
2814 MLX5_SQC_STATE_RST = 0x0,
2815 MLX5_SQC_STATE_RDY = 0x1,
2816 MLX5_SQC_STATE_ERR = 0x3,
2820 MLX5_SQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2821 MLX5_SQC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
2822 MLX5_SQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
2826 u8 rlkey[0x1];
2827 u8 cd_master[0x1];
2828 u8 fre[0x1];
2829 u8 flush_in_error_en[0x1];
2830 u8 allow_multi_pkt_send_wqe[0x1];
2831 u8 min_wqe_inline_mode[0x3];
2832 u8 state[0x4];
2833 u8 reg_umr[0x1];
2834 u8 allow_swp[0x1];
2835 u8 reserved_at_e[0x4];
2836 u8 qos_remap_en[0x1];
2837 u8 reserved_at_d[0x7];
2838 u8 ts_format[0x2];
2839 u8 reserved_at_1c[0x4];
2841 u8 reserved_1[0x8];
2842 u8 user_index[0x18];
2844 u8 reserved_2[0x8];
2845 u8 cqn[0x18];
2847 u8 reserved_3[0x80];
2849 u8 qos_para_vport_number[0x10];
2850 u8 packet_pacing_rate_limit_index[0x10];
2852 u8 tis_lst_sz[0x10];
2853 u8 qos_queue_group_id[0x10];
2855 u8 reserved_4[0x8];
2856 u8 queue_handle[0x18];
2858 u8 reserved_5[0x20];
2860 u8 reserved_6[0x8];
2861 u8 tis_num_0[0x18];
2867 u8 opcode[0x10];
2868 u8 uid[0x10];
2870 u8 reserved1[0x10];
2871 u8 op_mod[0x10];
2873 u8 reserved2[0x10];
2874 u8 rate_limit_index[0x10];
2876 u8 reserved_3[0x20];
2880 u8 rate_limit[0x20];
2882 u8 burst_upper_bound[0x20];
2884 u8 reserved_1[0xc];
2885 u8 rate_mode[0x4];
2886 u8 typical_packet_size[0x10];
2888 u8 reserved_2[0x8];
2889 u8 qos_handle[0x18];
2891 u8 reserved_3[0x40];
2895 u8 status[0x8];
2896 u8 reserved_1[0x18];
2898 u8 syndrome[0x20];
2900 u8 reserved_2[0x40];
2906 MLX5_TSAR_TYPE_DWRR = 0,
2912 u8 reserved_0[0x8];
2913 u8 tsar_type[0x8];
2914 u8 reserved_1[0x10];
2918 u8 reserved_0[0x10];
2919 u8 vport_number[0x10];
2923 u8 traffic_class[0x10];
2924 u8 vport_number[0x10];
2928 u8 reserved_0[0x0C];
2929 u8 traffic_class[0x04];
2930 u8 qos_para_vport_number[0x10];
2934 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2935 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2936 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2937 MLX5_SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2941 u8 element_type[0x8];
2942 u8 reserved_at_8[0x18];
2944 u8 element_attributes[0x20];
2946 u8 parent_element_id[0x20];
2948 u8 reserved_at_60[0x40];
2950 u8 bw_share[0x20];
2952 u8 max_average_bw[0x20];
2954 u8 reserved_at_e0[0x120];
2958 u8 reserved_0[0xa0];
2960 u8 reserved_1[0x10];
2961 u8 rqt_max_size[0x10];
2963 u8 reserved_2[0x10];
2964 u8 rqt_actual_size[0x10];
2966 u8 reserved_3[0x6a0];
2968 struct mlx5_ifc_rq_num_bits rq_num[0];
2972 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2973 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2977 MLX5_RQC_STATE_RST = 0x0,
2978 MLX5_RQC_STATE_RDY = 0x1,
2979 MLX5_RQC_STATE_ERR = 0x3,
2983 MLX5_RQC_DROPLESS_MODE_DISABLE = 0x0,
2984 MLX5_RQC_DROPLESS_MODE_ENABLE = 0x1,
2988 MLX5_RQC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
2989 MLX5_RQC_TIMESTAMP_FORMAT_DEFAULT = 0x1,
2990 MLX5_RQC_TIMESTAMP_FORMAT_REAL_TIME = 0x2,
2994 u8 rlkey[0x1];
2995 u8 delay_drop_en[0x1];
2996 u8 scatter_fcs[0x1];
2997 u8 vlan_strip_disable[0x1];
2998 u8 mem_rq_type[0x4];
2999 u8 state[0x4];
3000 u8 reserved_1[0x1];
3001 u8 flush_in_error_en[0x1];
3002 u8 reserved_at_e[0xc];
3003 u8 ts_format[0x2];
3004 u8 reserved_at_1c[0x4];
3006 u8 reserved_3[0x8];
3007 u8 user_index[0x18];
3009 u8 reserved_4[0x8];
3010 u8 cqn[0x18];
3012 u8 counter_set_id[0x8];
3013 u8 reserved_5[0x18];
3015 u8 reserved_6[0x8];
3016 u8 rmpn[0x18];
3018 u8 reserved_7[0xe0];
3024 MLX5_RMPC_STATE_RDY = 0x1,
3025 MLX5_RMPC_STATE_ERR = 0x3,
3029 u8 reserved_0[0x8];
3030 u8 state[0x4];
3031 u8 reserved_1[0x14];
3033 u8 basic_cyclic_rcv_wqe[0x1];
3034 u8 reserved_2[0x1f];
3036 u8 reserved_3[0x140];
3042 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
3043 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_MC_MAC_ADDRESS = 0x1,
3044 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_VLAN_LIST = 0x2,
3048 u8 reserved_0[0x5];
3049 u8 min_wqe_inline_mode[0x3];
3050 u8 reserved_1[0x15];
3051 u8 disable_mc_local_lb[0x1];
3052 u8 disable_uc_local_lb[0x1];
3053 u8 roce_en[0x1];
3055 u8 arm_change_event[0x1];
3056 u8 reserved_2[0x1a];
3057 u8 event_on_mtu[0x1];
3058 u8 event_on_promisc_change[0x1];
3059 u8 event_on_vlan_change[0x1];
3060 u8 event_on_mc_address_change[0x1];
3061 u8 event_on_uc_address_change[0x1];
3063 u8 reserved_3[0xe0];
3065 u8 reserved_4[0x10];
3066 u8 mtu[0x10];
3068 u8 system_image_guid[0x40];
3070 u8 port_guid[0x40];
3072 u8 node_guid[0x40];
3074 u8 reserved_5[0x140];
3076 u8 qkey_violation_counter[0x10];
3077 u8 reserved_6[0x10];
3079 u8 reserved_7[0x420];
3081 u8 promisc_uc[0x1];
3082 u8 promisc_mc[0x1];
3083 u8 promisc_all[0x1];
3084 u8 reserved_8[0x2];
3085 u8 allowed_list_type[0x3];
3086 u8 reserved_9[0xc];
3087 u8 allowed_list_size[0xc];
3091 u8 reserved_10[0x20];
3093 u8 current_uc_mac_address[0][0x40];
3097 MLX5_ACCESS_MODE_PA = 0x0,
3098 MLX5_ACCESS_MODE_MTT = 0x1,
3099 MLX5_ACCESS_MODE_KLM = 0x2,
3100 MLX5_ACCESS_MODE_KSM = 0x3,
3101 MLX5_ACCESS_MODE_SW_ICM = 0x4,
3102 MLX5_ACCESS_MODE_MEMIC = 0x5,
3106 u8 reserved_at_0[0x1];
3107 u8 free[0x1];
3108 u8 reserved_at_2[0x1];
3109 u8 access_mode_4_2[0x3];
3110 u8 reserved_at_6[0x7];
3111 u8 relaxed_ordering_write[0x1];
3112 u8 reserved_at_e[0x1];
3113 u8 small_fence_on_rdma_read_response[0x1];
3114 u8 umr_en[0x1];
3115 u8 a[0x1];
3116 u8 rw[0x1];
3117 u8 rr[0x1];
3118 u8 lw[0x1];
3119 u8 lr[0x1];
3120 u8 access_mode[0x2];
3121 u8 reserved_2[0x8];
3123 u8 qpn[0x18];
3124 u8 mkey_7_0[0x8];
3126 u8 reserved_3[0x20];
3128 u8 length64[0x1];
3129 u8 bsf_en[0x1];
3130 u8 sync_umr[0x1];
3131 u8 reserved_4[0x2];
3132 u8 expected_sigerr_count[0x1];
3133 u8 reserved_5[0x1];
3134 u8 en_rinval[0x1];
3135 u8 pd[0x18];
3137 u8 start_addr[0x40];
3139 u8 len[0x40];
3141 u8 bsf_octword_size[0x20];
3143 u8 reserved_6[0x80];
3145 u8 translations_octword_size[0x20];
3147 u8 reserved_at_1c0[0x19];
3148 u8 relaxed_ordering_read[0x1];
3149 u8 reserved_at_1d9[0x1];
3150 u8 log_page_size[0x5];
3152 u8 reserved_8[0x20];
3156 u8 reserved_0[0x10];
3157 u8 pkey[0x10];
3161 u8 array128_auto[16][0x8];
3165 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_PORT_GUID = 0x0,
3166 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_NODE_GUID = 0x1,
3167 MLX5_HCA_VPORT_CONTEXT_FIELD_SELECT_VPORT_STATE_POLICY = 0x2,
3171 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_SLEEP = 0x1,
3172 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_POLLING = 0x2,
3173 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_DISABLED = 0x3,
3174 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PORTCONFIGURATIONTRAINING = 0x4,
3175 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKUP = 0x5,
3176 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_LINKERRORRECOVERY = 0x6,
3177 MLX5_HCA_VPORT_CONTEXT_PORT_PHYSICAL_STATE_PHYTEST = 0x7,
3181 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_DOWN = 0x0,
3182 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_UP = 0x1,
3183 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_POLICY_FOLLOW = 0x2,
3187 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_DOWN = 0x1,
3188 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_INIT = 0x2,
3189 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ARM = 0x3,
3190 MLX5_HCA_VPORT_CONTEXT_PORT_STATE_ACTIVE = 0x4,
3194 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_DOWN = 0x1,
3195 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_INIT = 0x2,
3196 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ARM = 0x3,
3197 MLX5_HCA_VPORT_CONTEXT_VPORT_STATE_ACTIVE = 0x4,
3201 u8 field_select[0x20];
3203 u8 reserved_0[0xe0];
3205 u8 sm_virt_aware[0x1];
3206 u8 has_smi[0x1];
3207 u8 has_raw[0x1];
3208 u8 grh_required[0x1];
3209 u8 reserved_1[0x1];
3210 u8 min_wqe_inline_mode[0x3];
3211 u8 reserved_2[0x8];
3212 u8 port_physical_state[0x4];
3213 u8 vport_state_policy[0x4];
3214 u8 port_state[0x4];
3215 u8 vport_state[0x4];
3217 u8 reserved_3[0x20];
3219 u8 system_image_guid[0x40];
3221 u8 port_guid[0x40];
3223 u8 node_guid[0x40];
3225 u8 cap_mask1[0x20];
3227 u8 cap_mask1_field_select[0x20];
3229 u8 cap_mask2[0x20];
3231 u8 cap_mask2_field_select[0x20];
3233 u8 reserved_4[0x80];
3235 u8 lid[0x10];
3236 u8 reserved_5[0x4];
3237 u8 init_type_reply[0x4];
3238 u8 lmc[0x3];
3239 u8 subnet_timeout[0x5];
3241 u8 sm_lid[0x10];
3242 u8 sm_sl[0x4];
3243 u8 reserved_6[0xc];
3245 u8 qkey_violation_counter[0x10];
3246 u8 pkey_violation_counter[0x10];
3248 u8 reserved_7[0xca0];
3265 u8 reserved_0[0x8000];
3269 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_DEFAULT = 0x0,
3270 MLX5_FLOW_TABLE_CONTEXT_TABLE_MISS_ACTION_IDENTIFIED = 0x1,
3274 u8 reformat_en[0x1];
3275 u8 decap_en[0x1];
3276 u8 sw_owner[0x1];
3277 u8 termination_table[0x1];
3278 u8 table_miss_action[0x4];
3279 u8 level[0x8];
3280 u8 reserved_at_10[0x8];
3281 u8 log_size[0x8];
3283 u8 reserved_at_20[0x8];
3284 u8 table_miss_id[0x18];
3286 u8 reserved_at_40[0x8];
3287 u8 lag_master_next_table_id[0x18];
3289 u8 reserved_at_60[0x60];
3291 u8 sw_owner_icm_root_1[0x40];
3293 u8 sw_owner_icm_root_0[0x40];
3298 u8 reserved_0[0x3];
3299 u8 vport_svlan_strip[0x1];
3300 u8 vport_cvlan_strip[0x1];
3301 u8 vport_svlan_insert[0x1];
3302 u8 vport_cvlan_insert[0x2];
3303 u8 reserved_1[0x18];
3305 u8 reserved_2[0x20];
3307 u8 svlan_cfi[0x1];
3308 u8 svlan_pcp[0x3];
3309 u8 svlan_id[0xc];
3310 u8 cvlan_cfi[0x1];
3311 u8 cvlan_pcp[0x3];
3312 u8 cvlan_id[0xc];
3314 u8 reserved_3[0x7a0];
3318 MLX5_EQC_STATUS_OK = 0x0,
3319 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
3323 MLX5_EQ_STATE_ARMED = 0x9,
3324 MLX5_EQ_STATE_FIRED = 0xa,
3328 u8 status[0x4];
3329 u8 reserved_0[0x9];
3330 u8 ec[0x1];
3331 u8 oi[0x1];
3332 u8 reserved_1[0x5];
3333 u8 st[0x4];
3334 u8 reserved_2[0x8];
3336 u8 reserved_3[0x20];
3338 u8 reserved_4[0x14];
3339 u8 page_offset[0x6];
3340 u8 reserved_5[0x6];
3342 u8 reserved_6[0x3];
3343 u8 log_eq_size[0x5];
3344 u8 uar_page[0x18];
3346 u8 reserved_7[0x20];
3348 u8 reserved_8[0x18];
3349 u8 intr[0x8];
3351 u8 reserved_9[0x3];
3352 u8 log_page_size[0x5];
3353 u8 reserved_10[0x18];
3355 u8 reserved_11[0x60];
3357 u8 reserved_12[0x8];
3358 u8 consumer_counter[0x18];
3360 u8 reserved_13[0x8];
3361 u8 producer_counter[0x18];
3363 u8 reserved_14[0x80];
3367 MLX5_DCTC_STATE_ACTIVE = 0x0,
3368 MLX5_DCTC_STATE_DRAINING = 0x1,
3369 MLX5_DCTC_STATE_DRAINED = 0x2,
3373 MLX5_DCTC_CS_RES_DISABLE = 0x0,
3374 MLX5_DCTC_CS_RES_NA = 0x1,
3375 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
3379 MLX5_DCTC_MTU_256_BYTES = 0x1,
3380 MLX5_DCTC_MTU_512_BYTES = 0x2,
3381 MLX5_DCTC_MTU_1K_BYTES = 0x3,
3382 MLX5_DCTC_MTU_2K_BYTES = 0x4,
3383 MLX5_DCTC_MTU_4K_BYTES = 0x5,
3387 u8 reserved_0[0x4];
3388 u8 state[0x4];
3389 u8 reserved_1[0x18];
3391 u8 reserved_2[0x8];
3392 u8 user_index[0x18];
3394 u8 reserved_3[0x8];
3395 u8 cqn[0x18];
3397 u8 counter_set_id[0x8];
3398 u8 atomic_mode[0x4];
3399 u8 rre[0x1];
3400 u8 rwe[0x1];
3401 u8 rae[0x1];
3402 u8 atomic_like_write_en[0x1];
3403 u8 latency_sensitive[0x1];
3404 u8 rlky[0x1];
3405 u8 reserved_4[0xe];
3407 u8 reserved_5[0x8];
3408 u8 cs_res[0x8];
3409 u8 reserved_6[0x3];
3410 u8 min_rnr_nak[0x5];
3411 u8 reserved_7[0x8];
3413 u8 reserved_8[0x8];
3414 u8 srqn[0x18];
3416 u8 reserved_9[0x8];
3417 u8 pd[0x18];
3419 u8 tclass[0x8];
3420 u8 reserved_10[0x4];
3421 u8 flow_label[0x14];
3423 u8 dc_access_key[0x40];
3425 u8 reserved_11[0x5];
3426 u8 mtu[0x3];
3427 u8 port[0x8];
3428 u8 pkey_index[0x10];
3430 u8 reserved_12[0x8];
3431 u8 my_addr_index[0x8];
3432 u8 reserved_13[0x8];
3433 u8 hop_limit[0x8];
3435 u8 dc_access_key_violation_count[0x20];
3437 u8 reserved_14[0x14];
3438 u8 dei_cfi[0x1];
3439 u8 eth_prio[0x3];
3440 u8 ecn[0x2];
3441 u8 dscp[0x6];
3443 u8 reserved_15[0x40];
3447 MLX5_CQC_STATUS_OK = 0x0,
3448 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
3449 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
3453 CQE_SIZE_64 = 0x0,
3454 CQE_SIZE_128 = 0x1,
3458 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
3459 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
3463 MLX5_CQ_STATE_SOLICITED_ARMED = 0x6,
3464 MLX5_CQ_STATE_ARMED = 0x9,
3465 MLX5_CQ_STATE_FIRED = 0xa,
3469 u8 status[0x4];
3470 u8 reserved_at_4[0x2];
3471 u8 dbr_umem_valid[0x1];
3472 u8 reserved_at_7[0x1];
3473 u8 cqe_sz[0x3];
3474 u8 cc[0x1];
3475 u8 reserved_1[0x1];
3476 u8 scqe_break_moderation_en[0x1];
3477 u8 oi[0x1];
3478 u8 cq_period_mode[0x2];
3479 u8 cqe_compression_en[0x1];
3480 u8 mini_cqe_res_format[0x2];
3481 u8 st[0x4];
3482 u8 reserved_2[0x8];
3484 u8 reserved_3[0x20];
3486 u8 reserved_4[0x14];
3487 u8 page_offset[0x6];
3488 u8 reserved_5[0x6];
3490 u8 reserved_6[0x3];
3491 u8 log_cq_size[0x5];
3492 u8 uar_page[0x18];
3494 u8 reserved_7[0x4];
3495 u8 cq_period[0xc];
3496 u8 cq_max_count[0x10];
3498 u8 reserved_8[0x18];
3499 u8 c_eqn[0x8];
3501 u8 reserved_9[0x3];
3502 u8 log_page_size[0x5];
3503 u8 reserved_10[0x18];
3505 u8 reserved_11[0x20];
3507 u8 reserved_12[0x8];
3508 u8 last_notified_index[0x18];
3510 u8 reserved_13[0x8];
3511 u8 last_solicit_index[0x18];
3513 u8 reserved_14[0x8];
3514 u8 consumer_counter[0x18];
3516 u8 reserved_15[0x8];
3517 u8 producer_counter[0x18];
3519 u8 reserved_16[0x40];
3521 u8 dbr_addr[0x40];
3528 u8 reserved_0[0x800];
3532 u8 reserved_0[0xc0];
3534 u8 reserved_1[0x8];
3535 u8 ieee_vendor_id[0x18];
3537 u8 reserved_2[0x10];
3538 u8 vsd_vendor_id[0x10];
3540 u8 vsd[208][0x8];
3542 u8 vsd_contd_psid[16][0x8];
3548 u8 reserved_0[0x20];
3555 u8 reserved_0[0x20];
3559 u8 reserved_0[0x6];
3560 u8 lossy[0x1];
3561 u8 epsb[0x1];
3562 u8 reserved_1[0xc];
3563 u8 size[0xc];
3565 u8 xoff_threshold[0x10];
3566 u8 xon_threshold[0x10];
3570 u8 valid[0x2];
3571 u8 reserved_0[0x2];
3572 u8 header_type[0x2];
3573 u8 reserved_1[0x2];
3574 u8 default_location[0x1];
3575 u8 reserved_2[0x7];
3576 u8 version[0x4];
3577 u8 reserved_3[0x3];
3578 u8 length[0x9];
3580 u8 type[0x20];
3582 u8 reserved_4[0x10];
3583 u8 crc16[0x10];
3587 MLX5_XRQC_STATE_GOOD = 0x0,
3588 MLX5_XRQC_STATE_ERROR = 0x1,
3592 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3593 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3597 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3601 u8 log_matching_list_sz[0x4];
3602 u8 reserved_at_4[0xc];
3603 u8 append_next_index[0x10];
3605 u8 sw_phase_cnt[0x10];
3606 u8 hw_phase_cnt[0x10];
3608 u8 reserved_at_40[0x40];
3612 u8 state[0x4];
3613 u8 rlkey[0x1];
3614 u8 reserved_at_5[0xf];
3615 u8 topology[0x4];
3616 u8 reserved_at_18[0x4];
3617 u8 offload[0x4];
3619 u8 reserved_at_20[0x8];
3620 u8 user_index[0x18];
3622 u8 reserved_at_40[0x8];
3623 u8 cqn[0x18];
3625 u8 reserved_at_60[0xa0];
3629 u8 reserved_at_180[0x280];
3637 u8 network_en[0x1];
3638 u8 dma_en[0x1];
3639 u8 promisc_en[0x1];
3640 u8 promisc_multicast_en[0x1];
3641 u8 reserved_0[0x17];
3642 u8 receive_filter_en[0x5];
3644 u8 reserved_1[0x10];
3645 u8 mac_47_32[0x10];
3647 u8 mac_31_0[0x20];
3649 u8 receive_filters_mgid_mac[64][0x8];
3651 u8 gid[16][0x8];
3653 u8 reserved_2[0x10];
3654 u8 lid[0x10];
3656 u8 reserved_3[0xc];
3657 u8 sm_sl[0x4];
3658 u8 sm_lid[0x10];
3660 u8 completion_address_63_32[0x20];
3662 u8 completion_address_31_12[0x14];
3663 u8 reserved_4[0x6];
3664 u8 log_cq_size[0x6];
3666 u8 working_buffer_address_63_32[0x20];
3668 u8 working_buffer_address_31_12[0x14];
3669 u8 reserved_5[0xc];
3673 u8 pkey_index[0x10];
3674 u8 pkey[0x10];
3684 u8 reserved_6[0x400];
3702 u8 reserved_0[0xe0];
3706 u8 reserved_0[0x100];
3708 u8 assert_existptr[0x20];
3710 u8 assert_callra[0x20];
3712 u8 reserved_1[0x40];
3714 u8 fw_version[0x20];
3716 u8 hw_id[0x20];
3718 u8 reserved_2[0x20];
3720 u8 irisc_index[0x8];
3721 u8 synd[0x8];
3722 u8 ext_synd[0x10];
3726 u8 no_lb[0x1];
3727 u8 reserved_0[0x7];
3728 u8 port[0x8];
3729 u8 reserved_1[0x10];
3731 u8 reserved_2[0x60];
3747 u8 reserved_0[0x40];
3749 u8 reserved_1[0x10];
3750 u8 rol_mode[0x8];
3751 u8 wol_mode[0x8];
3755 u8 reserved_0[0x40];
3757 u8 rol_mode_valid[0x1];
3758 u8 wol_mode_valid[0x1];
3759 u8 reserved_1[0xe];
3760 u8 rol_mode[0x8];
3761 u8 wol_mode[0x8];
3763 u8 reserved_2[0x7a0];
3767 u8 virtual_mac_en[0x1];
3768 u8 mac_aux_v[0x1];
3769 u8 reserved_0[0x1e];
3771 u8 reserved_1[0x40];
3775 u8 reserved_2[0x760];
3779 u8 virtual_mac_en[0x1];
3780 u8 mac_aux_v[0x1];
3781 u8 reserved_0[0x1e];
3787 u8 reserved_1[0x760];
3793 u8 reserved_0[0x10];
3794 u8 hash_signature[0x10];
3796 u8 psid[16][0x8];
3798 u8 reserved_1[0x6e0];
3802 u8 reserved_0[0x10];
3803 u8 capability_group[0x10];
3807 u8 nv_access[0x1];
3808 u8 fw_info_psid[0x1];
3809 u8 reserved_0[0x1e];
3811 u8 reserved_1[0x16];
3812 u8 rol_s[0x1];
3813 u8 rol_g[0x1];
3814 u8 reserved_2[0x1];
3815 u8 wol_s[0x1];
3816 u8 wol_g[0x1];
3817 u8 wol_a[0x1];
3818 u8 wol_b[0x1];
3819 u8 wol_m[0x1];
3820 u8 wol_u[0x1];
3821 u8 wol_p[0x1];
3825 u8 status[0x8];
3826 u8 reserved_0[0x18];
3828 u8 reserved_1[0x7e0];
3832 u8 status[0x8];
3833 u8 reserved_0[0x18];
3835 u8 reserved_1[0x7e0];
3839 u8 address_hi[0x20];
3841 u8 address_lo[0x20];
3843 u8 reserved_0[0x7c0];
3847 u8 reserved_0[0x20];
3849 u8 address_hi[0x20];
3851 u8 address_lo[0x20];
3853 u8 reserved_1[0x7a0];
3857 u8 reserved_0[0x11];
3858 u8 status[0x7];
3859 u8 reserved_1[0x8];
3861 u8 register_id[0x10];
3862 u8 reserved_2[0x10];
3864 u8 reserved_3[0x40];
3866 u8 reserved_4[0x5];
3867 u8 len[0xb];
3868 u8 reserved_5[0x10];
3870 u8 register_data[0][0x20];
3874 MLX5_ICMD_ACCESS_REG_IN_METHOD_QUERY = 0x1,
3875 MLX5_ICMD_ACCESS_REG_IN_METHOD_WRITE = 0x2,
3879 u8 constant_1[0x5];
3880 u8 constant_2[0xb];
3881 u8 reserved_0[0x10];
3883 u8 register_id[0x10];
3884 u8 reserved_1[0x1];
3885 u8 method[0x7];
3886 u8 constant_3[0x8];
3888 u8 reserved_2[0x40];
3890 u8 constant_4[0x5];
3891 u8 len[0xb];
3892 u8 reserved_3[0x10];
3894 u8 register_data[0][0x20];
3898 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3899 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3903 u8 status[0x8];
3904 u8 reserved_0[0x18];
3906 u8 syndrome[0x20];
3908 u8 reserved_1[0x3f];
3910 u8 state[0x1];
3914 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3915 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
3916 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2,
3920 u8 opcode[0x10];
3921 u8 reserved_0[0x10];
3923 u8 reserved_1[0x10];
3924 u8 op_mod[0x10];
3926 u8 reserved_2[0x10];
3927 u8 profile[0x10];
3929 u8 reserved_3[0x20];
3933 u8 status[0x8];
3934 u8 reserved_at_8[0x18];
3936 u8 syndrome[0x20];
3938 u8 reserved_at_40[0x40];
3942 u8 opcode[0x10];
3943 u8 reserved_at_10[0x10];
3945 u8 reserved_at_20[0x10];
3946 u8 op_mod[0x10];
3948 u8 reserved_at_40[0x20];
3950 u8 reserved_at_60[0x10];
3951 u8 delay_drop_timeout[0x10];
3955 u8 status[0x8];
3956 u8 reserved_at_8[0x18];
3958 u8 syndrome[0x20];
3960 u8 reserved_at_40[0x20];
3962 u8 reserved_at_60[0x10];
3963 u8 delay_drop_timeout[0x10];
3967 u8 opcode[0x10];
3968 u8 reserved_at_10[0x10];
3970 u8 reserved_at_20[0x10];
3971 u8 op_mod[0x10];
3973 u8 reserved_at_40[0x40];
3977 u8 status[0x8];
3978 u8 reserved_0[0x18];
3980 u8 syndrome[0x20];
3982 u8 reserved_1[0x40];
3986 u8 opcode[0x10];
3987 u8 reserved_0[0x10];
3989 u8 reserved_1[0x10];
3990 u8 op_mod[0x10];
3992 u8 reserved_2[0x8];
3993 u8 qpn[0x18];
3995 u8 reserved_3[0x20];
3999 u8 status[0x8];
4000 u8 reserved_0[0x18];
4002 u8 syndrome[0x20];
4004 u8 reserved_1[0x40];
4008 u8 opcode[0x10];
4009 u8 uid[0x10];
4011 u8 reserved_1[0x10];
4012 u8 op_mod[0x10];
4014 u8 reserved_2[0x8];
4015 u8 qpn[0x18];
4017 u8 reserved_3[0x20];
4019 u8 opt_param_mask[0x20];
4021 u8 reserved_4[0x20];
4025 u8 reserved_5[0x80];
4029 u8 status[0x8];
4030 u8 reserved_0[0x18];
4032 u8 syndrome[0x20];
4034 u8 reserved_1[0x40];
4038 u8 opcode[0x10];
4039 u8 uid[0x10];
4041 u8 reserved_1[0x10];
4042 u8 op_mod[0x10];
4044 u8 reserved_2[0x8];
4045 u8 qpn[0x18];
4047 u8 reserved_3[0x20];
4049 u8 opt_param_mask[0x20];
4051 u8 reserved_4[0x20];
4055 u8 reserved_5[0x80];
4059 u8 status[0x8];
4060 u8 reserved_0[0x18];
4062 u8 syndrome[0x20];
4064 u8 reserved_1[0x40];
4068 u8 opcode[0x10];
4069 u8 reserved_0[0x10];
4071 u8 reserved_1[0x10];
4072 u8 op_mod[0x10];
4074 u8 rol_mode_valid[0x1];
4075 u8 wol_mode_valid[0x1];
4076 u8 reserved_2[0xe];
4077 u8 rol_mode[0x8];
4078 u8 wol_mode[0x8];
4080 u8 reserved_3[0x20];
4084 u8 status[0x8];
4085 u8 reserved_0[0x18];
4087 u8 syndrome[0x20];
4089 u8 reserved_1[0x40];
4093 u8 opcode[0x10];
4094 u8 reserved_0[0x10];
4096 u8 reserved_1[0x10];
4097 u8 op_mod[0x10];
4099 u8 roce_address_index[0x10];
4100 u8 reserved_2[0x10];
4102 u8 reserved_3[0x20];
4108 u8 status[0x8];
4109 u8 reserved_0[0x18];
4111 u8 syndrome[0x20];
4113 u8 reserved_1[0x40];
4117 u8 opcode[0x10];
4118 u8 reserved_0[0x10];
4120 u8 reserved_1[0x10];
4121 u8 op_mod[0x10];
4123 u8 reserved_2[0x8];
4124 u8 qpn[0x18];
4126 u8 reserved_3[0x18];
4127 u8 rdb_list_size[0x8];
4129 struct mlx5_ifc_rdbc_bits rdb_context[0];
4133 u8 status[0x8];
4134 u8 reserved_0[0x18];
4136 u8 syndrome[0x20];
4138 u8 reserved_1[0x40];
4142 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
4143 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
4147 u8 opcode[0x10];
4148 u8 reserved_0[0x10];
4150 u8 reserved_1[0x10];
4151 u8 op_mod[0x10];
4153 u8 reserved_2[0x20];
4155 u8 reserved_3[0x6];
4156 u8 demux_mode[0x2];
4157 u8 reserved_4[0x18];
4161 u8 status[0x8];
4162 u8 reserved_0[0x18];
4164 u8 syndrome[0x20];
4166 u8 reserved_1[0x40];
4170 u8 opcode[0x10];
4171 u8 reserved_0[0x10];
4173 u8 reserved_1[0x10];
4174 u8 op_mod[0x10];
4176 u8 reserved_2[0x60];
4178 u8 reserved_3[0x8];
4179 u8 table_index[0x18];
4181 u8 reserved_4[0x20];
4183 u8 reserved_5[0x13];
4184 u8 vlan_valid[0x1];
4185 u8 vlan[0xc];
4189 u8 reserved_6[0xc0];
4193 u8 status[0x8];
4194 u8 reserved_0[0x18];
4196 u8 syndrome[0x20];
4198 u8 reserved_1[0x40];
4202 u8 opcode[0x10];
4203 u8 reserved_0[0x10];
4205 u8 reserved_1[0x10];
4206 u8 op_mod[0x10];
4208 u8 reserved_2[0x10];
4209 u8 current_issi[0x10];
4211 u8 reserved_3[0x20];
4215 u8 status[0x8];
4216 u8 reserved_0[0x18];
4218 u8 syndrome[0x20];
4220 u8 reserved_1[0x40];
4224 u8 opcode[0x10];
4225 u8 reserved_0[0x10];
4227 u8 reserved_1[0x10];
4228 u8 op_mod[0x10];
4230 u8 reserved_2[0x40];
4236 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
4237 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
4238 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
4239 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
4243 u8 status[0x8];
4244 u8 reserved_0[0x18];
4246 u8 syndrome[0x20];
4248 u8 reserved_1[0x40];
4252 u8 opcode[0x10];
4253 u8 reserved_at_10[0x10];
4255 u8 reserved_at_20[0x10];
4256 u8 op_mod[0x10];
4258 u8 other_vport[0x1];
4259 u8 reserved_at_41[0xf];
4260 u8 vport_number[0x10];
4262 u8 reserved_at_60[0x20];
4264 u8 table_type[0x8];
4265 u8 reserved_at_88[0x7];
4266 u8 table_of_other_vport[0x1];
4267 u8 table_vport_number[0x10];
4269 u8 reserved_at_a0[0x8];
4270 u8 table_id[0x18];
4272 u8 reserved_at_c0[0x8];
4273 u8 underlay_qpn[0x18];
4274 u8 table_eswitch_owner_vhca_id_valid[0x1];
4275 u8 reserved_at_e1[0xf];
4276 u8 table_eswitch_owner_vhca_id[0x10];
4277 u8 reserved_at_100[0x100];
4281 u8 status[0x8];
4282 u8 reserved_0[0x18];
4284 u8 syndrome[0x20];
4286 u8 reserved_1[0x40];
4290 u8 opcode[0x10];
4291 u8 reserved_at_10[0x10];
4293 u8 reserved_at_20[0x10];
4294 u8 op_mod[0x10];
4296 u8 other_vport[0x1];
4297 u8 reserved_at_41[0xf];
4298 u8 vport_number[0x10];
4300 u8 reserved_at_60[0x20];
4302 u8 table_type[0x8];
4303 u8 reserved_at_88[0x18];
4305 u8 reserved_at_a0[0x8];
4306 u8 table_id[0x18];
4308 u8 ignore_flow_level[0x1];
4309 u8 reserved_at_c1[0x17];
4310 u8 modify_enable_mask[0x8];
4312 u8 reserved_at_e0[0x20];
4314 u8 flow_index[0x20];
4316 u8 reserved_at_120[0xe0];
4322 u8 status[0x8];
4323 u8 reserved_0[0x18];
4325 u8 syndrome[0x20];
4327 u8 reserved_1[0x40];
4331 u8 opcode[0x10];
4332 u8 reserved_0[0x10];
4334 u8 reserved_1[0x10];
4335 u8 op_mod[0x10];
4337 u8 reserved_2[0x40];
4339 u8 driver_version[64][0x8];
4343 u8 status[0x8];
4344 u8 reserved_0[0x18];
4346 u8 syndrome[0x20];
4348 u8 reserved_1[0x40];
4352 u8 opcode[0x10];
4353 u8 reserved_0[0x10];
4355 u8 reserved_1[0x10];
4356 u8 op_mod[0x10];
4358 u8 enable[0x1];
4359 u8 reserved_2[0x1f];
4361 u8 reserved_3[0x160];
4367 u8 status[0x8];
4368 u8 reserved_0[0x18];
4370 u8 syndrome[0x20];
4372 u8 reserved_1[0x40];
4376 u8 opcode[0x10];
4377 u8 reserved_0[0x10];
4379 u8 reserved_1[0x10];
4380 u8 op_mod[0x10];
4382 u8 reserved_2[0x20];
4384 u8 reserved_3[0x9];
4385 u8 device_burst_size[0x17];
4389 u8 status[0x8];
4390 u8 reserved_0[0x18];
4392 u8 syndrome[0x20];
4394 u8 reserved_1[0x40];
4398 u8 opcode[0x10];
4399 u8 uid[0x10];
4401 u8 reserved_1[0x10];
4402 u8 op_mod[0x10];
4404 u8 reserved_2[0x8];
4405 u8 qpn[0x18];
4407 u8 reserved_3[0x20];
4409 u8 opt_param_mask[0x20];
4411 u8 reserved_4[0x20];
4415 u8 reserved_5[0x80];
4419 u8 status[0x8];
4420 u8 reserved_0[0x18];
4422 u8 syndrome[0x20];
4424 u8 reserved_1[0x40];
4428 u8 opcode[0x10];
4429 u8 uid[0x10];
4431 u8 reserved_1[0x10];
4432 u8 op_mod[0x10];
4434 u8 reserved_2[0x8];
4435 u8 qpn[0x18];
4437 u8 reserved_3[0x20];
4439 u8 opt_param_mask[0x20];
4441 u8 reserved_4[0x20];
4445 u8 reserved_5[0x80];
4449 u8 status[0x8];
4450 u8 reserved_0[0x18];
4452 u8 syndrome[0x20];
4454 u8 reserved_1[0x40];
4458 u8 opcode[0x10];
4459 u8 uid[0x10];
4461 u8 reserved_1[0x10];
4462 u8 op_mod[0x10];
4464 u8 reserved_2[0x8];
4465 u8 qpn[0x18];
4467 u8 reserved_3[0x20];
4469 u8 opt_param_mask[0x20];
4471 u8 reserved_4[0x20];
4475 u8 reserved_5[0x80];
4479 u8 status[0x8];
4480 u8 reserved_at_8[0x18];
4482 u8 syndrome[0x20];
4484 u8 reserved_at_40[0x40];
4490 u8 opcode[0x10];
4491 u8 reserved_at_10[0x10];
4493 u8 reserved_at_20[0x10];
4494 u8 op_mod[0x10];
4496 u8 reserved_at_40[0x8];
4497 u8 xrqn[0x18];
4499 u8 reserved_at_60[0x20];
4503 u8 status[0x8];
4504 u8 reserved_0[0x18];
4506 u8 syndrome[0x20];
4508 u8 reserved_1[0x40];
4512 u8 opcode[0x10];
4513 u8 reserved_0[0x10];
4515 u8 reserved_1[0x10];
4516 u8 op_mod[0x10];
4518 u8 reserved_2[0x8];
4519 u8 qpn[0x18];
4521 u8 reserved_3[0x20];
4525 u8 status[0x8];
4526 u8 reserved_0[0x18];
4528 u8 syndrome[0x20];
4530 u8 reserved_1[0x40];
4534 u8 reserved_2[0x600];
4536 u8 pas[0][0x40];
4540 u8 opcode[0x10];
4541 u8 uid[0x10];
4543 u8 reserved_1[0x10];
4544 u8 op_mod[0x10];
4546 u8 reserved_2[0x8];
4547 u8 xrc_srqn[0x18];
4549 u8 reserved_3[0x20];
4553 u8 status[0x8];
4554 u8 reserved_0[0x18];
4556 u8 syndrome[0x20];
4558 u8 reserved_1[0x10];
4559 u8 rol_mode[0x8];
4560 u8 wol_mode[0x8];
4562 u8 reserved_2[0x20];
4566 u8 opcode[0x10];
4567 u8 reserved_0[0x10];
4569 u8 reserved_1[0x10];
4570 u8 op_mod[0x10];
4572 u8 reserved_2[0x40];
4576 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
4577 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
4581 u8 status[0x8];
4582 u8 reserved_0[0x18];
4584 u8 syndrome[0x20];
4586 u8 reserved_1[0x20];
4588 u8 reserved_2[0x18];
4589 u8 admin_state[0x4];
4590 u8 state[0x4];
4594 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
4595 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
4596 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
4600 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
4601 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
4602 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
4603 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
4604 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10,
4605 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
4606 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
4607 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80,
4608 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100,
4609 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400,
4610 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800,
4611 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000,
4612 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000,
4613 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000,
4617 u8 opcode[0x10];
4618 u8 reserved_0[0x10];
4620 u8 reserved_1[0x10];
4621 u8 op_mod[0x10];
4623 u8 other_vport[0x1];
4624 u8 reserved_2[0xf];
4625 u8 vport_number[0x10];
4627 u8 reserved_3[0x20];
4631 u8 status[0x8];
4632 u8 reserved_at_8[0x18];
4634 u8 syndrome[0x20];
4636 u8 reserved_at_40[0x40];
4642 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0,
4646 u8 opcode[0x10];
4647 u8 reserved_at_10[0x10];
4649 u8 reserved_at_20[0x10];
4650 u8 op_mod[0x10];
4652 u8 other_vport[0x1];
4653 u8 reserved_at_41[0xf];
4654 u8 vport_number[0x10];
4656 u8 reserved_at_60[0x20];
4660 u8 status[0x8];
4661 u8 reserved_0[0x18];
4663 u8 syndrome[0x20];
4665 u8 reserved_1[0x40];
4691 u8 reserved_2[0xa00];
4695 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
4699 u8 opcode[0x10];
4700 u8 reserved_0[0x10];
4702 u8 reserved_1[0x10];
4703 u8 op_mod[0x10];
4705 u8 other_vport[0x1];
4706 u8 reserved_2[0xb];
4707 u8 port_num[0x4];
4708 u8 vport_number[0x10];
4710 u8 reserved_3[0x60];
4712 u8 clear[0x1];
4713 u8 reserved_4[0x1f];
4715 u8 reserved_5[0x20];
4719 u8 status[0x8];
4720 u8 reserved_0[0x18];
4722 u8 syndrome[0x20];
4724 u8 reserved_1[0x40];
4730 u8 opcode[0x10];
4731 u8 reserved_0[0x10];
4733 u8 reserved_1[0x10];
4734 u8 op_mod[0x10];
4736 u8 reserved_2[0x8];
4737 u8 tisn[0x18];
4739 u8 reserved_3[0x20];
4743 u8 status[0x8];
4744 u8 reserved_0[0x18];
4746 u8 syndrome[0x20];
4748 u8 reserved_1[0xc0];
4754 u8 opcode[0x10];
4755 u8 reserved_0[0x10];
4757 u8 reserved_1[0x10];
4758 u8 op_mod[0x10];
4760 u8 reserved_2[0x8];
4761 u8 tirn[0x18];
4763 u8 reserved_3[0x20];
4767 u8 status[0x8];
4768 u8 reserved_0[0x18];
4770 u8 syndrome[0x20];
4772 u8 reserved_1[0x40];
4776 u8 reserved_2[0x600];
4778 u8 pas[0][0x40];
4782 u8 opcode[0x10];
4783 u8 reserved_0[0x10];
4785 u8 reserved_1[0x10];
4786 u8 op_mod[0x10];
4788 u8 reserved_2[0x8];
4789 u8 srqn[0x18];
4791 u8 reserved_3[0x20];
4795 u8 status[0x8];
4796 u8 reserved_0[0x18];
4798 u8 syndrome[0x20];
4800 u8 reserved_1[0xc0];
4806 u8 opcode[0x10];
4807 u8 reserved_0[0x10];
4809 u8 reserved_1[0x10];
4810 u8 op_mod[0x10];
4812 u8 reserved_2[0x8];
4813 u8 sqn[0x18];
4815 u8 reserved_3[0x20];
4819 u8 status[0x8];
4820 u8 reserved_0[0x18];
4822 u8 syndrome[0x20];
4824 u8 dump_fill_mkey[0x20];
4826 u8 resd_lkey[0x20];
4830 u8 opcode[0x10];
4831 u8 reserved_0[0x10];
4833 u8 reserved_1[0x10];
4834 u8 op_mod[0x10];
4836 u8 reserved_2[0x40];
4840 u8 status[0x8];
4841 u8 reserved_at_8[0x18];
4843 u8 syndrome[0x20];
4845 u8 reserved_at_40[0xc0];
4849 u8 reserved_at_300[0x100];
4853 MLX5_SCHEDULING_ELEMENT_IN_HIERARCHY_E_SWITCH = 0x2,
4857 u8 opcode[0x10];
4858 u8 reserved_at_10[0x10];
4860 u8 reserved_at_20[0x10];
4861 u8 op_mod[0x10];
4863 u8 scheduling_hierarchy[0x8];
4864 u8 reserved_at_48[0x18];
4866 u8 scheduling_element_id[0x20];
4868 u8 reserved_at_80[0x180];
4872 u8 status[0x8];
4873 u8 reserved_0[0x18];
4875 u8 syndrome[0x20];
4877 u8 reserved_1[0xc0];
4883 u8 opcode[0x10];
4884 u8 reserved_0[0x10];
4886 u8 reserved_1[0x10];
4887 u8 op_mod[0x10];
4889 u8 reserved_2[0x8];
4890 u8 rqtn[0x18];
4892 u8 reserved_3[0x20];
4896 u8 status[0x8];
4897 u8 reserved_0[0x18];
4899 u8 syndrome[0x20];
4901 u8 reserved_1[0xc0];
4907 u8 opcode[0x10];
4908 u8 reserved_0[0x10];
4910 u8 reserved_1[0x10];
4911 u8 op_mod[0x10];
4913 u8 reserved_2[0x8];
4914 u8 rqn[0x18];
4916 u8 reserved_3[0x20];
4920 u8 status[0x8];
4921 u8 reserved_0[0x18];
4923 u8 syndrome[0x20];
4925 u8 reserved_1[0x40];
4931 u8 opcode[0x10];
4932 u8 reserved_0[0x10];
4934 u8 reserved_1[0x10];
4935 u8 op_mod[0x10];
4937 u8 roce_address_index[0x10];
4938 u8 reserved_2[0x10];
4940 u8 reserved_3[0x20];
4944 u8 status[0x8];
4945 u8 reserved_0[0x18];
4947 u8 syndrome[0x20];
4949 u8 reserved_1[0xc0];
4955 u8 opcode[0x10];
4956 u8 reserved_0[0x10];
4958 u8 reserved_1[0x10];
4959 u8 op_mod[0x10];
4961 u8 reserved_2[0x8];
4962 u8 rmpn[0x18];
4964 u8 reserved_3[0x20];
4968 u8 status[0x8];
4969 u8 reserved_0[0x18];
4971 u8 syndrome[0x20];
4973 u8 reserved_1[0x20];
4975 u8 reserved_2[0x18];
4976 u8 rdb_list_size[0x8];
4978 struct mlx5_ifc_rdbc_bits rdb_context[0];
4982 u8 opcode[0x10];
4983 u8 reserved_0[0x10];
4985 u8 reserved_1[0x10];
4986 u8 op_mod[0x10];
4988 u8 reserved_2[0x8];
4989 u8 qpn[0x18];
4991 u8 reserved_3[0x20];
4995 u8 status[0x8];
4996 u8 reserved_0[0x18];
4998 u8 syndrome[0x20];
5000 u8 reserved_1[0x40];
5002 u8 opt_param_mask[0x20];
5004 u8 reserved_2[0x20];
5008 u8 reserved_3[0x80];
5010 u8 pas[0][0x40];
5014 u8 opcode[0x10];
5015 u8 reserved_0[0x10];
5017 u8 reserved_1[0x10];
5018 u8 op_mod[0x10];
5020 u8 reserved_2[0x8];
5021 u8 qpn[0x18];
5023 u8 reserved_3[0x20];
5027 u8 status[0x8];
5028 u8 reserved_0[0x18];
5030 u8 syndrome[0x20];
5032 u8 reserved_1[0x40];
5034 u8 rx_write_requests[0x20];
5036 u8 reserved_2[0x20];
5038 u8 rx_read_requests[0x20];
5040 u8 reserved_3[0x20];
5042 u8 rx_atomic_requests[0x20];
5044 u8 reserved_4[0x20];
5046 u8 rx_dct_connect[0x20];
5048 u8 reserved_5[0x20];
5050 u8 out_of_buffer[0x20];
5052 u8 reserved_7[0x20];
5054 u8 out_of_sequence[0x20];
5056 u8 reserved_8[0x20];
5058 u8 duplicate_request[0x20];
5060 u8 reserved_9[0x20];
5062 u8 rnr_nak_retry_err[0x20];
5064 u8 reserved_10[0x20];
5066 u8 packet_seq_err[0x20];
5068 u8 reserved_11[0x20];
5070 u8 implied_nak_seq_err[0x20];
5072 u8 reserved_12[0x20];
5074 u8 local_ack_timeout_err[0x20];
5076 u8 reserved_13[0x20];
5078 u8 resp_rnr_nak[0x20];
5080 u8 reserved_14[0x20];
5082 u8 req_rnr_retries_exceeded[0x20];
5084 u8 reserved_15[0x460];
5088 u8 opcode[0x10];
5089 u8 reserved_0[0x10];
5091 u8 reserved_1[0x10];
5092 u8 op_mod[0x10];
5094 u8 reserved_2[0x80];
5096 u8 clear[0x1];
5097 u8 reserved_3[0x1f];
5099 u8 reserved_4[0x18];
5100 u8 counter_set_id[0x8];
5104 u8 status[0x8];
5105 u8 reserved_0[0x18];
5107 u8 syndrome[0x20];
5109 u8 reserved_1[0x10];
5110 u8 function_id[0x10];
5112 u8 num_pages[0x20];
5116 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
5117 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
5118 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
5122 u8 opcode[0x10];
5123 u8 reserved_0[0x10];
5125 u8 reserved_1[0x10];
5126 u8 op_mod[0x10];
5128 u8 reserved_2[0x10];
5129 u8 function_id[0x10];
5131 u8 reserved_3[0x20];
5135 u8 status[0x8];
5136 u8 reserved_0[0x18];
5138 u8 syndrome[0x20];
5140 u8 reserved_1[0x40];
5146 u8 opcode[0x10];
5147 u8 reserved_0[0x10];
5149 u8 reserved_1[0x10];
5150 u8 op_mod[0x10];
5152 u8 other_vport[0x1];
5153 u8 reserved_2[0xf];
5154 u8 vport_number[0x10];
5156 u8 reserved_3[0x5];
5157 u8 allowed_list_type[0x3];
5158 u8 reserved_4[0x18];
5162 u8 status[0x8];
5163 u8 reserved_0[0x18];
5165 u8 syndrome[0x20];
5167 u8 reserved_1[0x40];
5171 u8 reserved_2[0x600];
5173 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
5175 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
5179 u8 opcode[0x10];
5180 u8 reserved_0[0x10];
5182 u8 reserved_1[0x10];
5183 u8 op_mod[0x10];
5185 u8 reserved_2[0x8];
5186 u8 mkey_index[0x18];
5188 u8 pg_access[0x1];
5189 u8 reserved_3[0x1f];
5193 u8 status[0x8];
5194 u8 reserved_0[0x18];
5196 u8 syndrome[0x20];
5198 u8 reserved_1[0x40];
5200 u8 mad_dumux_parameters_block[0x20];
5204 u8 opcode[0x10];
5205 u8 reserved_0[0x10];
5207 u8 reserved_1[0x10];
5208 u8 op_mod[0x10];
5210 u8 reserved_2[0x40];
5214 u8 status[0x8];
5215 u8 reserved_0[0x18];
5217 u8 syndrome[0x20];
5219 u8 reserved_1[0xa0];
5221 u8 reserved_2[0x13];
5222 u8 vlan_valid[0x1];
5223 u8 vlan[0xc];
5227 u8 reserved_3[0xc0];
5231 u8 opcode[0x10];
5232 u8 reserved_0[0x10];
5234 u8 reserved_1[0x10];
5235 u8 op_mod[0x10];
5237 u8 reserved_2[0x60];
5239 u8 reserved_3[0x8];
5240 u8 table_index[0x18];
5242 u8 reserved_4[0x140];
5246 u8 status[0x8];
5247 u8 reserved_0[0x18];
5249 u8 syndrome[0x20];
5251 u8 reserved_1[0x10];
5252 u8 current_issi[0x10];
5254 u8 reserved_2[0xa0];
5256 u8 supported_issi_reserved[76][0x8];
5257 u8 supported_issi_dw0[0x20];
5261 u8 opcode[0x10];
5262 u8 reserved_0[0x10];
5264 u8 reserved_1[0x10];
5265 u8 op_mod[0x10];
5267 u8 reserved_2[0x40];
5271 u8 status[0x8];
5272 u8 reserved_0[0x18];
5274 u8 syndrome[0x20];
5276 u8 reserved_1[0x40];
5278 struct mlx5_ifc_pkey_bits pkey[0];
5282 u8 opcode[0x10];
5283 u8 reserved_0[0x10];
5285 u8 reserved_1[0x10];
5286 u8 op_mod[0x10];
5288 u8 other_vport[0x1];
5289 u8 reserved_2[0xb];
5290 u8 port_num[0x4];
5291 u8 vport_number[0x10];
5293 u8 reserved_3[0x10];
5294 u8 pkey_index[0x10];
5298 u8 status[0x8];
5299 u8 reserved_0[0x18];
5301 u8 syndrome[0x20];
5303 u8 reserved_1[0x20];
5305 u8 gids_num[0x10];
5306 u8 reserved_2[0x10];
5308 struct mlx5_ifc_array128_auto_bits gid[0];
5312 u8 opcode[0x10];
5313 u8 reserved_0[0x10];
5315 u8 reserved_1[0x10];
5316 u8 op_mod[0x10];
5318 u8 other_vport[0x1];
5319 u8 reserved_2[0xb];
5320 u8 port_num[0x4];
5321 u8 vport_number[0x10];
5323 u8 reserved_3[0x10];
5324 u8 gid_index[0x10];
5328 u8 status[0x8];
5329 u8 reserved_0[0x18];
5331 u8 syndrome[0x20];
5333 u8 reserved_1[0x40];
5339 u8 opcode[0x10];
5340 u8 reserved_0[0x10];
5342 u8 reserved_1[0x10];
5343 u8 op_mod[0x10];
5345 u8 other_vport[0x1];
5346 u8 reserved_2[0xb];
5347 u8 port_num[0x4];
5348 u8 vport_number[0x10];
5350 u8 reserved_3[0x20];
5354 u8 status[0x8];
5355 u8 reserved_0[0x18];
5357 u8 syndrome[0x20];
5359 u8 reserved_1[0x40];
5365 u8 opcode[0x10];
5366 u8 reserved_0[0x10];
5368 u8 reserved_1[0x10];
5369 u8 op_mod[0x10];
5371 u8 reserved_2[0x40];
5375 u8 status[0x8];
5376 u8 reserved_at_8[0x18];
5378 u8 syndrome[0x20];
5380 u8 reserved_at_40[0x80];
5386 u8 opcode[0x10];
5387 u8 reserved_0[0x10];
5389 u8 reserved_1[0x10];
5390 u8 op_mod[0x10];
5392 u8 other_vport[0x1];
5393 u8 reserved_2[0xf];
5394 u8 vport_number[0x10];
5396 u8 reserved_3[0x20];
5398 u8 table_type[0x8];
5399 u8 reserved_4[0x18];
5401 u8 reserved_5[0x8];
5402 u8 table_id[0x18];
5404 u8 reserved_6[0x140];
5408 u8 status[0x8];
5409 u8 reserved_0[0x18];
5411 u8 syndrome[0x20];
5413 u8 reserved_1[0x1c0];
5419 u8 opcode[0x10];
5420 u8 reserved_0[0x10];
5422 u8 reserved_1[0x10];
5423 u8 op_mod[0x10];
5425 u8 other_vport[0x1];
5426 u8 reserved_2[0xf];
5427 u8 vport_number[0x10];
5429 u8 reserved_3[0x20];
5431 u8 table_type[0x8];
5432 u8 reserved_4[0x18];
5434 u8 reserved_5[0x8];
5435 u8 table_id[0x18];
5437 u8 reserved_6[0x40];
5439 u8 flow_index[0x20];
5441 u8 reserved_7[0xe0];
5445 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5446 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5447 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5451 u8 status[0x8];
5452 u8 reserved_0[0x18];
5454 u8 syndrome[0x20];
5456 u8 reserved_1[0xa0];
5458 u8 start_flow_index[0x20];
5460 u8 reserved_2[0x20];
5462 u8 end_flow_index[0x20];
5464 u8 reserved_3[0xa0];
5466 u8 reserved_4[0x18];
5467 u8 match_criteria_enable[0x8];
5471 u8 reserved_5[0xe00];
5475 u8 opcode[0x10];
5476 u8 reserved_0[0x10];
5478 u8 reserved_1[0x10];
5479 u8 op_mod[0x10];
5481 u8 other_vport[0x1];
5482 u8 reserved_2[0xf];
5483 u8 vport_number[0x10];
5485 u8 reserved_3[0x20];
5487 u8 table_type[0x8];
5488 u8 reserved_4[0x18];
5490 u8 reserved_5[0x8];
5491 u8 table_id[0x18];
5493 u8 group_id[0x20];
5495 u8 reserved_6[0x120];
5499 u8 status[0x8];
5500 u8 reserved_at_8[0x18];
5502 u8 syndrome[0x20];
5504 u8 reserved_at_40[0x40];
5506 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
5510 u8 opcode[0x10];
5511 u8 reserved_at_10[0x10];
5513 u8 reserved_at_20[0x10];
5514 u8 op_mod[0x10];
5516 u8 reserved_at_40[0x80];
5518 u8 clear[0x1];
5519 u8 reserved_at_c1[0xf];
5520 u8 num_of_counters[0x10];
5522 u8 reserved_at_e0[0x10];
5523 u8 flow_counter_id[0x10];
5527 u8 status[0x8];
5528 u8 reserved_0[0x18];
5530 u8 syndrome[0x20];
5532 u8 reserved_1[0x40];
5538 u8 opcode[0x10];
5539 u8 reserved_0[0x10];
5541 u8 reserved_1[0x10];
5542 u8 op_mod[0x10];
5544 u8 other_vport[0x1];
5545 u8 reserved_2[0xf];
5546 u8 vport_number[0x10];
5548 u8 reserved_3[0x20];
5552 u8 status[0x8];
5553 u8 reserved_0[0x18];
5555 u8 syndrome[0x20];
5557 u8 reserved_1[0x40];
5561 u8 reserved_2[0x40];
5563 u8 event_bitmask[0x40];
5565 u8 reserved_3[0x580];
5567 u8 pas[0][0x40];
5571 u8 opcode[0x10];
5572 u8 reserved_0[0x10];
5574 u8 reserved_1[0x10];
5575 u8 op_mod[0x10];
5577 u8 reserved_2[0x18];
5578 u8 eq_number[0x8];
5580 u8 reserved_3[0x20];
5584 u8 action_type[0x4];
5585 u8 field[0xc];
5586 u8 reserved_at_10[0x3];
5587 u8 offset[0x5];
5588 u8 reserved_at_18[0x3];
5589 u8 length[0x5];
5591 u8 data[0x20];
5595 u8 action_type[0x4];
5596 u8 field[0xc];
5597 u8 reserved_at_10[0x10];
5599 u8 data[0x20];
5603 u8 action_type[0x4];
5604 u8 src_field[0xc];
5605 u8 reserved_at_10[0x3];
5606 u8 src_offset[0x5];
5607 u8 reserved_at_18[0x3];
5608 u8 length[0x5];
5610 u8 reserved_at_20[0x4];
5611 u8 dst_field[0xc];
5612 u8 reserved_at_30[0x3];
5613 u8 dst_offset[0x5];
5614 u8 reserved_at_38[0x8];
5621 u8 reserved_at_0[0x40];
5625 MLX5_ACTION_TYPE_SET = 0x1,
5626 MLX5_ACTION_TYPE_ADD = 0x2,
5627 MLX5_ACTION_TYPE_COPY = 0x3,
5631 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
5632 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
5633 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
5634 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
5635 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
5636 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
5637 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
5638 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
5639 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
5640 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
5641 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
5642 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
5643 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
5644 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
5645 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
5646 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
5647 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
5648 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
5649 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
5650 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
5651 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
5652 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
5653 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17,
5654 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
5655 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49,
5656 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50,
5657 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51,
5658 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52,
5659 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53,
5660 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54,
5661 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55,
5662 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56,
5663 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57,
5664 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58,
5665 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59,
5666 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B,
5667 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D,
5668 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F,
5669 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70,
5673 u8 status[0x8];
5674 u8 reserved_at_8[0x18];
5676 u8 syndrome[0x20];
5678 u8 modify_header_id[0x20];
5680 u8 reserved_at_60[0x20];
5684 u8 opcode[0x10];
5685 u8 reserved_at_10[0x10];
5687 u8 reserved_at_20[0x10];
5688 u8 op_mod[0x10];
5690 u8 reserved_at_40[0x20];
5692 u8 table_type[0x8];
5693 u8 reserved_at_68[0x10];
5694 u8 num_of_actions[0x8];
5700 u8 status[0x8];
5701 u8 reserved_at_8[0x18];
5703 u8 syndrome[0x20];
5705 u8 reserved_at_40[0x40];
5709 u8 opcode[0x10];
5710 u8 reserved_at_10[0x10];
5712 u8 reserved_at_20[0x10];
5713 u8 op_mod[0x10];
5715 u8 modify_header_id[0x20];
5717 u8 reserved_at_60[0x20];
5721 u8 opcode[0x10];
5722 u8 uid[0x10];
5724 u8 reserved_at_20[0x10];
5725 u8 op_mod[0x10];
5727 u8 modify_header_id[0x20];
5729 u8 reserved_at_60[0xa0];
5733 u8 status[0x8];
5734 u8 reserved_0[0x18];
5736 u8 syndrome[0x20];
5738 u8 reserved_1[0x40];
5742 u8 reserved_2[0x180];
5746 u8 opcode[0x10];
5747 u8 reserved_0[0x10];
5749 u8 reserved_1[0x10];
5750 u8 op_mod[0x10];
5752 u8 reserved_2[0x8];
5753 u8 dctn[0x18];
5755 u8 reserved_3[0x20];
5759 u8 status[0x8];
5760 u8 reserved_0[0x18];
5762 u8 syndrome[0x20];
5764 u8 enable[0x1];
5765 u8 reserved_1[0x1f];
5767 u8 reserved_2[0x160];
5773 u8 opcode[0x10];
5774 u8 reserved_0[0x10];
5776 u8 reserved_1[0x10];
5777 u8 op_mod[0x10];
5779 u8 reserved_2[0x40];
5783 u8 reformat_type[0x8];
5784 u8 reserved_at_8[0x4];
5785 u8 reformat_param_0[0x4];
5786 u8 reserved_at_10[0x6];
5787 u8 reformat_data_size[0xa];
5789 u8 reformat_param_1[0x8];
5790 u8 reserved_at_28[0x8];
5791 u8 reformat_data[2][0x8];
5793 u8 more_reformat_data[][0x8];
5797 u8 status[0x8];
5798 u8 reserved_at_8[0x18];
5800 u8 syndrome[0x20];
5802 u8 reserved_at_40[0xa0];
5804 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[0];
5808 u8 opcode[0x10];
5809 u8 reserved_at_10[0x10];
5811 u8 reserved_at_20[0x10];
5812 u8 op_mod[0x10];
5814 u8 packet_reformat_id[0x20];
5816 u8 reserved_at_60[0xa0];
5820 u8 status[0x8];
5821 u8 reserved_at_8[0x18];
5823 u8 syndrome[0x20];
5825 u8 packet_reformat_id[0x20];
5827 u8 reserved_at_60[0x20];
5831 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0,
5832 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1,
5833 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
5834 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
5835 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
5836 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
5837 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV4 = 0x7,
5838 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
5839 MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT_OVER_UDP = 0xa,
5840 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
5841 MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_UDPV6 = 0xc,
5845 u8 opcode[0x10];
5846 u8 reserved_at_10[0x10];
5848 u8 reserved_at_20[0x10];
5849 u8 op_mod[0x10];
5851 u8 reserved_at_40[0xa0];
5857 u8 status[0x8];
5858 u8 reserved_at_8[0x18];
5860 u8 syndrome[0x20];
5862 u8 reserved_at_40[0x40];
5866 u8 opcode[0x10];
5867 u8 reserved_at_10[0x10];
5869 u8 reserved_20[0x10];
5870 u8 op_mod[0x10];
5872 u8 packet_reformat_id[0x20];
5874 u8 reserved_60[0x20];
5878 u8 counter_id[0x10];
5879 u8 sample_id[0x10];
5881 u8 time_stamp_31_0[0x20];
5883 u8 counter_value_h[0x20];
5885 u8 counter_value_l[0x20];
5889 MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_ENABLE = 0x1,
5890 MLX5_DIAGNOSTIC_PARAMS_CONTEXT_ENABLE_DISABLE = 0x0,
5894 u8 status[0x8];
5895 u8 reserved_0[0x18];
5897 u8 syndrome[0x20];
5899 u8 reserved_1[0x40];
5903 u8 reserved_2[0x600];
5905 u8 pas[0][0x40];
5909 u8 opcode[0x10];
5910 u8 reserved_0[0x10];
5912 u8 reserved_1[0x10];
5913 u8 op_mod[0x10];
5915 u8 reserved_2[0x8];
5916 u8 cqn[0x18];
5918 u8 reserved_3[0x20];
5922 u8 status[0x8];
5923 u8 reserved_0[0x18];
5925 u8 syndrome[0x20];
5927 u8 reserved_1[0x20];
5929 u8 enable[0x1];
5930 u8 tag_enable[0x1];
5931 u8 reserved_2[0x1e];
5935 u8 opcode[0x10];
5936 u8 reserved_0[0x10];
5938 u8 reserved_1[0x10];
5939 u8 op_mod[0x10];
5941 u8 reserved_2[0x18];
5942 u8 priority[0x4];
5943 u8 cong_protocol[0x4];
5945 u8 reserved_3[0x20];
5949 u8 status[0x8];
5950 u8 reserved_0[0x18];
5952 u8 syndrome[0x20];
5954 u8 reserved_1[0x40];
5956 u8 rp_cur_flows[0x20];
5958 u8 sum_flows[0x20];
5960 u8 rp_cnp_ignored_high[0x20];
5962 u8 rp_cnp_ignored_low[0x20];
5964 u8 rp_cnp_handled_high[0x20];
5966 u8 rp_cnp_handled_low[0x20];
5968 u8 reserved_2[0x100];
5970 u8 time_stamp_high[0x20];
5972 u8 time_stamp_low[0x20];
5974 u8 accumulators_period[0x20];
5976 u8 np_ecn_marked_roce_packets_high[0x20];
5978 u8 np_ecn_marked_roce_packets_low[0x20];
5980 u8 np_cnp_sent_high[0x20];
5982 u8 np_cnp_sent_low[0x20];
5984 u8 reserved_3[0x560];
5988 u8 opcode[0x10];
5989 u8 reserved_0[0x10];
5991 u8 reserved_1[0x10];
5992 u8 op_mod[0x10];
5994 u8 clear[0x1];
5995 u8 reserved_2[0x1f];
5997 u8 reserved_3[0x20];
6001 u8 status[0x8];
6002 u8 reserved_0[0x18];
6004 u8 syndrome[0x20];
6006 u8 reserved_1[0x40];
6012 u8 opcode[0x10];
6013 u8 reserved_0[0x10];
6015 u8 reserved_1[0x10];
6016 u8 op_mod[0x10];
6018 u8 reserved_2[0x1c];
6019 u8 cong_protocol[0x4];
6021 u8 reserved_3[0x20];
6025 u8 status[0x8];
6026 u8 reserved_0[0x18];
6028 u8 syndrome[0x20];
6030 u8 reserved_1[0x20];
6032 u8 reserved_2[0x9];
6033 u8 device_burst_size[0x17];
6037 u8 opcode[0x10];
6038 u8 reserved_0[0x10];
6040 u8 reserved_1[0x10];
6041 u8 op_mod[0x10];
6043 u8 reserved_2[0x40];
6047 u8 status[0x8];
6048 u8 reserved_0[0x18];
6050 u8 syndrome[0x20];
6052 u8 reserved_1[0x40];
6058 u8 opcode[0x10];
6059 u8 reserved_0[0x10];
6061 u8 reserved_1[0x10];
6062 u8 op_mod[0x10];
6064 u8 reserved_2[0x40];
6068 u8 status[0x8];
6069 u8 reserved_0[0x18];
6071 u8 syndrome[0x20];
6073 u8 reserved_1[0x40];
6077 u8 opcode[0x10];
6078 u8 uid[0x10];
6080 u8 reserved_1[0x10];
6081 u8 op_mod[0x10];
6083 u8 reserved_2[0x8];
6084 u8 qpn[0x18];
6086 u8 reserved_3[0x20];
6090 u8 status[0x8];
6091 u8 reserved_0[0x18];
6093 u8 syndrome[0x20];
6095 u8 reserved_1[0x40];
6099 u8 opcode[0x10];
6100 u8 uid[0x10];
6102 u8 reserved_1[0x10];
6103 u8 op_mod[0x10];
6105 u8 reserved_2[0x8];
6106 u8 qpn[0x18];
6108 u8 reserved_3[0x20];
6112 u8 reserved_at_0[0xc];
6113 u8 traffic_class[0x4];
6114 u8 qos_para_vport_number[0x10];
6118 u8 status[0x8];
6119 u8 reserved_0[0x18];
6121 u8 syndrome[0x20];
6123 u8 reserved_1[0x40];
6127 u8 opcode[0x10];
6128 u8 reserved_0[0x10];
6130 u8 reserved_1[0x10];
6131 u8 op_mod[0x10];
6133 u8 error[0x1];
6134 u8 reserved_2[0x4];
6135 u8 rdma[0x1];
6136 u8 read_write[0x1];
6137 u8 req_res[0x1];
6138 u8 qpn[0x18];
6140 u8 reserved_3[0x20];
6144 u8 status[0x8];
6145 u8 reserved_0[0x18];
6147 u8 syndrome[0x20];
6149 u8 reserved_1[0x40];
6153 u8 opcode[0x10];
6154 u8 reserved_0[0x10];
6156 u8 reserved_1[0x10];
6157 u8 op_mod[0x10];
6159 u8 reserved_2[0x40];
6163 u8 status[0x8];
6164 u8 reserved_0[0x18];
6166 u8 syndrome[0x20];
6168 u8 reserved_1[0x40];
6172 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_NIC_VPORT = 0x0,
6173 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
6174 MLX5_MODIFY_VPORT_STATE_IN_OP_MOD_UPLINK = 0x2,
6178 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_DOWN = 0x0,
6179 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_UP = 0x1,
6180 MLX5_MODIFY_VPORT_STATE_IN_ADMIN_STATE_FOLLOW = 0x2,
6184 u8 opcode[0x10];
6185 u8 reserved_0[0x10];
6187 u8 reserved_1[0x10];
6188 u8 op_mod[0x10];
6190 u8 other_vport[0x1];
6191 u8 reserved_2[0xf];
6192 u8 vport_number[0x10];
6194 u8 reserved_3[0x18];
6195 u8 admin_state[0x4];
6196 u8 reserved_4[0x4];
6200 u8 status[0x8];
6201 u8 reserved_0[0x18];
6203 u8 syndrome[0x20];
6205 u8 reserved_1[0x40];
6209 u8 reserved_at_0[0x20];
6211 u8 reserved_at_20[0x1d];
6212 u8 lag_tx_port_affinity[0x1];
6213 u8 strict_lag_tx_port_affinity[0x1];
6214 u8 prio[0x1];
6218 u8 opcode[0x10];
6219 u8 uid[0x10];
6221 u8 reserved_1[0x10];
6222 u8 op_mod[0x10];
6224 u8 reserved_2[0x8];
6225 u8 tisn[0x18];
6227 u8 reserved_3[0x20];
6231 u8 reserved_4[0x40];
6237 u8 status[0x8];
6238 u8 reserved_0[0x18];
6240 u8 syndrome[0x20];
6242 u8 reserved_1[0x40];
6247 MLX5_MODIFY_SQ_BITMASK_PACKET_PACING_RATE_LIMIT_INDEX = 0x1 << 0,
6248 MLX5_MODIFY_SQ_BITMASK_QOS_PARA_VPORT_NUMBER = 0x1 << 1
6252 u8 opcode[0x10];
6253 u8 uid[0x10];
6255 u8 reserved_1[0x10];
6256 u8 op_mod[0x10];
6258 u8 reserved_2[0x8];
6259 u8 tirn[0x18];
6261 u8 reserved_3[0x20];
6263 u8 modify_bitmask[0x40];
6265 u8 reserved_4[0x40];
6271 u8 status[0x8];
6272 u8 reserved_0[0x18];
6274 u8 syndrome[0x20];
6276 u8 reserved_1[0x40];
6280 u8 opcode[0x10];
6281 u8 uid[0x10];
6283 u8 reserved_1[0x10];
6284 u8 op_mod[0x10];
6286 u8 sq_state[0x4];
6287 u8 reserved_2[0x4];
6288 u8 sqn[0x18];
6290 u8 reserved_3[0x20];
6292 u8 modify_bitmask[0x40];
6294 u8 reserved_4[0x40];
6300 u8 status[0x8];
6301 u8 reserved_at_8[0x18];
6303 u8 syndrome[0x20];
6305 u8 reserved_at_40[0x1c0];
6309 MLX5_MODIFY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
6313 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_BW_SHARE = 0x1,
6314 MLX5_MODIFY_SCHEDULING_ELEMENT_BITMASK_MAX_AVERAGE_BW = 0x2,
6318 u8 opcode[0x10];
6319 u8 reserved_at_10[0x10];
6321 u8 reserved_at_20[0x10];
6322 u8 op_mod[0x10];
6324 u8 scheduling_hierarchy[0x8];
6325 u8 reserved_at_48[0x18];
6327 u8 scheduling_element_id[0x20];
6329 u8 reserved_at_80[0x20];
6331 u8 modify_bitmask[0x20];
6333 u8 reserved_at_c0[0x40];
6337 u8 reserved_at_300[0x100];
6341 u8 status[0x8];
6342 u8 reserved_0[0x18];
6344 u8 syndrome[0x20];
6346 u8 reserved_1[0x40];
6350 u8 reserved_at_0[0x20];
6352 u8 reserved_at_20[0x1f];
6353 u8 rqn_list[0x1];
6358 u8 opcode[0x10];
6359 u8 uid[0x10];
6361 u8 reserved_1[0x10];
6362 u8 op_mod[0x10];
6364 u8 reserved_2[0x8];
6365 u8 rqtn[0x18];
6367 u8 reserved_3[0x20];
6371 u8 reserved_4[0x40];
6377 u8 status[0x8];
6378 u8 reserved_0[0x18];
6380 u8 syndrome[0x20];
6382 u8 reserved_1[0x40];
6391 u8 opcode[0x10];
6392 u8 uid[0x10];
6394 u8 reserved_1[0x10];
6395 u8 op_mod[0x10];
6397 u8 rq_state[0x4];
6398 u8 reserved_2[0x4];
6399 u8 rqn[0x18];
6401 u8 reserved_3[0x20];
6403 u8 modify_bitmask[0x40];
6405 u8 reserved_4[0x40];
6411 u8 status[0x8];
6412 u8 reserved_0[0x18];
6414 u8 syndrome[0x20];
6416 u8 reserved_1[0x40];
6420 u8 reserved[0x20];
6422 u8 reserved1[0x1f];
6423 u8 lwm[0x1];
6427 u8 opcode[0x10];
6428 u8 uid[0x10];
6430 u8 reserved_1[0x10];
6431 u8 op_mod[0x10];
6433 u8 rmp_state[0x4];
6434 u8 reserved_2[0x4];
6435 u8 rmpn[0x18];
6437 u8 reserved_3[0x20];
6441 u8 reserved_4[0x40];
6447 u8 status[0x8];
6448 u8 reserved_0[0x18];
6450 u8 syndrome[0x20];
6452 u8 reserved_1[0x40];
6456 u8 reserved_0[0x14];
6457 u8 disable_uc_local_lb[0x1];
6458 u8 disable_mc_local_lb[0x1];
6459 u8 node_guid[0x1];
6460 u8 port_guid[0x1];
6461 u8 min_wqe_inline_mode[0x1];
6462 u8 mtu[0x1];
6463 u8 change_event[0x1];
6464 u8 promisc[0x1];
6465 u8 permanent_address[0x1];
6466 u8 addresses_list[0x1];
6467 u8 roce_en[0x1];
6468 u8 reserved_1[0x1];
6472 u8 opcode[0x10];
6473 u8 reserved_0[0x10];
6475 u8 reserved_1[0x10];
6476 u8 op_mod[0x10];
6478 u8 other_vport[0x1];
6479 u8 reserved_2[0xf];
6480 u8 vport_number[0x10];
6484 u8 reserved_3[0x780];
6490 u8 status[0x8];
6491 u8 reserved_0[0x18];
6493 u8 syndrome[0x20];
6495 u8 reserved_1[0x40];
6536 u8 opcode[0x10];
6537 u8 reserved_0[0x10];
6539 u8 reserved_1[0x10];
6540 u8 op_mod[0x10];
6542 u8 other_vport[0x1];
6543 u8 reserved_2[0xb];
6544 u8 port_num[0x4];
6545 u8 vport_number[0x10];
6547 u8 reserved_3[0x20];
6553 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
6558 u8 status[0x8];
6559 u8 reserved_at_8[0x18];
6561 u8 syndrome[0x20];
6563 u8 reserved_at_40[0x40];
6567 MLX5_MODIFY_FLOW_TABLE_SELECT_MISS_ACTION_AND_ID = 0x1,
6568 MLX5_MODIFY_FLOW_TABLE_SELECT_LAG_MASTER_NEXT_TABLE_ID = 0x8000,
6572 u8 opcode[0x10];
6573 u8 reserved_at_10[0x10];
6575 u8 reserved_at_20[0x10];
6576 u8 op_mod[0x10];
6578 u8 other_vport[0x1];
6579 u8 reserved_at_41[0xf];
6580 u8 vport_number[0x10];
6582 u8 reserved_at_60[0x10];
6583 u8 modify_field_select[0x10];
6585 u8 table_type[0x8];
6586 u8 reserved_at_88[0x18];
6588 u8 reserved_at_a0[0x8];
6589 u8 table_id[0x18];
6595 u8 status[0x8];
6596 u8 reserved_0[0x18];
6598 u8 syndrome[0x20];
6600 u8 reserved_1[0x40];
6604 u8 reserved[0x1c];
6605 u8 vport_cvlan_insert[0x1];
6606 u8 vport_svlan_insert[0x1];
6607 u8 vport_cvlan_strip[0x1];
6608 u8 vport_svlan_strip[0x1];
6612 u8 opcode[0x10];
6613 u8 reserved_0[0x10];
6615 u8 reserved_1[0x10];
6616 u8 op_mod[0x10];
6618 u8 other_vport[0x1];
6619 u8 reserved_2[0xf];
6620 u8 vport_number[0x10];
6628 u8 status[0x8];
6629 u8 reserved_0[0x18];
6631 u8 syndrome[0x20];
6633 u8 reserved_1[0x40];
6637 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
6638 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
6642 u8 opcode[0x10];
6643 u8 uid[0x10];
6645 u8 reserved_1[0x10];
6646 u8 op_mod[0x10];
6648 u8 reserved_2[0x8];
6649 u8 cqn[0x18];
6655 u8 reserved_at_280[0x60];
6657 u8 cq_umem_valid[0x1];
6658 u8 reserved_at_2e1[0x1f];
6660 u8 reserved_at_300[0x580];
6662 u8 pas[0][0x40];
6666 u8 status[0x8];
6667 u8 reserved_0[0x18];
6669 u8 syndrome[0x20];
6671 u8 reserved_1[0x40];
6675 u8 opcode[0x10];
6676 u8 reserved_0[0x10];
6678 u8 reserved_1[0x10];
6679 u8 op_mod[0x10];
6681 u8 reserved_2[0x18];
6682 u8 priority[0x4];
6683 u8 cong_protocol[0x4];
6685 u8 enable[0x1];
6686 u8 tag_enable[0x1];
6687 u8 reserved_3[0x1e];
6691 u8 status[0x8];
6692 u8 reserved_0[0x18];
6694 u8 syndrome[0x20];
6696 u8 reserved_1[0x40];
6700 u8 opcode[0x10];
6701 u8 reserved_0[0x10];
6703 u8 reserved_1[0x10];
6704 u8 op_mod[0x10];
6706 u8 reserved_2[0x1c];
6707 u8 cong_protocol[0x4];
6711 u8 reserved_3[0x80];
6717 u8 status[0x8];
6718 u8 reserved_0[0x18];
6720 u8 syndrome[0x20];
6722 u8 output_num_entries[0x20];
6724 u8 reserved_1[0x20];
6726 u8 pas[0][0x40];
6730 MLX5_PAGES_CANT_GIVE = 0x0,
6731 MLX5_PAGES_GIVE = 0x1,
6732 MLX5_PAGES_TAKE = 0x2,
6736 u8 opcode[0x10];
6737 u8 reserved_0[0x10];
6739 u8 reserved_1[0x10];
6740 u8 op_mod[0x10];
6742 u8 reserved_2[0x10];
6743 u8 function_id[0x10];
6745 u8 input_num_entries[0x20];
6747 u8 pas[0][0x40];
6751 u8 status[0x8];
6752 u8 reserved_0[0x18];
6754 u8 syndrome[0x20];
6756 u8 reserved_1[0x40];
6758 u8 response_mad_packet[256][0x8];
6762 u8 opcode[0x10];
6763 u8 reserved_0[0x10];
6765 u8 reserved_1[0x10];
6766 u8 op_mod[0x10];
6768 u8 remote_lid[0x10];
6769 u8 reserved_2[0x8];
6770 u8 port[0x8];
6772 u8 reserved_3[0x20];
6774 u8 mad[256][0x8];
6778 u8 status[0x8];
6779 u8 reserved_0[0x18];
6781 u8 syndrome[0x20];
6783 u8 reserved_1[0x40];
6787 MLX5_INIT_HCA_IN_OP_MOD_INIT = 0x0,
6788 MLX5_INIT_HCA_IN_OP_MOD_PRE_INIT = 0x1,
6792 u8 opcode[0x10];
6793 u8 reserved_0[0x10];
6795 u8 reserved_1[0x10];
6796 u8 op_mod[0x10];
6798 u8 reserved_2[0x40];
6802 u8 status[0x8];
6803 u8 reserved_0[0x18];
6805 u8 syndrome[0x20];
6807 u8 reserved_1[0x40];
6811 u8 opcode[0x10];
6812 u8 uid[0x10];
6814 u8 reserved_1[0x10];
6815 u8 op_mod[0x10];
6817 u8 reserved_2[0x8];
6818 u8 qpn[0x18];
6820 u8 reserved_3[0x20];
6822 u8 opt_param_mask[0x20];
6824 u8 reserved_4[0x20];
6828 u8 reserved_5[0x80];
6832 u8 status[0x8];
6833 u8 reserved_0[0x18];
6835 u8 syndrome[0x20];
6837 u8 reserved_1[0x40];
6841 u8 opcode[0x10];
6842 u8 uid[0x10];
6844 u8 reserved_1[0x10];
6845 u8 op_mod[0x10];
6847 u8 reserved_2[0x8];
6848 u8 qpn[0x18];
6850 u8 reserved_3[0x20];
6852 u8 opt_param_mask[0x20];
6854 u8 reserved_4[0x20];
6858 u8 reserved_5[0x80];
6862 u8 status[0x8];
6863 u8 reserved_0[0x18];
6865 u8 syndrome[0x20];
6867 u8 reserved_1[0x40];
6869 u8 packet_headers_log[128][0x8];
6871 u8 packet_syndrome[64][0x8];
6875 u8 opcode[0x10];
6876 u8 reserved_0[0x10];
6878 u8 reserved_1[0x10];
6879 u8 op_mod[0x10];
6881 u8 reserved_2[0x40];
6885 u8 modify_field_select[0x40];
6887 u8 reserved_at_40[0x14];
6888 u8 key_size[0x4];
6889 u8 reserved_at_58[0x4];
6890 u8 key_type[0x4];
6892 u8 reserved_at_60[0x8];
6893 u8 pd[0x18];
6895 u8 reserved_at_80[0x180];
6897 u8 key[8][0x20];
6899 u8 reserved_at_300[0x500];
6903 u8 opcode[0x10];
6904 u8 reserved_0[0x10];
6906 u8 reserved_1[0x10];
6907 u8 op_mod[0x10];
6909 u8 reserved_2[0x18];
6910 u8 eq_number[0x8];
6912 u8 reserved_3[0x20];
6914 u8 eqe[64][0x8];
6918 u8 status[0x8];
6919 u8 reserved_0[0x18];
6921 u8 syndrome[0x20];
6923 u8 reserved_1[0x40];
6927 u8 status[0x8];
6928 u8 reserved_0[0x18];
6930 u8 syndrome[0x20];
6932 u8 reserved_1[0x20];
6936 u8 opcode[0x10];
6937 u8 reserved_0[0x10];
6939 u8 reserved_1[0x10];
6940 u8 op_mod[0x10];
6942 u8 reserved_2[0x10];
6943 u8 function_id[0x10];
6945 u8 reserved_3[0x20];
6949 u8 status[0x8];
6950 u8 reserved_0[0x18];
6952 u8 syndrome[0x20];
6954 u8 reserved_1[0x40];
6958 u8 opcode[0x10];
6959 u8 uid[0x10];
6961 u8 reserved_1[0x10];
6962 u8 op_mod[0x10];
6964 u8 reserved_2[0x8];
6965 u8 dctn[0x18];
6967 u8 reserved_3[0x20];
6971 u8 status[0x8];
6972 u8 reserved_0[0x18];
6974 u8 syndrome[0x20];
6976 u8 reserved_1[0x20];
6980 u8 opcode[0x10];
6981 u8 reserved_0[0x10];
6983 u8 reserved_1[0x10];
6984 u8 op_mod[0x10];
6986 u8 reserved_2[0x10];
6987 u8 function_id[0x10];
6989 u8 reserved_3[0x20];
6993 u8 status[0x8];
6994 u8 reserved_0[0x18];
6996 u8 syndrome[0x20];
6998 u8 reserved_1[0x40];
7002 u8 opcode[0x10];
7003 u8 uid[0x10];
7005 u8 reserved_1[0x10];
7006 u8 op_mod[0x10];
7008 u8 reserved_2[0x8];
7009 u8 qpn[0x18];
7011 u8 reserved_3[0x20];
7013 u8 multicast_gid[16][0x8];
7017 u8 status[0x8];
7018 u8 reserved_0[0x18];
7020 u8 syndrome[0x20];
7022 u8 reserved_1[0x40];
7026 u8 opcode[0x10];
7027 u8 uid[0x10];
7029 u8 reserved_1[0x10];
7030 u8 op_mod[0x10];
7032 u8 reserved_2[0x8];
7033 u8 xrc_srqn[0x18];
7035 u8 reserved_3[0x20];
7039 u8 status[0x8];
7040 u8 reserved_0[0x18];
7042 u8 syndrome[0x20];
7044 u8 reserved_1[0x40];
7048 u8 opcode[0x10];
7049 u8 uid[0x10];
7051 u8 reserved_1[0x10];
7052 u8 op_mod[0x10];
7054 u8 reserved_2[0x8];
7055 u8 tisn[0x18];
7057 u8 reserved_3[0x20];
7061 u8 status[0x8];
7062 u8 reserved_0[0x18];
7064 u8 syndrome[0x20];
7066 u8 reserved_1[0x40];
7070 u8 opcode[0x10];
7071 u8 uid[0x10];
7073 u8 reserved_1[0x10];
7074 u8 op_mod[0x10];
7076 u8 reserved_2[0x8];
7077 u8 tirn[0x18];
7079 u8 reserved_3[0x20];
7083 u8 status[0x8];
7084 u8 reserved_0[0x18];
7086 u8 syndrome[0x20];
7088 u8 reserved_1[0x40];
7092 u8 opcode[0x10];
7093 u8 uid[0x10];
7095 u8 reserved_1[0x10];
7096 u8 op_mod[0x10];
7098 u8 reserved_2[0x8];
7099 u8 srqn[0x18];
7101 u8 reserved_3[0x20];
7105 u8 status[0x8];
7106 u8 reserved_0[0x18];
7108 u8 syndrome[0x20];
7110 u8 reserved_1[0x40];
7114 u8 opcode[0x10];
7115 u8 uid[0x10];
7117 u8 reserved_1[0x10];
7118 u8 op_mod[0x10];
7120 u8 reserved_2[0x8];
7121 u8 sqn[0x18];
7123 u8 reserved_3[0x20];
7127 u8 status[0x8];
7128 u8 reserved_at_8[0x18];
7130 u8 syndrome[0x20];
7132 u8 reserved_at_40[0x1c0];
7136 MLX5_DESTROY_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
7140 u8 opcode[0x10];
7141 u8 reserved_at_10[0x10];
7143 u8 reserved_at_20[0x10];
7144 u8 op_mod[0x10];
7146 u8 scheduling_hierarchy[0x8];
7147 u8 reserved_at_48[0x18];
7149 u8 scheduling_element_id[0x20];
7151 u8 reserved_at_80[0x180];
7155 u8 status[0x8];
7156 u8 reserved_0[0x18];
7158 u8 syndrome[0x20];
7160 u8 reserved_1[0x40];
7164 u8 opcode[0x10];
7165 u8 uid[0x10];
7167 u8 reserved_1[0x10];
7168 u8 op_mod[0x10];
7170 u8 reserved_2[0x8];
7171 u8 rqtn[0x18];
7173 u8 reserved_3[0x20];
7177 u8 status[0x8];
7178 u8 reserved_0[0x18];
7180 u8 syndrome[0x20];
7182 u8 reserved_1[0x40];
7186 u8 opcode[0x10];
7187 u8 uid[0x10];
7189 u8 reserved_1[0x10];
7190 u8 op_mod[0x10];
7192 u8 reserved_2[0x8];
7193 u8 rqn[0x18];
7195 u8 reserved_3[0x20];
7199 u8 status[0x8];
7200 u8 reserved_0[0x18];
7202 u8 syndrome[0x20];
7204 u8 reserved_1[0x40];
7208 u8 opcode[0x10];
7209 u8 reserved_0[0x10];
7211 u8 reserved_1[0x10];
7212 u8 op_mod[0x10];
7214 u8 reserved_2[0x8];
7215 u8 rmpn[0x18];
7217 u8 reserved_3[0x20];
7221 u8 status[0x8];
7222 u8 reserved_0[0x18];
7224 u8 syndrome[0x20];
7226 u8 reserved_1[0x40];
7230 u8 opcode[0x10];
7231 u8 uid[0x10];
7233 u8 reserved_1[0x10];
7234 u8 op_mod[0x10];
7236 u8 reserved_2[0x8];
7237 u8 qpn[0x18];
7239 u8 reserved_3[0x20];
7243 u8 status[0x8];
7244 u8 reserved_at_8[0x18];
7246 u8 syndrome[0x20];
7248 u8 reserved_at_40[0x1c0];
7252 u8 opcode[0x10];
7253 u8 reserved_at_10[0x10];
7255 u8 reserved_at_20[0x10];
7256 u8 op_mod[0x10];
7258 u8 reserved_at_40[0x20];
7260 u8 reserved_at_60[0x10];
7261 u8 qos_para_vport_number[0x10];
7263 u8 reserved_at_80[0x180];
7267 u8 status[0x8];
7268 u8 reserved_0[0x18];
7270 u8 syndrome[0x20];
7272 u8 reserved_1[0x40];
7276 u8 opcode[0x10];
7277 u8 reserved_0[0x10];
7279 u8 reserved_1[0x10];
7280 u8 op_mod[0x10];
7282 u8 reserved_2[0x8];
7283 u8 psvn[0x18];
7285 u8 reserved_3[0x20];
7289 u8 status[0x8];
7290 u8 reserved_0[0x18];
7292 u8 syndrome[0x20];
7294 u8 reserved_1[0x40];
7298 u8 opcode[0x10];
7299 u8 reserved_0[0x10];
7301 u8 reserved_1[0x10];
7302 u8 op_mod[0x10];
7304 u8 reserved_2[0x8];
7305 u8 mkey_index[0x18];
7307 u8 reserved_3[0x20];
7311 u8 status[0x8];
7312 u8 reserved_0[0x18];
7314 u8 syndrome[0x20];
7316 u8 reserved_1[0x40];
7320 u8 opcode[0x10];
7321 u8 reserved_0[0x10];
7323 u8 reserved_1[0x10];
7324 u8 op_mod[0x10];
7326 u8 other_vport[0x1];
7327 u8 reserved_2[0xf];
7328 u8 vport_number[0x10];
7330 u8 reserved_3[0x20];
7332 u8 table_type[0x8];
7333 u8 reserved_4[0x18];
7335 u8 reserved_5[0x8];
7336 u8 table_id[0x18];
7338 u8 reserved_6[0x140];
7342 u8 status[0x8];
7343 u8 reserved_0[0x18];
7345 u8 syndrome[0x20];
7347 u8 reserved_1[0x40];
7351 u8 opcode[0x10];
7352 u8 reserved_0[0x10];
7354 u8 reserved_1[0x10];
7355 u8 op_mod[0x10];
7357 u8 other_vport[0x1];
7358 u8 reserved_2[0xf];
7359 u8 vport_number[0x10];
7361 u8 reserved_3[0x20];
7363 u8 table_type[0x8];
7364 u8 reserved_4[0x18];
7366 u8 reserved_5[0x8];
7367 u8 table_id[0x18];
7369 u8 group_id[0x20];
7371 u8 reserved_6[0x120];
7375 u8 status[0x8];
7376 u8 reserved_at_8[0x18];
7378 u8 syndrome[0x20];
7380 u8 reserved_at_40[0x40];
7384 u8 opcode[0x10];
7385 u8 reserved_at_10[0x10];
7387 u8 reserved_at_20[0x10];
7388 u8 obj_type[0x10];
7390 u8 obj_id[0x20];
7392 u8 reserved_at_60[0x20];
7396 u8 status[0x8];
7397 u8 reserved_0[0x18];
7399 u8 syndrome[0x20];
7401 u8 reserved_1[0x40];
7405 u8 opcode[0x10];
7406 u8 reserved_0[0x10];
7408 u8 reserved_1[0x10];
7409 u8 op_mod[0x10];
7411 u8 reserved_2[0x18];
7412 u8 eq_number[0x8];
7414 u8 reserved_3[0x20];
7418 u8 status[0x8];
7419 u8 reserved_0[0x18];
7421 u8 syndrome[0x20];
7423 u8 reserved_1[0x40];
7427 u8 opcode[0x10];
7428 u8 uid[0x10];
7430 u8 reserved_1[0x10];
7431 u8 op_mod[0x10];
7433 u8 reserved_2[0x8];
7434 u8 dctn[0x18];
7436 u8 reserved_3[0x20];
7440 u8 status[0x8];
7441 u8 reserved_0[0x18];
7443 u8 syndrome[0x20];
7445 u8 reserved_1[0x40];
7449 u8 opcode[0x10];
7450 u8 uid[0x10];
7452 u8 reserved_1[0x10];
7453 u8 op_mod[0x10];
7455 u8 reserved_2[0x8];
7456 u8 cqn[0x18];
7458 u8 reserved_3[0x20];
7462 u8 status[0x8];
7463 u8 reserved_0[0x18];
7465 u8 syndrome[0x20];
7467 u8 reserved_1[0x40];
7471 u8 opcode[0x10];
7472 u8 reserved_0[0x10];
7474 u8 reserved_1[0x10];
7475 u8 op_mod[0x10];
7477 u8 reserved_2[0x20];
7479 u8 reserved_3[0x10];
7480 u8 vxlan_udp_port[0x10];
7484 u8 status[0x8];
7485 u8 reserved_0[0x18];
7487 u8 syndrome[0x20];
7489 u8 reserved_1[0x40];
7493 u8 opcode[0x10];
7494 u8 reserved_0[0x10];
7496 u8 reserved_1[0x10];
7497 u8 op_mod[0x10];
7499 u8 reserved_2[0x60];
7501 u8 reserved_3[0x8];
7502 u8 table_index[0x18];
7504 u8 reserved_4[0x140];
7508 u8 status[0x8];
7509 u8 reserved_0[0x18];
7511 u8 syndrome[0x20];
7513 u8 reserved_1[0x40];
7517 u8 opcode[0x10];
7518 u8 reserved_0[0x10];
7520 u8 reserved_1[0x10];
7521 u8 op_mod[0x10];
7523 u8 other_vport[0x1];
7524 u8 reserved_2[0xf];
7525 u8 vport_number[0x10];
7527 u8 reserved_3[0x20];
7529 u8 table_type[0x8];
7530 u8 reserved_4[0x18];
7532 u8 reserved_5[0x8];
7533 u8 table_id[0x18];
7535 u8 reserved_6[0x40];
7537 u8 flow_index[0x20];
7539 u8 reserved_7[0xe0];
7543 u8 status[0x8];
7544 u8 reserved_0[0x18];
7546 u8 syndrome[0x20];
7548 u8 reserved_1[0x40];
7552 u8 opcode[0x10];
7553 u8 uid[0x10];
7555 u8 reserved_1[0x10];
7556 u8 op_mod[0x10];
7558 u8 reserved_2[0x8];
7559 u8 xrcd[0x18];
7561 u8 reserved_3[0x20];
7565 u8 status[0x8];
7566 u8 reserved_0[0x18];
7568 u8 syndrome[0x20];
7570 u8 reserved_1[0x40];
7574 u8 opcode[0x10];
7575 u8 reserved_0[0x10];
7577 u8 reserved_1[0x10];
7578 u8 op_mod[0x10];
7580 u8 reserved_2[0x8];
7581 u8 uar[0x18];
7583 u8 reserved_3[0x20];
7587 u8 status[0x8];
7588 u8 reserved_0[0x18];
7590 u8 syndrome[0x20];
7592 u8 reserved_1[0x40];
7596 u8 opcode[0x10];
7597 u8 uid[0x10];
7599 u8 reserved_1[0x10];
7600 u8 op_mod[0x10];
7602 u8 reserved_2[0x8];
7603 u8 transport_domain[0x18];
7605 u8 reserved_3[0x20];
7609 u8 status[0x8];
7610 u8 reserved_0[0x18];
7612 u8 syndrome[0x20];
7614 u8 reserved_1[0x40];
7618 u8 reserved[0x10];
7619 u8 counter_id[0x10];
7623 u8 num_of_counters[0x10];
7624 u8 reserved_2[0x8];
7625 u8 log_num_of_samples[0x8];
7627 u8 single[0x1];
7628 u8 repetitive[0x1];
7629 u8 sync[0x1];
7630 u8 clear[0x1];
7631 u8 on_demand[0x1];
7632 u8 enable[0x1];
7633 u8 reserved_3[0x12];
7634 u8 log_sample_period[0x8];
7636 u8 reserved_4[0x80];
7638 struct mlx5_ifc_counter_id_bits counter_id[0];
7642 u8 opcode[0x10];
7643 u8 reserved_at_10[0x10];
7645 u8 reserved_at_20[0x10];
7646 u8 op_mod[0x10];
7648 u8 reserved_at_40[0x40];
7652 u8 status[0x8];
7653 u8 reserved_at_8[0x18];
7655 u8 syndrome[0x20];
7661 u8 opcode[0x10];
7662 u8 reserved_0[0x10];
7664 u8 reserved_1[0x10];
7665 u8 op_mod[0x10];
7671 u8 status[0x8];
7672 u8 reserved_0[0x18];
7674 u8 syndrome[0x20];
7676 u8 reserved_1[0x40];
7680 u8 opcode[0x10];
7681 u8 reserved_0[0x10];
7683 u8 reserved_1[0x10];
7684 u8 op_mod[0x10];
7686 u8 num_of_samples[0x10];
7687 u8 sample_index[0x10];
7689 u8 reserved_2[0x20];
7693 u8 counter_id[0x10];
7694 u8 sample_id[0x10];
7696 u8 time_stamp_31_0[0x20];
7698 u8 counter_value_h[0x20];
7700 u8 counter_value_l[0x20];
7704 u8 status[0x8];
7705 u8 reserved_0[0x18];
7707 u8 syndrome[0x20];
7709 u8 reserved_1[0x40];
7711 struct mlx5_ifc_diagnostic_counter_bits diag_counter[0];
7715 u8 opcode[0x10];
7716 u8 reserved_0[0x10];
7718 u8 reserved_1[0x10];
7719 u8 op_mod[0x10];
7721 u8 reserved_2[0x18];
7722 u8 counter_set_id[0x8];
7724 u8 reserved_3[0x20];
7728 u8 status[0x8];
7729 u8 reserved_0[0x18];
7731 u8 syndrome[0x20];
7733 u8 reserved_1[0x40];
7737 u8 opcode[0x10];
7738 u8 uid[0x10];
7740 u8 reserved_1[0x10];
7741 u8 op_mod[0x10];
7743 u8 reserved_2[0x8];
7744 u8 pd[0x18];
7746 u8 reserved_3[0x20];
7750 u8 status[0x8];
7751 u8 reserved_0[0x18];
7753 u8 syndrome[0x20];
7755 u8 reserved_1[0x40];
7759 u8 opcode[0x10];
7760 u8 reserved_0[0x10];
7762 u8 reserved_1[0x10];
7763 u8 op_mod[0x10];
7765 u8 flow_counter_id[0x20];
7767 u8 reserved_3[0x20];
7771 u8 status[0x8];
7772 u8 reserved_at_8[0x18];
7774 u8 syndrome[0x20];
7776 u8 reserved_at_40[0x8];
7777 u8 xrqn[0x18];
7779 u8 reserved_at_60[0x20];
7783 u8 opcode[0x10];
7784 u8 uid[0x10];
7786 u8 reserved_at_20[0x10];
7787 u8 op_mod[0x10];
7789 u8 reserved_at_40[0x40];
7795 u8 status[0x8];
7796 u8 reserved_0[0x18];
7798 u8 syndrome[0x20];
7800 u8 reserved_1[0x40];
7804 u8 opcode[0x10];
7805 u8 reserved_0[0x10];
7807 u8 reserved_1[0x10];
7808 u8 op_mod[0x10];
7810 u8 mkey[0x20];
7812 u8 reserved_2[0x20];
7816 u8 status[0x8];
7817 u8 reserved_0[0x18];
7819 u8 syndrome[0x20];
7821 u8 reserved_1[0x8];
7822 u8 xrc_srqn[0x18];
7824 u8 reserved_2[0x20];
7828 u8 opcode[0x10];
7829 u8 uid[0x10];
7831 u8 reserved_1[0x10];
7832 u8 op_mod[0x10];
7834 u8 reserved_2[0x40];
7838 u8 reserved_at_280[0x60];
7840 u8 xrc_srq_umem_valid[0x1];
7841 u8 reserved_at_2e1[0x1f];
7843 u8 reserved_at_300[0x580];
7845 u8 pas[0][0x40];
7849 u8 status[0x8];
7850 u8 reserved_0[0x18];
7852 u8 syndrome[0x20];
7854 u8 reserved_1[0x8];
7855 u8 tisn[0x18];
7857 u8 reserved_2[0x20];
7861 u8 opcode[0x10];
7862 u8 uid[0x10];
7864 u8 reserved_1[0x10];
7865 u8 op_mod[0x10];
7867 u8 reserved_2[0xc0];
7873 u8 status[0x8];
7874 u8 reserved_0[0x18];
7876 u8 syndrome[0x20];
7878 u8 reserved_1[0x8];
7879 u8 tirn[0x18];
7881 u8 reserved_2[0x20];
7885 u8 opcode[0x10];
7886 u8 uid[0x10];
7888 u8 reserved_1[0x10];
7889 u8 op_mod[0x10];
7891 u8 reserved_2[0xc0];
7897 u8 status[0x8];
7898 u8 reserved_0[0x18];
7900 u8 syndrome[0x20];
7902 u8 reserved_1[0x8];
7903 u8 srqn[0x18];
7905 u8 reserved_2[0x20];
7909 u8 opcode[0x10];
7910 u8 uid[0x10];
7912 u8 reserved_1[0x10];
7913 u8 op_mod[0x10];
7915 u8 reserved_2[0x40];
7919 u8 reserved_3[0x600];
7921 u8 pas[0][0x40];
7925 u8 status[0x8];
7926 u8 reserved_0[0x18];
7928 u8 syndrome[0x20];
7930 u8 reserved_1[0x8];
7931 u8 sqn[0x18];
7933 u8 reserved_2[0x20];
7937 u8 opcode[0x10];
7938 u8 uid[0x10];
7940 u8 reserved_1[0x10];
7941 u8 op_mod[0x10];
7943 u8 reserved_2[0xc0];
7949 u8 status[0x8];
7950 u8 reserved_at_8[0x18];
7952 u8 syndrome[0x20];
7954 u8 reserved_at_40[0x40];
7956 u8 scheduling_element_id[0x20];
7958 u8 reserved_at_a0[0x160];
7962 MLX5_CREATE_SCHEDULING_ELEMENT_IN_SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
7966 u8 opcode[0x10];
7967 u8 reserved_at_10[0x10];
7969 u8 reserved_at_20[0x10];
7970 u8 op_mod[0x10];
7972 u8 scheduling_hierarchy[0x8];
7973 u8 reserved_at_48[0x18];
7975 u8 reserved_at_60[0xa0];
7979 u8 reserved_at_300[0x100];
7983 u8 status[0x8];
7984 u8 reserved_0[0x18];
7986 u8 syndrome[0x20];
7988 u8 reserved_1[0x8];
7989 u8 rqtn[0x18];
7991 u8 reserved_2[0x20];
7995 u8 opcode[0x10];
7996 u8 uid[0x10];
7998 u8 reserved_1[0x10];
7999 u8 op_mod[0x10];
8001 u8 reserved_2[0xc0];
8007 u8 status[0x8];
8008 u8 reserved_0[0x18];
8010 u8 syndrome[0x20];
8012 u8 reserved_1[0x8];
8013 u8 rqn[0x18];
8015 u8 reserved_2[0x20];
8019 u8 opcode[0x10];
8020 u8 uid[0x10];
8022 u8 reserved_1[0x10];
8023 u8 op_mod[0x10];
8025 u8 reserved_2[0xc0];
8031 u8 status[0x8];
8032 u8 reserved_0[0x18];
8034 u8 syndrome[0x20];
8036 u8 reserved_1[0x8];
8037 u8 rmpn[0x18];
8039 u8 reserved_2[0x20];
8043 u8 opcode[0x10];
8044 u8 uid[0x10];
8046 u8 reserved_1[0x10];
8047 u8 op_mod[0x10];
8049 u8 reserved_2[0xc0];
8055 u8 status[0x8];
8056 u8 reserved_0[0x18];
8058 u8 syndrome[0x20];
8060 u8 reserved_1[0x8];
8061 u8 qpn[0x18];
8063 u8 reserved_2[0x20];
8067 u8 opcode[0x10];
8068 u8 uid[0x10];
8070 u8 reserved_1[0x10];
8071 u8 op_mod[0x10];
8073 u8 reserved_2[0x8];
8074 u8 input_qpn[0x18];
8076 u8 reserved_3[0x20];
8078 u8 opt_param_mask[0x20];
8080 u8 reserved_4[0x20];
8084 u8 reserved_at_800[0x60];
8086 u8 wq_umem_valid[0x1];
8087 u8 reserved_at_861[0x1f];
8089 u8 pas[0][0x40];
8093 u8 status[0x8];
8094 u8 reserved_at_8[0x18];
8096 u8 syndrome[0x20];
8098 u8 reserved_at_40[0x20];
8100 u8 reserved_at_60[0x10];
8101 u8 qos_para_vport_number[0x10];
8103 u8 reserved_at_80[0x180];
8107 u8 opcode[0x10];
8108 u8 reserved_at_10[0x10];
8110 u8 reserved_at_20[0x10];
8111 u8 op_mod[0x10];
8113 u8 reserved_at_40[0x1c0];
8117 u8 status[0x8];
8118 u8 reserved_0[0x18];
8120 u8 syndrome[0x20];
8122 u8 reserved_1[0x40];
8124 u8 reserved_2[0x8];
8125 u8 psv0_index[0x18];
8127 u8 reserved_3[0x8];
8128 u8 psv1_index[0x18];
8130 u8 reserved_4[0x8];
8131 u8 psv2_index[0x18];
8133 u8 reserved_5[0x8];
8134 u8 psv3_index[0x18];
8138 u8 opcode[0x10];
8139 u8 reserved_0[0x10];
8141 u8 reserved_1[0x10];
8142 u8 op_mod[0x10];
8144 u8 num_psv[0x4];
8145 u8 reserved_2[0x4];
8146 u8 pd[0x18];
8148 u8 reserved_3[0x20];
8152 u8 status[0x8];
8153 u8 reserved_0[0x18];
8155 u8 syndrome[0x20];
8157 u8 reserved_1[0x8];
8158 u8 mkey_index[0x18];
8160 u8 reserved_2[0x20];
8164 u8 opcode[0x10];
8165 u8 reserved_0[0x10];
8167 u8 reserved_1[0x10];
8168 u8 op_mod[0x10];
8170 u8 reserved_2[0x20];
8172 u8 pg_access[0x1];
8173 u8 mkey_umem_valid[0x1];
8174 u8 reserved_at_62[0x1e];
8178 u8 reserved_4[0x80];
8180 u8 translations_octword_actual_size[0x20];
8182 u8 reserved_5[0x560];
8184 u8 klm_pas_mtt[0][0x20];
8188 u8 status[0x8];
8189 u8 reserved_0[0x18];
8191 u8 syndrome[0x20];
8193 u8 reserved_1[0x8];
8194 u8 table_id[0x18];
8196 u8 reserved_2[0x20];
8200 u8 opcode[0x10];
8201 u8 uid[0x10];
8203 u8 reserved_at_20[0x10];
8204 u8 op_mod[0x10];
8206 u8 other_vport[0x1];
8207 u8 reserved_at_41[0xf];
8208 u8 vport_number[0x10];
8210 u8 reserved_at_60[0x20];
8212 u8 table_type[0x8];
8213 u8 reserved_at_88[0x18];
8215 u8 reserved_at_a0[0x20];
8221 u8 status[0x8];
8222 u8 reserved_0[0x18];
8224 u8 syndrome[0x20];
8226 u8 reserved_1[0x8];
8227 u8 group_id[0x18];
8229 u8 reserved_2[0x20];
8233 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
8234 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
8235 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
8236 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3,
8240 u8 opcode[0x10];
8241 u8 reserved_at_10[0x10];
8243 u8 reserved_at_20[0x10];
8244 u8 op_mod[0x10];
8246 u8 other_vport[0x1];
8247 u8 reserved_at_41[0xf];
8248 u8 vport_number[0x10];
8250 u8 reserved_at_60[0x20];
8252 u8 table_type[0x8];
8253 u8 reserved_at_88[0x4];
8254 u8 group_type[0x4];
8255 u8 reserved_at_90[0x10];
8257 u8 reserved_at_a0[0x8];
8258 u8 table_id[0x18];
8260 u8 source_eswitch_owner_vhca_id_valid[0x1];
8262 u8 reserved_at_c1[0x1f];
8264 u8 start_flow_index[0x20];
8266 u8 reserved_at_100[0x20];
8268 u8 end_flow_index[0x20];
8270 u8 reserved_at_140[0x10];
8271 u8 match_definer_id[0x10];
8273 u8 reserved_at_160[0x80];
8275 u8 reserved_at_1e0[0x18];
8276 u8 match_criteria_enable[0x8];
8280 u8 reserved_at_1200[0xe00];
8284 u8 status[0x8];
8285 u8 reserved_at_8[0x18];
8287 u8 syndrome[0x20];
8289 u8 obj_id[0x20];
8291 u8 reserved_at_60[0x20];
8295 u8 opcode[0x10];
8296 u8 reserved_at_10[0x10];
8298 u8 reserved_at_20[0x10];
8299 u8 obj_type[0x10];
8301 u8 reserved_at_40[0x40];
8307 u8 status[0x8];
8308 u8 reserved_0[0x18];
8310 u8 syndrome[0x20];
8312 u8 reserved_1[0x18];
8313 u8 eq_number[0x8];
8315 u8 reserved_2[0x20];
8319 u8 opcode[0x10];
8320 u8 reserved_0[0x10];
8322 u8 reserved_1[0x10];
8323 u8 op_mod[0x10];
8325 u8 reserved_2[0x40];
8329 u8 reserved_3[0x40];
8331 u8 event_bitmask[0x40];
8333 u8 reserved_4[0x580];
8335 u8 pas[0][0x40];
8339 u8 status[0x8];
8340 u8 reserved_0[0x18];
8342 u8 syndrome[0x20];
8344 u8 reserved_1[0x8];
8345 u8 dctn[0x18];
8347 u8 reserved_2[0x20];
8351 u8 opcode[0x10];
8352 u8 uid[0x10];
8354 u8 reserved_1[0x10];
8355 u8 op_mod[0x10];
8357 u8 reserved_2[0x40];
8361 u8 reserved_3[0x180];
8365 u8 status[0x8];
8366 u8 reserved_0[0x18];
8368 u8 syndrome[0x20];
8370 u8 reserved_1[0x8];
8371 u8 cqn[0x18];
8373 u8 reserved_2[0x20];
8377 u8 opcode[0x10];
8378 u8 uid[0x10];
8380 u8 reserved_1[0x10];
8381 u8 op_mod[0x10];
8383 u8 reserved_2[0x40];
8387 u8 reserved_at_280[0x60];
8389 u8 cq_umem_valid[0x1];
8390 u8 reserved_at_2e1[0x59f];
8392 u8 pas[0][0x40];
8396 u8 status[0x8];
8397 u8 reserved_0[0x18];
8399 u8 syndrome[0x20];
8401 u8 reserved_1[0x4];
8402 u8 min_delay[0xc];
8403 u8 int_vector[0x10];
8405 u8 reserved_2[0x20];
8409 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
8410 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
8414 u8 opcode[0x10];
8415 u8 reserved_0[0x10];
8417 u8 reserved_1[0x10];
8418 u8 op_mod[0x10];
8420 u8 reserved_2[0x4];
8421 u8 min_delay[0xc];
8422 u8 int_vector[0x10];
8424 u8 reserved_3[0x20];
8428 u8 status[0x8];
8429 u8 reserved_0[0x18];
8431 u8 syndrome[0x20];
8433 u8 reserved_1[0x40];
8437 u8 opcode[0x10];
8438 u8 uid[0x10];
8440 u8 reserved_1[0x10];
8441 u8 op_mod[0x10];
8443 u8 reserved_2[0x8];
8444 u8 qpn[0x18];
8446 u8 reserved_3[0x20];
8448 u8 multicast_gid[16][0x8];
8452 u8 status[0x8];
8453 u8 reserved_at_8[0x18];
8455 u8 syndrome[0x20];
8457 u8 reserved_at_40[0x40];
8461 u8 opcode[0x10];
8462 u8 reserved_at_10[0x10];
8464 u8 reserved_at_20[0x10];
8465 u8 op_mod[0x10];
8467 u8 reserved_at_40[0x8];
8468 u8 xrqn[0x18];
8470 u8 reserved_at_60[0x10];
8471 u8 lwm[0x10];
8475 u8 status[0x8];
8476 u8 reserved_0[0x18];
8478 u8 syndrome[0x20];
8480 u8 reserved_1[0x40];
8484 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
8488 u8 opcode[0x10];
8489 u8 uid[0x10];
8491 u8 reserved_1[0x10];
8492 u8 op_mod[0x10];
8494 u8 reserved_2[0x8];
8495 u8 xrc_srqn[0x18];
8497 u8 reserved_3[0x10];
8498 u8 lwm[0x10];
8502 u8 status[0x8];
8503 u8 reserved_0[0x18];
8505 u8 syndrome[0x20];
8507 u8 reserved_1[0x40];
8511 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
8515 u8 opcode[0x10];
8516 u8 uid[0x10];
8518 u8 reserved_1[0x10];
8519 u8 op_mod[0x10];
8521 u8 reserved_2[0x8];
8522 u8 srq_number[0x18];
8524 u8 reserved_3[0x10];
8525 u8 lwm[0x10];
8529 u8 status[0x8];
8530 u8 reserved_0[0x18];
8532 u8 syndrome[0x20];
8534 u8 reserved_1[0x40];
8538 u8 opcode[0x10];
8539 u8 reserved_0[0x10];
8541 u8 reserved_1[0x10];
8542 u8 op_mod[0x10];
8544 u8 reserved_2[0x8];
8545 u8 dctn[0x18];
8547 u8 reserved_3[0x20];
8551 u8 status[0x8];
8552 u8 reserved_0[0x18];
8554 u8 syndrome[0x20];
8556 u8 reserved_1[0x8];
8557 u8 xrcd[0x18];
8559 u8 reserved_2[0x20];
8563 u8 opcode[0x10];
8564 u8 uid[0x10];
8566 u8 reserved_1[0x10];
8567 u8 op_mod[0x10];
8569 u8 reserved_2[0x40];
8573 u8 status[0x8];
8574 u8 reserved_0[0x18];
8576 u8 syndrome[0x20];
8578 u8 reserved_1[0x8];
8579 u8 uar[0x18];
8581 u8 reserved_2[0x20];
8585 u8 opcode[0x10];
8586 u8 reserved_0[0x10];
8588 u8 reserved_1[0x10];
8589 u8 op_mod[0x10];
8591 u8 reserved_2[0x40];
8595 u8 status[0x8];
8596 u8 reserved_0[0x18];
8598 u8 syndrome[0x20];
8600 u8 reserved_1[0x8];
8601 u8 transport_domain[0x18];
8603 u8 reserved_2[0x20];
8607 u8 opcode[0x10];
8608 u8 uid[0x10];
8610 u8 reserved_1[0x10];
8611 u8 op_mod[0x10];
8613 u8 reserved_2[0x40];
8617 u8 status[0x8];
8618 u8 reserved_0[0x18];
8620 u8 syndrome[0x20];
8622 u8 reserved_1[0x18];
8623 u8 counter_set_id[0x8];
8625 u8 reserved_2[0x20];
8629 u8 opcode[0x10];
8630 u8 uid[0x10];
8632 u8 reserved_1[0x10];
8633 u8 op_mod[0x10];
8635 u8 reserved_2[0x40];
8639 u8 status[0x8];
8640 u8 reserved_0[0x18];
8642 u8 syndrome[0x20];
8644 u8 reserved_1[0x8];
8645 u8 pd[0x18];
8647 u8 reserved_2[0x20];
8651 u8 opcode[0x10];
8652 u8 uid[0x10];
8654 u8 reserved_1[0x10];
8655 u8 op_mod[0x10];
8657 u8 reserved_2[0x40];
8661 u8 status[0x8];
8662 u8 reserved_at_8[0x18];
8664 u8 syndrome[0x20];
8666 u8 flow_counter_id[0x20];
8668 u8 reserved_at_60[0x20];
8672 u8 opcode[0x10];
8673 u8 reserved_at_10[0x10];
8675 u8 reserved_at_20[0x10];
8676 u8 op_mod[0x10];
8678 u8 reserved_at_40[0x38];
8679 u8 flow_counter_bulk[0x8];
8683 u8 status[0x8];
8684 u8 reserved_0[0x18];
8686 u8 syndrome[0x20];
8688 u8 reserved_1[0x40];
8692 u8 opcode[0x10];
8693 u8 reserved_0[0x10];
8695 u8 reserved_1[0x10];
8696 u8 op_mod[0x10];
8698 u8 reserved_2[0x20];
8700 u8 reserved_3[0x10];
8701 u8 vxlan_udp_port[0x10];
8705 u8 status[0x8];
8706 u8 reserved_0[0x18];
8708 u8 syndrome[0x20];
8710 u8 reserved_1[0x40];
8714 u8 opcode[0x10];
8715 u8 reserved_0[0x10];
8717 u8 reserved_1[0x10];
8718 u8 op_mod[0x10];
8720 u8 mkey[0x20];
8722 u8 reserved_2[0x20];
8726 u8 status[0x8];
8727 u8 reserved_at_8[0x18];
8729 u8 syndrome[0x20];
8731 u8 reserved_at_40[0x40];
8735 u8 opcode[0x10];
8736 u8 uid[0x10];
8738 u8 reserved_at_20[0x10];
8739 u8 op_mod[0x10];
8741 u8 reserved_at_40[0x10];
8742 u8 rate_limit_index[0x10];
8744 u8 reserved_at_60[0x20];
8746 u8 rate_limit[0x20];
8748 u8 burst_upper_bound[0x20];
8750 u8 reserved_at_c0[0x10];
8751 u8 typical_packet_size[0x10];
8753 u8 reserved_at_e0[0x120];
8757 u8 status[0x8];
8758 u8 reserved_0[0x18];
8760 u8 syndrome[0x20];
8762 u8 reserved_1[0x40];
8764 u8 register_data[0][0x20];
8768 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
8769 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
8773 u8 opcode[0x10];
8774 u8 reserved_0[0x10];
8776 u8 reserved_1[0x10];
8777 u8 op_mod[0x10];
8779 u8 reserved_2[0x10];
8780 u8 register_id[0x10];
8782 u8 argument[0x20];
8784 u8 register_data[0][0x20];
8788 u8 status[0x4];
8789 u8 version[0x4];
8790 u8 local_port[0x8];
8791 u8 pnat[0x2];
8792 u8 reserved_0[0x2];
8793 u8 lane[0x4];
8794 u8 reserved_1[0x8];
8796 u8 reserved_2[0x20];
8798 u8 reserved_3[0x7];
8799 u8 polarity[0x1];
8800 u8 ob_tap0[0x8];
8801 u8 ob_tap1[0x8];
8802 u8 ob_tap2[0x8];
8804 u8 reserved_4[0xc];
8805 u8 ob_preemp_mode[0x4];
8806 u8 ob_reg[0x8];
8807 u8 ob_bias[0x8];
8809 u8 reserved_5[0x20];
8813 u8 status[0x4];
8814 u8 version[0x4];
8815 u8 local_port[0x8];
8816 u8 pnat[0x2];
8817 u8 reserved_0[0x2];
8818 u8 lane[0x4];
8819 u8 reserved_1[0x8];
8821 u8 ib_sel[0x2];
8822 u8 reserved_2[0x11];
8823 u8 dp_sel[0x1];
8824 u8 dp90sel[0x4];
8825 u8 mix90phase[0x8];
8827 u8 ffe_tap0[0x8];
8828 u8 ffe_tap1[0x8];
8829 u8 ffe_tap2[0x8];
8830 u8 ffe_tap3[0x8];
8832 u8 ffe_tap4[0x8];
8833 u8 ffe_tap5[0x8];
8834 u8 ffe_tap6[0x8];
8835 u8 ffe_tap7[0x8];
8837 u8 ffe_tap8[0x8];
8838 u8 mixerbias_tap_amp[0x8];
8839 u8 reserved_3[0x7];
8840 u8 ffe_tap_en[0x9];
8842 u8 ffe_tap_offset0[0x8];
8843 u8 ffe_tap_offset1[0x8];
8844 u8 slicer_offset0[0x10];
8846 u8 mixer_offset0[0x10];
8847 u8 mixer_offset1[0x10];
8849 u8 mixerbgn_inp[0x8];
8850 u8 mixerbgn_inn[0x8];
8851 u8 mixerbgn_refp[0x8];
8852 u8 mixerbgn_refn[0x8];
8854 u8 sel_slicer_lctrl_h[0x1];
8855 u8 sel_slicer_lctrl_l[0x1];
8856 u8 reserved_4[0x1];
8857 u8 ref_mixer_vreg[0x5];
8858 u8 slicer_gctrl[0x8];
8859 u8 lctrl_input[0x8];
8860 u8 mixer_offset_cm1[0x8];
8862 u8 common_mode[0x6];
8863 u8 reserved_5[0x1];
8864 u8 mixer_offset_cm0[0x9];
8865 u8 reserved_6[0x7];
8866 u8 slicer_offset_cm[0x9];
8870 u8 status[0x4];
8871 u8 version[0x4];
8872 u8 local_port[0x8];
8873 u8 pnat[0x2];
8874 u8 reserved_0[0x2];
8875 u8 lane[0x4];
8876 u8 reserved_1[0x8];
8878 u8 time_to_link_up[0x10];
8879 u8 reserved_2[0xc];
8880 u8 grade_lane_speed[0x4];
8882 u8 grade_version[0x8];
8883 u8 grade[0x18];
8885 u8 reserved_3[0x4];
8886 u8 height_grade_type[0x4];
8887 u8 height_grade[0x18];
8889 u8 height_dz[0x10];
8890 u8 height_dv[0x10];
8892 u8 reserved_4[0x10];
8893 u8 height_sigma[0x10];
8895 u8 reserved_5[0x20];
8897 u8 reserved_6[0x4];
8898 u8 phase_grade_type[0x4];
8899 u8 phase_grade[0x18];
8901 u8 reserved_7[0x8];
8902 u8 phase_eo_pos[0x8];
8903 u8 reserved_8[0x8];
8904 u8 phase_eo_neg[0x8];
8906 u8 ffe_set_tested[0x10];
8907 u8 test_errors_per_lane[0x10];
8911 u8 reserved_0[0x8];
8912 u8 local_port[0x8];
8913 u8 reserved_1[0x10];
8915 u8 reserved_2[0x1c];
8916 u8 vl_hw_cap[0x4];
8918 u8 reserved_3[0x1c];
8919 u8 vl_admin[0x4];
8921 u8 reserved_4[0x1c];
8922 u8 vl_operational[0x4];
8926 u8 swid[0x8];
8927 u8 local_port[0x8];
8928 u8 reserved_0[0x4];
8929 u8 admin_status[0x4];
8930 u8 reserved_1[0x4];
8931 u8 oper_status[0x4];
8933 u8 reserved_2[0x60];
8937 MLX5_PTYS_REG_PROTO_MASK_INFINIBAND = 0x1,
8938 MLX5_PTYS_REG_PROTO_MASK_ETHERNET = 0x4,
8942 u8 reserved_0[0x1];
8943 u8 an_disable_admin[0x1];
8944 u8 an_disable_cap[0x1];
8945 u8 reserved_1[0x4];
8946 u8 force_tx_aba_param[0x1];
8947 u8 local_port[0x8];
8948 u8 reserved_2[0xd];
8949 u8 proto_mask[0x3];
8951 u8 an_status[0x4];
8952 u8 reserved_3[0xc];
8953 u8 data_rate_oper[0x10];
8955 u8 ext_eth_proto_capability[0x20];
8957 u8 eth_proto_capability[0x20];
8959 u8 ib_link_width_capability[0x10];
8960 u8 ib_proto_capability[0x10];
8962 u8 ext_eth_proto_admin[0x20];
8964 u8 eth_proto_admin[0x20];
8966 u8 ib_link_width_admin[0x10];
8967 u8 ib_proto_admin[0x10];
8969 u8 ext_eth_proto_oper[0x20];
8971 u8 eth_proto_oper[0x20];
8973 u8 ib_link_width_oper[0x10];
8974 u8 ib_proto_oper[0x10];
8976 u8 reserved_4[0x1c];
8977 u8 connector_type[0x4];
8979 u8 eth_proto_lp_advertise[0x20];
8981 u8 reserved_5[0x60];
8985 u8 reserved_0[0x20];
8987 u8 algorithm_options[0x10];
8988 u8 reserved_1[0x4];
8989 u8 repetitions_mode[0x4];
8990 u8 num_of_repetitions[0x8];
8992 u8 grade_version[0x8];
8993 u8 height_grade_type[0x4];
8994 u8 phase_grade_type[0x4];
8995 u8 height_grade_weight[0x8];
8996 u8 phase_grade_weight[0x8];
8998 u8 gisim_measure_bits[0x10];
8999 u8 adaptive_tap_measure_bits[0x10];
9001 u8 ber_bath_high_error_threshold[0x10];
9002 u8 ber_bath_mid_error_threshold[0x10];
9004 u8 ber_bath_low_error_threshold[0x10];
9005 u8 one_ratio_high_threshold[0x10];
9007 u8 one_ratio_high_mid_threshold[0x10];
9008 u8 one_ratio_low_mid_threshold[0x10];
9010 u8 one_ratio_low_threshold[0x10];
9011 u8 ndeo_error_threshold[0x10];
9013 u8 mixer_offset_step_size[0x10];
9014 u8 reserved_2[0x8];
9015 u8 mix90_phase_for_voltage_bath[0x8];
9017 u8 mixer_offset_start[0x10];
9018 u8 mixer_offset_end[0x10];
9020 u8 reserved_3[0x15];
9021 u8 ber_test_time[0xb];
9025 u8 swid[0x8];
9026 u8 local_port[0x8];
9027 u8 sub_port[0x8];
9028 u8 reserved_0[0x8];
9030 u8 reserved_1[0x20];
9034 u8 reserved_0[0x8];
9035 u8 local_port[0x8];
9036 u8 reserved_1[0x10];
9038 u8 reserved_2[0x60];
9040 u8 reserved_3[0x1c];
9041 u8 wrps_admin[0x4];
9043 u8 reserved_4[0x1c];
9044 u8 wrps_status[0x4];
9046 u8 up_th_vld[0x1];
9047 u8 down_th_vld[0x1];
9048 u8 reserved_5[0x6];
9049 u8 up_threshold[0x8];
9050 u8 reserved_6[0x8];
9051 u8 down_threshold[0x8];
9053 u8 reserved_7[0x20];
9055 u8 reserved_8[0x1c];
9056 u8 srps_admin[0x4];
9058 u8 reserved_9[0x60];
9062 u8 reserved_0[0x8];
9063 u8 local_port[0x8];
9064 u8 reserved_1[0x10];
9066 u8 reserved_2[0x8];
9067 u8 lb_cap[0x8];
9068 u8 reserved_3[0x8];
9069 u8 lb_en[0x8];
9073 u8 reserved_at_0[0x8];
9074 u8 local_port[0x8];
9075 u8 reserved_at_10[0x10];
9077 u8 reserved_at_20[0x20];
9079 u8 port_profile_mode[0x8];
9080 u8 static_port_profile[0x8];
9081 u8 active_port_profile[0x8];
9082 u8 reserved_at_58[0x8];
9084 u8 retransmission_active[0x8];
9085 u8 fec_mode_active[0x18];
9087 u8 rs_fec_correction_bypass_cap[0x4];
9088 u8 reserved_at_84[0x8];
9089 u8 fec_override_cap_56g[0x4];
9090 u8 fec_override_cap_100g[0x4];
9091 u8 fec_override_cap_50g[0x4];
9092 u8 fec_override_cap_25g[0x4];
9093 u8 fec_override_cap_10g_40g[0x4];
9095 u8 rs_fec_correction_bypass_admin[0x4];
9096 u8 reserved_at_a4[0x8];
9097 u8 fec_override_admin_56g[0x4];
9098 u8 fec_override_admin_100g[0x4];
9099 u8 fec_override_admin_50g[0x4];
9100 u8 fec_override_admin_25g[0x4];
9101 u8 fec_override_admin_10g_40g[0x4];
9103 u8 fec_override_cap_400g_8x[0x10];
9104 u8 fec_override_cap_200g_4x[0x10];
9105 u8 fec_override_cap_100g_2x[0x10];
9106 u8 fec_override_cap_50g_1x[0x10];
9108 u8 fec_override_admin_400g_8x[0x10];
9109 u8 fec_override_admin_200g_4x[0x10];
9110 u8 fec_override_admin_100g_2x[0x10];
9111 u8 fec_override_admin_50g_1x[0x10];
9113 u8 reserved_at_140[0x140];
9117 u8 num_pll_groups[0x8];
9118 u8 pll_group[0x8];
9119 u8 reserved_0[0x4];
9120 u8 num_plls[0x4];
9121 u8 reserved_1[0x8];
9123 u8 reserved_2[0x1f];
9124 u8 ae[0x1];
9126 u8 pll_status[4][0x40];
9130 u8 reserved_0[0x3];
9131 u8 single_mac[0x1];
9132 u8 reserved_1[0x4];
9133 u8 local_port[0x8];
9134 u8 mac_47_32[0x10];
9136 u8 mac_31_0[0x20];
9138 u8 reserved_2[0x40];
9142 u8 reserved_0[0x8];
9143 u8 local_port[0x8];
9144 u8 reserved_1[0x10];
9146 u8 max_mtu[0x10];
9147 u8 reserved_2[0x10];
9149 u8 admin_mtu[0x10];
9150 u8 reserved_3[0x10];
9152 u8 oper_mtu[0x10];
9153 u8 reserved_4[0x10];
9157 u8 reserved_0[0x8];
9158 u8 module[0x8];
9159 u8 reserved_1[0x10];
9161 u8 reserved_2[0x18];
9162 u8 attenuation_5g[0x8];
9164 u8 reserved_3[0x18];
9165 u8 attenuation_7g[0x8];
9167 u8 reserved_4[0x18];
9168 u8 attenuation_12g[0x8];
9172 u8 reserved_0[0x8];
9173 u8 module[0x8];
9174 u8 reserved_1[0xc];
9175 u8 module_status[0x4];
9177 u8 reserved_2[0x14];
9178 u8 error_type[0x4];
9179 u8 reserved_3[0x8];
9181 u8 reserved_4[0x40];
9185 u8 module_state_updated[32][0x8];
9189 u8 reserved_0[0x4];
9190 u8 mlpn_status[0x4];
9191 u8 local_port[0x8];
9192 u8 reserved_1[0x10];
9194 u8 e[0x1];
9195 u8 reserved_2[0x1f];
9199 u8 rxtx[0x1];
9200 u8 reserved_0[0x7];
9201 u8 local_port[0x8];
9202 u8 reserved_1[0x8];
9203 u8 width[0x8];
9205 u8 lane0_module_mapping[0x20];
9207 u8 lane1_module_mapping[0x20];
9209 u8 lane2_module_mapping[0x20];
9211 u8 lane3_module_mapping[0x20];
9213 u8 reserved_2[0x160];
9217 u8 reserved_0[0x8];
9218 u8 module[0x8];
9219 u8 reserved_1[0x4];
9220 u8 admin_status[0x4];
9221 u8 reserved_2[0x4];
9222 u8 oper_status[0x4];
9224 u8 ase[0x1];
9225 u8 ee[0x1];
9226 u8 reserved_3[0x12];
9227 u8 error_type[0x4];
9228 u8 reserved_4[0x6];
9229 u8 e[0x2];
9231 u8 reserved_5[0x40];
9235 u8 reserved_0[0x4];
9236 u8 profile_id[0xc];
9237 u8 reserved_1[0x4];
9238 u8 proto_mask[0x4];
9239 u8 reserved_2[0x8];
9241 u8 reserved_3[0x10];
9242 u8 lane_speed[0x10];
9244 u8 reserved_4[0x17];
9245 u8 lpbf[0x1];
9246 u8 fec_mode_policy[0x8];
9248 u8 retransmission_capability[0x8];
9249 u8 fec_mode_capability[0x18];
9251 u8 retransmission_support_admin[0x8];
9252 u8 fec_mode_support_admin[0x18];
9254 u8 retransmission_request_admin[0x8];
9255 u8 fec_mode_request_admin[0x18];
9257 u8 reserved_5[0x80];
9261 u8 reserved_0[0x1];
9262 u8 lock_cal[0x1];
9263 u8 lock_status[0x2];
9264 u8 reserved_1[0x2];
9265 u8 algo_f_ctrl[0xa];
9266 u8 analog_algo_num_var[0x6];
9267 u8 f_ctrl_measure[0xa];
9269 u8 reserved_2[0x2];
9270 u8 analog_var[0x6];
9271 u8 reserved_3[0x2];
9272 u8 high_var[0x6];
9273 u8 reserved_4[0x2];
9274 u8 low_var[0x6];
9275 u8 reserved_5[0x2];
9276 u8 mid_val[0x6];
9280 u8 reserved_0[0x8];
9281 u8 local_port[0x8];
9282 u8 reserved_1[0x8];
9283 u8 ib_port[0x8];
9285 u8 reserved_2[0x60];
9289 u8 reserved_0[0x8];
9290 u8 local_port[0x8];
9291 u8 reserved_1[0xd];
9292 u8 lbf_mode[0x3];
9294 u8 reserved_2[0x20];
9298 u8 reserved_0[0x8];
9299 u8 local_port[0x8];
9300 u8 reserved_1[0x10];
9302 u8 dic[0x1];
9303 u8 reserved_2[0x19];
9304 u8 ipg[0x4];
9305 u8 reserved_3[0x2];
9309 u8 reserved_0[0x8];
9310 u8 local_port[0x8];
9311 u8 reserved_1[0x10];
9313 u8 reserved_2[0xe0];
9315 u8 port_filter[8][0x20];
9317 u8 port_filter_update_en[8][0x20];
9321 u8 time_since_last_clear_high[0x20];
9323 u8 time_since_last_clear_low[0x20];
9325 u8 symbol_errors_high[0x20];
9327 u8 symbol_errors_low[0x20];
9329 u8 sync_headers_errors_high[0x20];
9331 u8 sync_headers_errors_low[0x20];
9333 u8 edpl_bip_errors_lane0_high[0x20];
9335 u8 edpl_bip_errors_lane0_low[0x20];
9337 u8 edpl_bip_errors_lane1_high[0x20];
9339 u8 edpl_bip_errors_lane1_low[0x20];
9341 u8 edpl_bip_errors_lane2_high[0x20];
9343 u8 edpl_bip_errors_lane2_low[0x20];
9345 u8 edpl_bip_errors_lane3_high[0x20];
9347 u8 edpl_bip_errors_lane3_low[0x20];
9349 u8 fc_fec_corrected_blocks_lane0_high[0x20];
9351 u8 fc_fec_corrected_blocks_lane0_low[0x20];
9353 u8 fc_fec_corrected_blocks_lane1_high[0x20];
9355 u8 fc_fec_corrected_blocks_lane1_low[0x20];
9357 u8 fc_fec_corrected_blocks_lane2_high[0x20];
9359 u8 fc_fec_corrected_blocks_lane2_low[0x20];
9361 u8 fc_fec_corrected_blocks_lane3_high[0x20];
9363 u8 fc_fec_corrected_blocks_lane3_low[0x20];
9365 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
9367 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
9369 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
9371 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
9373 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
9375 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
9377 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
9379 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
9381 u8 rs_fec_corrected_blocks_high[0x20];
9383 u8 rs_fec_corrected_blocks_low[0x20];
9385 u8 rs_fec_uncorrectable_blocks_high[0x20];
9387 u8 rs_fec_uncorrectable_blocks_low[0x20];
9389 u8 rs_fec_no_errors_blocks_high[0x20];
9391 u8 rs_fec_no_errors_blocks_low[0x20];
9393 u8 rs_fec_single_error_blocks_high[0x20];
9395 u8 rs_fec_single_error_blocks_low[0x20];
9397 u8 rs_fec_corrected_symbols_total_high[0x20];
9399 u8 rs_fec_corrected_symbols_total_low[0x20];
9401 u8 rs_fec_corrected_symbols_lane0_high[0x20];
9403 u8 rs_fec_corrected_symbols_lane0_low[0x20];
9405 u8 rs_fec_corrected_symbols_lane1_high[0x20];
9407 u8 rs_fec_corrected_symbols_lane1_low[0x20];
9409 u8 rs_fec_corrected_symbols_lane2_high[0x20];
9411 u8 rs_fec_corrected_symbols_lane2_low[0x20];
9413 u8 rs_fec_corrected_symbols_lane3_high[0x20];
9415 u8 rs_fec_corrected_symbols_lane3_low[0x20];
9417 u8 link_down_events[0x20];
9419 u8 successful_recovery_events[0x20];
9421 u8 reserved_0[0x180];
9425 u8 symbol_error_counter[0x10];
9427 u8 link_error_recovery_counter[0x8];
9429 u8 link_downed_counter[0x8];
9431 u8 port_rcv_errors[0x10];
9433 u8 port_rcv_remote_physical_errors[0x10];
9435 u8 port_rcv_switch_relay_errors[0x10];
9437 u8 port_xmit_discards[0x10];
9439 u8 port_xmit_constraint_errors[0x8];
9441 u8 port_rcv_constraint_errors[0x8];
9443 u8 reserved_at_70[0x8];
9445 u8 link_overrun_errors[0x8];
9447 u8 reserved_at_80[0x10];
9449 u8 vl_15_dropped[0x10];
9451 u8 reserved_at_a0[0xa0];
9455 u8 time_since_last_clear_high[0x20];
9457 u8 time_since_last_clear_low[0x20];
9459 u8 phy_received_bits_high[0x20];
9461 u8 phy_received_bits_low[0x20];
9463 u8 phy_symbol_errors_high[0x20];
9465 u8 phy_symbol_errors_low[0x20];
9467 u8 phy_corrected_bits_high[0x20];
9469 u8 phy_corrected_bits_low[0x20];
9471 u8 phy_corrected_bits_lane0_high[0x20];
9473 u8 phy_corrected_bits_lane0_low[0x20];
9475 u8 phy_corrected_bits_lane1_high[0x20];
9477 u8 phy_corrected_bits_lane1_low[0x20];
9479 u8 phy_corrected_bits_lane2_high[0x20];
9481 u8 phy_corrected_bits_lane2_low[0x20];
9483 u8 phy_corrected_bits_lane3_high[0x20];
9485 u8 phy_corrected_bits_lane3_low[0x20];
9487 u8 reserved_at_200[0x5c0];
9491 u8 symbol_error_counter[0x10];
9492 u8 link_error_recovery_counter[0x8];
9493 u8 link_downed_counter[0x8];
9495 u8 port_rcv_errors[0x10];
9496 u8 port_rcv_remote_physical_errors[0x10];
9498 u8 port_rcv_switch_relay_errors[0x10];
9499 u8 port_xmit_discards[0x10];
9501 u8 port_xmit_constraint_errors[0x8];
9502 u8 port_rcv_constraint_errors[0x8];
9503 u8 reserved_0[0x8];
9504 u8 local_link_integrity_errors[0x4];
9505 u8 excessive_buffer_overrun_errors[0x4];
9507 u8 reserved_1[0x10];
9508 u8 vl_15_dropped[0x10];
9510 u8 port_xmit_data[0x20];
9512 u8 port_rcv_data[0x20];
9514 u8 port_xmit_pkts[0x20];
9516 u8 port_rcv_pkts[0x20];
9518 u8 port_xmit_wait[0x20];
9520 u8 reserved_2[0x680];
9524 u8 clr[0x1];
9525 u8 reserved_0[0x7];
9526 u8 local_port[0x8];
9527 u8 reserved_1[0x10];
9529 u8 hist_group[0x8];
9530 u8 reserved_2[0x10];
9531 u8 hist_id[0x8];
9533 u8 reserved_3[0x40];
9535 u8 time_since_last_clear_high[0x20];
9537 u8 time_since_last_clear_low[0x20];
9539 u8 bin[10][0x20];
9543 u8 reserved_0[0x18];
9544 u8 prio[0x8];
9548 u8 reserved_0[0x18];
9549 u8 tclass[0x8];
9553 u8 opcode[0x4];
9554 u8 reserved_0[0x4];
9555 u8 local_port[0x8];
9556 u8 pnat[0x2];
9557 u8 reserved_1[0xe];
9559 u8 hist_group[0x8];
9560 u8 reserved_2[0x10];
9561 u8 hist_id[0x8];
9563 u8 reserved_3[0x10];
9564 u8 hist_type[0x10];
9566 u8 hist_parameters[0x20];
9568 u8 hist_min_value[0x20];
9570 u8 hist_max_value[0x20];
9572 u8 sample_time[0x20];
9576 MLX5_PFCC_REG_PPAN_DISABLED = 0x0,
9577 MLX5_PFCC_REG_PPAN_ENABLED = 0x1,
9581 u8 dcbx_operation_type[0x2];
9582 u8 cap_local_admin[0x1];
9583 u8 cap_remote_admin[0x1];
9584 u8 reserved_0[0x4];
9585 u8 local_port[0x8];
9586 u8 pnat[0x2];
9587 u8 reserved_1[0xc];
9588 u8 shl_cap[0x1];
9589 u8 shl_opr[0x1];
9591 u8 ppan[0x4];
9592 u8 reserved_2[0x4];
9593 u8 prio_mask_tx[0x8];
9594 u8 reserved_3[0x8];
9595 u8 prio_mask_rx[0x8];
9597 u8 pptx[0x1];
9598 u8 aptx[0x1];
9599 u8 reserved_4[0x6];
9600 u8 pfctx[0x8];
9601 u8 reserved_5[0x8];
9602 u8 cbftx[0x8];
9604 u8 pprx[0x1];
9605 u8 aprx[0x1];
9606 u8 reserved_6[0x6];
9607 u8 pfcrx[0x8];
9608 u8 reserved_7[0x8];
9609 u8 cbfrx[0x8];
9611 u8 device_stall_minor_watermark[0x10];
9612 u8 device_stall_critical_watermark[0x10];
9614 u8 reserved_8[0x60];
9618 u8 op[0x4];
9619 u8 reserved_0[0x4];
9620 u8 local_port[0x8];
9621 u8 reserved_1[0x10];
9623 u8 op_admin[0x8];
9624 u8 op_capability[0x8];
9625 u8 op_request[0x8];
9626 u8 op_active[0x8];
9628 u8 admin[0x40];
9630 u8 capability[0x40];
9632 u8 request[0x40];
9634 u8 active[0x40];
9636 u8 reserved_2[0x80];
9640 u8 reserved_0[0x8];
9641 u8 local_port[0x8];
9642 u8 reserved_1[0x10];
9644 u8 reserved_2[0xc];
9645 u8 error_count[0x4];
9646 u8 reserved_3[0x10];
9648 u8 reserved_4[0xc];
9649 u8 lane[0x4];
9650 u8 reserved_5[0x8];
9651 u8 error_type[0x8];
9655 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
9656 u8 qpdpm[0x1];
9657 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
9658 u8 qdpm[0x1];
9659 u8 qpts[0x1];
9660 u8 qcap[0x1];
9661 u8 qcam_access_reg_cap_mask_0[0x1];
9665 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
9666 u8 qpts_trust_both[0x1];
9670 u8 reserved_at_0[0x8];
9671 u8 feature_group[0x8];
9672 u8 reserved_at_10[0x8];
9673 u8 access_reg_group[0x8];
9674 u8 reserved_at_20[0x20];
9678 u8 reserved_at_0[0x80];
9681 u8 reserved_at_c0[0x80];
9685 u8 reserved_at_0[0x80];
9688 u8 reserved_at_1c0[0x80];
9692 u8 reserved_at_0[0x6d];
9693 u8 rx_icrc_encapsulated_counter[0x1];
9694 u8 reserved_at_6e[0x4];
9695 u8 ptys_extended_ethernet[0x1];
9696 u8 reserved_at_73[0x3];
9697 u8 pfcc_mask[0x1];
9698 u8 reserved_at_77[0x3];
9699 u8 per_lane_error_counters[0x1];
9700 u8 rx_buffer_fullness_counters[0x1];
9701 u8 ptys_connector_type[0x1];
9702 u8 reserved_at_7d[0x1];
9703 u8 ppcnt_discard_group[0x1];
9704 u8 ppcnt_statistical_group[0x1];
9708 u8 port_access_reg_cap_mask_127_to_96[0x20];
9709 u8 port_access_reg_cap_mask_95_to_64[0x20];
9711 u8 reserved_at_40[0xe];
9712 u8 pddr[0x1];
9713 u8 reserved_at_4f[0xd];
9715 u8 pplm[0x1];
9716 u8 port_access_reg_cap_mask_34_to_32[0x3];
9718 u8 port_access_reg_cap_mask_31_to_13[0x13];
9719 u8 pbmc[0x1];
9720 u8 pptb[0x1];
9721 u8 port_access_reg_cap_mask_10_to_09[0x2];
9722 u8 ppcnt[0x1];
9723 u8 port_access_reg_cap_mask_07_to_00[0x8];
9727 u8 reserved_at_0[0x8];
9728 u8 feature_group[0x8];
9729 u8 reserved_at_10[0x8];
9730 u8 access_reg_group[0x8];
9732 u8 reserved_at_20[0x20];
9736 u8 reserved_at_0[0x80];
9739 u8 reserved_at_c0[0x80];
9743 u8 reserved_at_0[0x80];
9746 u8 reserved_at_1c0[0xc0];
9750 u8 reserved_at_0[0x6e];
9751 u8 pcie_status_and_power[0x1];
9752 u8 reserved_at_111[0x10];
9753 u8 pcie_performance_group[0x1];
9757 u8 reserved_at_0[0x1c];
9758 u8 mcda[0x1];
9759 u8 mcc[0x1];
9760 u8 mcqi[0x1];
9761 u8 reserved_at_1f[0x1];
9763 u8 regs_95_to_64[0x20];
9764 u8 regs_63_to_32[0x20];
9765 u8 regs_31_to_0[0x20];
9769 u8 reserved_at_0[0x8];
9770 u8 feature_group[0x8];
9771 u8 reserved_at_10[0x8];
9772 u8 access_reg_group[0x8];
9774 u8 reserved_at_20[0x20];
9778 u8 reserved_at_0[0x80];
9781 u8 reserved_at_c0[0x80];
9785 u8 reserved_at_0[0x80];
9788 u8 reserved_at_1c0[0x80];
9792 u8 reserved_0[0x8];
9793 u8 local_port[0x8];
9794 u8 reserved_1[0x10];
9796 u8 port_capability_mask[4][0x20];
9800 u8 reserved_at_0[0x8];
9801 u8 local_port[0x8];
9802 u8 reserved_at_10[0x10];
9804 u8 xoff_timer_value[0x10];
9805 u8 xoff_refresh[0x10];
9807 u8 reserved_at_40[0x9];
9808 u8 fullness_threshold[0x7];
9809 u8 port_buffer_size[0x10];
9813 u8 reserved_at_2e0[0x80];
9817 u8 swid[0x8];
9818 u8 local_port[0x8];
9819 u8 reserved_0[0x4];
9820 u8 admin_status[0x4];
9821 u8 reserved_1[0x4];
9822 u8 oper_status[0x4];
9824 u8 ase[0x1];
9825 u8 ee[0x1];
9826 u8 reserved_2[0x1c];
9827 u8 e[0x2];
9829 u8 reserved_3[0x40];
9833 u8 reserved_0[0x8];
9834 u8 opamp_group[0x8];
9835 u8 reserved_1[0xc];
9836 u8 opamp_group_type[0x4];
9838 u8 start_index[0x10];
9839 u8 reserved_2[0x4];
9840 u8 num_of_indices[0xc];
9842 u8 index_data[18][0x10];
9846 u8 llr_rx_cells_high[0x20];
9848 u8 llr_rx_cells_low[0x20];
9850 u8 llr_rx_error_high[0x20];
9852 u8 llr_rx_error_low[0x20];
9854 u8 llr_rx_crc_error_high[0x20];
9856 u8 llr_rx_crc_error_low[0x20];
9858 u8 llr_tx_cells_high[0x20];
9860 u8 llr_tx_cells_low[0x20];
9862 u8 llr_tx_ret_cells_high[0x20];
9864 u8 llr_tx_ret_cells_low[0x20];
9866 u8 llr_tx_ret_events_high[0x20];
9868 u8 llr_tx_ret_events_low[0x20];
9870 u8 reserved_0[0x640];
9874 u8 i[0x1];
9875 u8 reserved_at_1[0x18];
9876 u8 sensor_index[0x7];
9878 u8 reserved_at_20[0x10];
9879 u8 temperature[0x10];
9881 u8 mte[0x1];
9882 u8 mtr[0x1];
9883 u8 reserved_at_42[0x0e];
9884 u8 max_temperature[0x10];
9886 u8 tee[0x2];
9887 u8 reserved_at_62[0x0e];
9888 u8 temperature_threshold_hi[0x10];
9890 u8 reserved_at_80[0x10];
9891 u8 temperature_threshold_lo[0x10];
9893 u8 reserved_at_100[0x20];
9895 u8 sensor_name[0x40];
9899 u8 reserved_0[0x6];
9900 u8 rx_lane[0x2];
9901 u8 reserved_1[0x6];
9902 u8 tx_lane[0x2];
9903 u8 reserved_2[0x8];
9904 u8 module[0x8];
9908 u8 transmit_queue_high[0x20];
9910 u8 transmit_queue_low[0x20];
9912 u8 reserved_0[0x780];
9916 u8 no_buffer_discard_uc_high[0x20];
9918 u8 no_buffer_discard_uc_low[0x20];
9920 u8 wred_discard_high[0x20];
9922 u8 wred_discard_low[0x20];
9924 u8 reserved_0[0x740];
9928 u8 rx_octets_high[0x20];
9930 u8 rx_octets_low[0x20];
9932 u8 reserved_0[0xc0];
9934 u8 rx_frames_high[0x20];
9936 u8 rx_frames_low[0x20];
9938 u8 tx_octets_high[0x20];
9940 u8 tx_octets_low[0x20];
9942 u8 reserved_1[0xc0];
9944 u8 tx_frames_high[0x20];
9946 u8 tx_frames_low[0x20];
9948 u8 rx_pause_high[0x20];
9950 u8 rx_pause_low[0x20];
9952 u8 rx_pause_duration_high[0x20];
9954 u8 rx_pause_duration_low[0x20];
9956 u8 tx_pause_high[0x20];
9958 u8 tx_pause_low[0x20];
9960 u8 tx_pause_duration_high[0x20];
9962 u8 tx_pause_duration_low[0x20];
9964 u8 rx_pause_transition_high[0x20];
9966 u8 rx_pause_transition_low[0x20];
9968 u8 rx_discards_high[0x20];
9970 u8 rx_discards_low[0x20];
9972 u8 device_stall_minor_watermark_cnt_high[0x20];
9974 u8 device_stall_minor_watermark_cnt_low[0x20];
9976 u8 device_stall_critical_watermark_cnt_high[0x20];
9978 u8 device_stall_critical_watermark_cnt_low[0x20];
9980 u8 reserved_2[0x340];
9984 u8 port_transmit_wait_high[0x20];
9986 u8 port_transmit_wait_low[0x20];
9988 u8 ecn_marked_high[0x20];
9990 u8 ecn_marked_low[0x20];
9992 u8 no_buffer_discard_mc_high[0x20];
9994 u8 no_buffer_discard_mc_low[0x20];
9996 u8 rx_ebp_high[0x20];
9998 u8 rx_ebp_low[0x20];
10000 u8 tx_ebp_high[0x20];
10002 u8 tx_ebp_low[0x20];
10004 u8 rx_buffer_almost_full_high[0x20];
10006 u8 rx_buffer_almost_full_low[0x20];
10008 u8 rx_buffer_full_high[0x20];
10010 u8 rx_buffer_full_low[0x20];
10012 u8 rx_icrc_encapsulated_high[0x20];
10014 u8 rx_icrc_encapsulated_low[0x20];
10016 u8 reserved_0[0x80];
10018 u8 tx_stats_pkts64octets_high[0x20];
10020 u8 tx_stats_pkts64octets_low[0x20];
10022 u8 tx_stats_pkts65to127octets_high[0x20];
10024 u8 tx_stats_pkts65to127octets_low[0x20];
10026 u8 tx_stats_pkts128to255octets_high[0x20];
10028 u8 tx_stats_pkts128to255octets_low[0x20];
10030 u8 tx_stats_pkts256to511octets_high[0x20];
10032 u8 tx_stats_pkts256to511octets_low[0x20];
10034 u8 tx_stats_pkts512to1023octets_high[0x20];
10036 u8 tx_stats_pkts512to1023octets_low[0x20];
10038 u8 tx_stats_pkts1024to1518octets_high[0x20];
10040 u8 tx_stats_pkts1024to1518octets_low[0x20];
10042 u8 tx_stats_pkts1519to2047octets_high[0x20];
10044 u8 tx_stats_pkts1519to2047octets_low[0x20];
10046 u8 tx_stats_pkts2048to4095octets_high[0x20];
10048 u8 tx_stats_pkts2048to4095octets_low[0x20];
10050 u8 tx_stats_pkts4096to8191octets_high[0x20];
10052 u8 tx_stats_pkts4096to8191octets_low[0x20];
10054 u8 tx_stats_pkts8192to10239octets_high[0x20];
10056 u8 tx_stats_pkts8192to10239octets_low[0x20];
10058 u8 reserved_1[0x2C0];
10062 u8 a_frames_transmitted_ok_high[0x20];
10064 u8 a_frames_transmitted_ok_low[0x20];
10066 u8 a_frames_received_ok_high[0x20];
10068 u8 a_frames_received_ok_low[0x20];
10070 u8 a_frame_check_sequence_errors_high[0x20];
10072 u8 a_frame_check_sequence_errors_low[0x20];
10074 u8 a_alignment_errors_high[0x20];
10076 u8 a_alignment_errors_low[0x20];
10078 u8 a_octets_transmitted_ok_high[0x20];
10080 u8 a_octets_transmitted_ok_low[0x20];
10082 u8 a_octets_received_ok_high[0x20];
10084 u8 a_octets_received_ok_low[0x20];
10086 u8 a_multicast_frames_xmitted_ok_high[0x20];
10088 u8 a_multicast_frames_xmitted_ok_low[0x20];
10090 u8 a_broadcast_frames_xmitted_ok_high[0x20];
10092 u8 a_broadcast_frames_xmitted_ok_low[0x20];
10094 u8 a_multicast_frames_received_ok_high[0x20];
10096 u8 a_multicast_frames_received_ok_low[0x20];
10098 u8 a_broadcast_frames_recieved_ok_high[0x20];
10100 u8 a_broadcast_frames_recieved_ok_low[0x20];
10102 u8 a_in_range_length_errors_high[0x20];
10104 u8 a_in_range_length_errors_low[0x20];
10106 u8 a_out_of_range_length_field_high[0x20];
10108 u8 a_out_of_range_length_field_low[0x20];
10110 u8 a_frame_too_long_errors_high[0x20];
10112 u8 a_frame_too_long_errors_low[0x20];
10114 u8 a_symbol_error_during_carrier_high[0x20];
10116 u8 a_symbol_error_during_carrier_low[0x20];
10118 u8 a_mac_control_frames_transmitted_high[0x20];
10120 u8 a_mac_control_frames_transmitted_low[0x20];
10122 u8 a_mac_control_frames_received_high[0x20];
10124 u8 a_mac_control_frames_received_low[0x20];
10126 u8 a_unsupported_opcodes_received_high[0x20];
10128 u8 a_unsupported_opcodes_received_low[0x20];
10130 u8 a_pause_mac_ctrl_frames_received_high[0x20];
10132 u8 a_pause_mac_ctrl_frames_received_low[0x20];
10134 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
10136 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
10138 u8 reserved_0[0x300];
10142 u8 dot3stats_alignment_errors_high[0x20];
10144 u8 dot3stats_alignment_errors_low[0x20];
10146 u8 dot3stats_fcs_errors_high[0x20];
10148 u8 dot3stats_fcs_errors_low[0x20];
10150 u8 dot3stats_single_collision_frames_high[0x20];
10152 u8 dot3stats_single_collision_frames_low[0x20];
10154 u8 dot3stats_multiple_collision_frames_high[0x20];
10156 u8 dot3stats_multiple_collision_frames_low[0x20];
10158 u8 dot3stats_sqe_test_errors_high[0x20];
10160 u8 dot3stats_sqe_test_errors_low[0x20];
10162 u8 dot3stats_deferred_transmissions_high[0x20];
10164 u8 dot3stats_deferred_transmissions_low[0x20];
10166 u8 dot3stats_late_collisions_high[0x20];
10168 u8 dot3stats_late_collisions_low[0x20];
10170 u8 dot3stats_excessive_collisions_high[0x20];
10172 u8 dot3stats_excessive_collisions_low[0x20];
10174 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
10176 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
10178 u8 dot3stats_carrier_sense_errors_high[0x20];
10180 u8 dot3stats_carrier_sense_errors_low[0x20];
10182 u8 dot3stats_frame_too_longs_high[0x20];
10184 u8 dot3stats_frame_too_longs_low[0x20];
10186 u8 dot3stats_internal_mac_receive_errors_high[0x20];
10188 u8 dot3stats_internal_mac_receive_errors_low[0x20];
10190 u8 dot3stats_symbol_errors_high[0x20];
10192 u8 dot3stats_symbol_errors_low[0x20];
10194 u8 dot3control_in_unknown_opcodes_high[0x20];
10196 u8 dot3control_in_unknown_opcodes_low[0x20];
10198 u8 dot3in_pause_frames_high[0x20];
10200 u8 dot3in_pause_frames_low[0x20];
10202 u8 dot3out_pause_frames_high[0x20];
10204 u8 dot3out_pause_frames_low[0x20];
10206 u8 reserved_0[0x3c0];
10210 u8 if_in_octets_high[0x20];
10212 u8 if_in_octets_low[0x20];
10214 u8 if_in_ucast_pkts_high[0x20];
10216 u8 if_in_ucast_pkts_low[0x20];
10218 u8 if_in_discards_high[0x20];
10220 u8 if_in_discards_low[0x20];
10222 u8 if_in_errors_high[0x20];
10224 u8 if_in_errors_low[0x20];
10226 u8 if_in_unknown_protos_high[0x20];
10228 u8 if_in_unknown_protos_low[0x20];
10230 u8 if_out_octets_high[0x20];
10232 u8 if_out_octets_low[0x20];
10234 u8 if_out_ucast_pkts_high[0x20];
10236 u8 if_out_ucast_pkts_low[0x20];
10238 u8 if_out_discards_high[0x20];
10240 u8 if_out_discards_low[0x20];
10242 u8 if_out_errors_high[0x20];
10244 u8 if_out_errors_low[0x20];
10246 u8 if_in_multicast_pkts_high[0x20];
10248 u8 if_in_multicast_pkts_low[0x20];
10250 u8 if_in_broadcast_pkts_high[0x20];
10252 u8 if_in_broadcast_pkts_low[0x20];
10254 u8 if_out_multicast_pkts_high[0x20];
10256 u8 if_out_multicast_pkts_low[0x20];
10258 u8 if_out_broadcast_pkts_high[0x20];
10260 u8 if_out_broadcast_pkts_low[0x20];
10262 u8 reserved_0[0x480];
10266 u8 ether_stats_drop_events_high[0x20];
10268 u8 ether_stats_drop_events_low[0x20];
10270 u8 ether_stats_octets_high[0x20];
10272 u8 ether_stats_octets_low[0x20];
10274 u8 ether_stats_pkts_high[0x20];
10276 u8 ether_stats_pkts_low[0x20];
10278 u8 ether_stats_broadcast_pkts_high[0x20];
10280 u8 ether_stats_broadcast_pkts_low[0x20];
10282 u8 ether_stats_multicast_pkts_high[0x20];
10284 u8 ether_stats_multicast_pkts_low[0x20];
10286 u8 ether_stats_crc_align_errors_high[0x20];
10288 u8 ether_stats_crc_align_errors_low[0x20];
10290 u8 ether_stats_undersize_pkts_high[0x20];
10292 u8 ether_stats_undersize_pkts_low[0x20];
10294 u8 ether_stats_oversize_pkts_high[0x20];
10296 u8 ether_stats_oversize_pkts_low[0x20];
10298 u8 ether_stats_fragments_high[0x20];
10300 u8 ether_stats_fragments_low[0x20];
10302 u8 ether_stats_jabbers_high[0x20];
10304 u8 ether_stats_jabbers_low[0x20];
10306 u8 ether_stats_collisions_high[0x20];
10308 u8 ether_stats_collisions_low[0x20];
10310 u8 ether_stats_pkts64octets_high[0x20];
10312 u8 ether_stats_pkts64octets_low[0x20];
10314 u8 ether_stats_pkts65to127octets_high[0x20];
10316 u8 ether_stats_pkts65to127octets_low[0x20];
10318 u8 ether_stats_pkts128to255octets_high[0x20];
10320 u8 ether_stats_pkts128to255octets_low[0x20];
10322 u8 ether_stats_pkts256to511octets_high[0x20];
10324 u8 ether_stats_pkts256to511octets_low[0x20];
10326 u8 ether_stats_pkts512to1023octets_high[0x20];
10328 u8 ether_stats_pkts512to1023octets_low[0x20];
10330 u8 ether_stats_pkts1024to1518octets_high[0x20];
10332 u8 ether_stats_pkts1024to1518octets_low[0x20];
10334 u8 ether_stats_pkts1519to2047octets_high[0x20];
10336 u8 ether_stats_pkts1519to2047octets_low[0x20];
10338 u8 ether_stats_pkts2048to4095octets_high[0x20];
10340 u8 ether_stats_pkts2048to4095octets_low[0x20];
10342 u8 ether_stats_pkts4096to8191octets_high[0x20];
10344 u8 ether_stats_pkts4096to8191octets_low[0x20];
10346 u8 ether_stats_pkts8192to10239octets_high[0x20];
10348 u8 ether_stats_pkts8192to10239octets_low[0x20];
10350 u8 reserved_0[0x280];
10354 u8 symbol_error_counter[0x10];
10355 u8 link_error_recovery_counter[0x8];
10356 u8 link_downed_counter[0x8];
10358 u8 port_rcv_errors[0x10];
10359 u8 port_rcv_remote_physical_errors[0x10];
10361 u8 port_rcv_switch_relay_errors[0x10];
10362 u8 port_xmit_discards[0x10];
10364 u8 port_xmit_constraint_errors[0x8];
10365 u8 port_rcv_constraint_errors[0x8];
10366 u8 reserved_0[0x8];
10367 u8 local_link_integrity_errors[0x4];
10368 u8 excessive_buffer_overrun_errors[0x4];
10370 u8 reserved_1[0x10];
10371 u8 vl_15_dropped[0x10];
10373 u8 port_xmit_data[0x20];
10375 u8 port_rcv_data[0x20];
10377 u8 port_xmit_pkts[0x20];
10379 u8 port_rcv_pkts[0x20];
10381 u8 port_xmit_wait[0x20];
10383 u8 reserved_2[0x680];
10387 u8 reserved_0[0x80];
10389 u8 tlb_addr[0][0x40];
10393 u8 reserved_0[0x10];
10394 u8 requested_event_num[0x10];
10396 u8 reserved_1[0x20];
10398 u8 reserved_2[0x10];
10399 u8 acual_event_num[0x10];
10401 u8 reserved_3[0x20];
10403 u8 event[0][0x40];
10407 u8 reserved_0[0x1f];
10408 u8 lock[0x1];
10410 u8 reserved_1[0x60];
10414 u8 status[0x1];
10415 u8 reserved_0[0xf];
10416 u8 filter_index[0x10];
10418 u8 reserved_1[0x20];
10420 u8 filter_val[0x20];
10422 u8 reserved_2[0x1a0];
10426 u8 status[0x1];
10427 u8 reserved_0[0xf];
10428 u8 event_index[0x10];
10430 u8 reserved_1[0x20];
10432 u8 event_id[0x20];
10434 u8 event_selector_val[0x10];
10435 u8 event_selector_size[0x10];
10437 u8 reserved_2[0x180];
10441 u8 limit_en[0x1];
10442 u8 reserved_0[0x3];
10443 u8 dump_mode[0x4];
10444 u8 reserved_1[0x15];
10445 u8 state[0x3];
10447 u8 reserved_2[0x20];
10449 u8 limit_event_index[0x20];
10451 u8 mkey[0x20];
10453 u8 fifo_ready_ev_num[0x20];
10455 u8 reserved_3[0x160];
10459 u8 reserved_0[0x18];
10460 u8 dump_mode[0x8];
10462 u8 reserved_1[0x20];
10464 u8 num_of_events[0x10];
10465 u8 num_of_filters[0x10];
10467 u8 fifo_size[0x20];
10469 u8 tlb_size[0x10];
10470 u8 event_size[0x10];
10472 u8 reserved_2[0x160];
10476 u8 node_description[64][0x8];
10480 u8 reserved_0[0x18];
10481 u8 power_settings_level[0x8];
10483 u8 reserved_1[0x60];
10487 u8 he[0x1];
10488 u8 reserved_0[0x1f];
10490 u8 reserved_1[0x60];
10494 u8 physical_address[0x40];
10498 u8 operation_type[0x2];
10499 u8 cap_local_admin[0x1];
10500 u8 cap_remote_admin[0x1];
10501 u8 reserved_0[0x4];
10502 u8 port_number[0x8];
10503 u8 reserved_1[0xd];
10504 u8 prio[0x3];
10506 u8 reserved_2[0x1d];
10507 u8 tclass[0x3];
10511 u8 reserved_0[0x8];
10512 u8 port_number[0x8];
10513 u8 reserved_1[0x10];
10515 u8 reserved_2[0x1d];
10516 u8 pprio[0x3];
10520 u8 reserved_0[0x8];
10521 u8 port[0x8];
10522 u8 max_gid[0x10];
10524 u8 reserved_1[0x20];
10526 u8 port_guid[0x40];
10530 u8 type[0x20];
10532 u8 reserved_0[0x18];
10533 u8 version[0x4];
10534 u8 reserved_1[0x2];
10535 u8 support_wr[0x1];
10536 u8 support_rd[0x1];
10540 u8 reserved_0[0x1d];
10541 u8 target[0x3];
10543 u8 reserved_1[0x20];
10553 u8 configuration_item_data[0x20];
10557 u8 system_image_guid[0x40];
10559 u8 reserved_0[0x40];
10561 u8 node_guid[0x40];
10563 u8 reserved_1[0x10];
10564 u8 max_pkey[0x10];
10566 u8 reserved_2[0x20];
10570 u8 g[0x1];
10571 u8 b[0x1];
10572 u8 r[0x1];
10573 u8 reserved_0[0x9];
10574 u8 group[0x4];
10575 u8 reserved_1[0x9];
10576 u8 bw_allocation[0x7];
10578 u8 reserved_2[0xc];
10579 u8 max_bw_units[0x4];
10580 u8 reserved_3[0x8];
10581 u8 max_bw_value[0x8];
10585 u8 reserved_0[0x2];
10586 u8 r[0x1];
10587 u8 reserved_1[0x1d];
10589 u8 reserved_2[0xc];
10590 u8 max_bw_units[0x4];
10591 u8 reserved_3[0x8];
10592 u8 max_bw_value[0x8];
10596 u8 reserved_at_0[0x8];
10597 u8 port_number[0x8];
10598 u8 reserved_at_10[0x30];
10600 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
10615 u8 reserved_0[0xc0];
10619 u8 mgid_filter0[16][0x8];
10621 u8 mgid_filter1[16][0x8];
10623 u8 mgid_filter2[16][0x8];
10625 u8 mgid_filter3[16][0x8];
10629 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_SINGLE_PORT = 0x0,
10630 MLX5_NODNIC_CONFIG_REG_NUM_PORTS_DUAL_PORT = 0x1,
10634 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_LEGACY_CQE = 0x0,
10635 MLX5_NODNIC_CONFIG_REG_CQE_FORMAT_NEW_CQE = 0x1,
10639 u8 no_dram_nic_revision[0x8];
10640 u8 hardware_format[0x8];
10641 u8 support_receive_filter[0x1];
10642 u8 support_promisc_filter[0x1];
10643 u8 support_promisc_multicast_filter[0x1];
10644 u8 reserved_0[0x2];
10645 u8 log_working_buffer_size[0x3];
10646 u8 log_pkey_table_size[0x4];
10647 u8 reserved_1[0x3];
10648 u8 num_ports[0x1];
10650 u8 reserved_2[0x2];
10651 u8 log_max_ring_size[0x6];
10652 u8 reserved_3[0x18];
10654 u8 lkey[0x20];
10656 u8 cqe_format[0x4];
10657 u8 reserved_4[0x1c];
10659 u8 node_guid[0x40];
10661 u8 reserved_5[0x740];
10669 u8 reserved_0[0x14];
10670 u8 vlan[0xc];
10672 u8 reserved_1[0x20];
10676 u8 reserved_0[0x20];
10678 u8 mkey[0x20];
10680 u8 addressh_63_32[0x20];
10682 u8 addressl_31_0[0x20];
10686 u8 dc_key[0x40];
10688 u8 ext[0x1];
10689 u8 reserved_0[0x7];
10690 u8 destination_qp_dct[0x18];
10692 u8 static_rate[0x4];
10693 u8 sl_eth_prio[0x4];
10694 u8 fl[0x1];
10695 u8 mlid[0x7];
10696 u8 rlid_udp_sport[0x10];
10698 u8 reserved_1[0x20];
10700 u8 rmac_47_16[0x20];
10702 u8 rmac_15_0[0x10];
10703 u8 tclass[0x8];
10704 u8 hop_limit[0x8];
10706 u8 reserved_2[0x1];
10707 u8 grh[0x1];
10708 u8 reserved_3[0x2];
10709 u8 src_addr_index[0x8];
10710 u8 flow_label[0x14];
10712 u8 rgid_rip[16][0x8];
10716 u8 reserved_0[0x8];
10717 u8 module[0x8];
10718 u8 reserved_1[0xc];
10719 u8 module_status[0x4];
10721 u8 reserved_2[0x14];
10722 u8 error_type[0x4];
10723 u8 reserved_3[0x8];
10725 u8 reserved_4[0xa0];
10729 u8 opcode[0x10];
10730 u8 status[0x8];
10731 u8 reserved_0[0x7];
10732 u8 busy[0x1];
10736 u8 reserved_0[0x8];
10737 u8 event_type[0x8];
10738 u8 reserved_1[0x8];
10739 u8 event_sub_type[0x8];
10741 u8 reserved_2[0xe0];
10745 u8 reserved_3[0x10];
10746 u8 signature[0x8];
10747 u8 reserved_4[0x7];
10748 u8 owner[0x1];
10752 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
10756 u8 type[0x8];
10757 u8 reserved_0[0x18];
10759 u8 input_length[0x20];
10761 u8 input_mailbox_pointer_63_32[0x20];
10763 u8 input_mailbox_pointer_31_9[0x17];
10764 u8 reserved_1[0x9];
10766 u8 command_input_inline_data[16][0x8];
10768 u8 command_output_inline_data[16][0x8];
10770 u8 output_mailbox_pointer_63_32[0x20];
10772 u8 output_mailbox_pointer_31_9[0x17];
10773 u8 reserved_2[0x9];
10775 u8 output_length[0x20];
10777 u8 token[0x8];
10778 u8 signature[0x8];
10779 u8 reserved_3[0x8];
10780 u8 status[0x7];
10781 u8 ownership[0x1];
10785 u8 status[0x8];
10786 u8 reserved_0[0x18];
10788 u8 syndrome[0x20];
10790 u8 command_output[0x20];
10794 u8 opcode[0x10];
10795 u8 reserved_0[0x10];
10797 u8 reserved_1[0x10];
10798 u8 op_mod[0x10];
10800 u8 command[0][0x20];
10804 u8 mailbox_data[512][0x8];
10806 u8 reserved_0[0x180];
10808 u8 next_pointer_63_32[0x20];
10810 u8 next_pointer_31_10[0x16];
10811 u8 reserved_1[0xa];
10813 u8 block_number[0x20];
10815 u8 reserved_2[0x8];
10816 u8 token[0x8];
10817 u8 ctrl_signature[0x8];
10818 u8 signature[0x8];
10822 u8 ptag_63_32[0x20];
10824 u8 ptag_31_8[0x18];
10825 u8 reserved_0[0x6];
10826 u8 wr_en[0x1];
10827 u8 rd_en[0x1];
10831 u8 valid[0x1];
10832 u8 reserved_at_1[0x7];
10833 u8 pd[0x18];
10835 u8 next_record_tcp_sn[0x20];
10837 u8 hw_resync_tcp_sn[0x20];
10839 u8 record_tracker_state[0x2];
10840 u8 auth_state[0x2];
10841 u8 reserved_at_64[0x4];
10842 u8 hw_offset_record_number[0x18];
10846 u8 const_2[0x2];
10847 u8 tls_version[0x4];
10848 u8 const_1[0x2];
10849 u8 reserved_at_8[0x14];
10850 u8 encryption_standard[0x4];
10852 u8 reserved_at_20[0x20];
10854 u8 initial_record_number[0x40];
10856 u8 resync_tcp_sn[0x20];
10858 u8 gcm_iv[0x20];
10860 u8 implicit_iv[0x40];
10862 u8 reserved_at_100[0x8];
10863 u8 dek_index[0x18];
10865 u8 reserved_at_120[0xe0];
10870 MLX5_VSC_DOMAIN_ICMD = 0x1,
10871 MLX5_VSC_DOMAIN_PROTECTED_CRSPACE = 0x6,
10872 MLX5_VSC_DOMAIN_SCAN_CRSPACE = 0x7,
10873 MLX5_VSC_DOMAIN_SEMAPHORES = 0xA,
10877 u8 type[0x8];
10878 u8 length[0x8];
10879 u8 next_pointer[0x8];
10880 u8 capability_id[0x8];
10882 u8 status[0x3];
10883 u8 reserved_0[0xd];
10884 u8 space[0x10];
10886 u8 counter[0x20];
10888 u8 semaphore[0x20];
10890 u8 flag[0x1];
10891 u8 reserved_1[0x1];
10892 u8 address[0x1e];
10894 u8 data[0x20];
10898 u8 status[0x3];
10899 u8 reserved0[0xd];
10900 u8 space[0x10];
10904 u8 flag[0x1];
10905 u8 reserved0[0x1];
10906 u8 address[0x1e];
10910 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
10911 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
10912 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
10916 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
10917 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
10918 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
10922 MLX5_HEALTH_SYNDR_FW_ERR = 0x1,
10923 MLX5_HEALTH_SYNDR_IRISC_ERR = 0x7,
10924 MLX5_HEALTH_SYNDR_HW_UNRECOVERABLE_ERR = 0x8,
10925 MLX5_HEALTH_SYNDR_CRC_ERR = 0x9,
10926 MLX5_HEALTH_SYNDR_FETCH_PCI_ERR = 0xa,
10927 MLX5_HEALTH_SYNDR_HW_FTL_ERR = 0xb,
10928 MLX5_HEALTH_SYNDR_ASYNC_EQ_OVERRUN_ERR = 0xc,
10929 MLX5_HEALTH_SYNDR_EQ_ERR = 0xd,
10930 MLX5_HEALTH_SYNDR_EQ_INV = 0xe,
10931 MLX5_HEALTH_SYNDR_FFSER_ERR = 0xf,
10932 MLX5_HEALTH_SYNDR_HIGH_TEMP = 0x10,
10936 u8 fw_rev_minor[0x10];
10937 u8 fw_rev_major[0x10];
10939 u8 cmd_interface_rev[0x10];
10940 u8 fw_rev_subminor[0x10];
10942 u8 reserved_0[0x40];
10944 u8 cmdq_phy_addr_63_32[0x20];
10946 u8 cmdq_phy_addr_31_12[0x14];
10947 u8 reserved_1[0x2];
10948 u8 nic_interface[0x2];
10949 u8 log_cmdq_size[0x4];
10950 u8 log_cmdq_stride[0x4];
10952 u8 command_doorbell_vector[0x20];
10954 u8 reserved_2[0xf00];
10956 u8 initializing[0x1];
10957 u8 reserved_3[0x4];
10958 u8 nic_interface_supported[0x3];
10959 u8 reserved_4[0x18];
10963 u8 no_dram_nic_offset[0x20];
10965 u8 reserved_5[0x6de0];
10967 u8 internal_timer_h[0x20];
10969 u8 internal_timer_l[0x20];
10971 u8 reserved_6[0x20];
10973 u8 reserved_7[0x1f];
10974 u8 clear_int[0x1];
10976 u8 health_syndrome[0x8];
10977 u8 health_counter[0x18];
10979 u8 reserved_8[0x17fc0];
10997 u8 reserved_0[0x42c0];
11011 u8 reserved_0[0x7c0];
11015 u8 swid[0x8];
11016 u8 local_port[0x8];
11017 u8 pnat[0x2];
11018 u8 reserved_0[0x8];
11019 u8 grp[0x6];
11021 u8 clr[0x1];
11022 u8 reserved_1[0x1c];
11023 u8 prio_tc[0x3];
11029 u8 life_time_counter_high[0x20];
11031 u8 life_time_counter_low[0x20];
11033 u8 error_counter_lane0[0x20];
11035 u8 error_counter_lane1[0x20];
11037 u8 error_counter_lane2[0x20];
11039 u8 error_counter_lane3[0x20];
11041 u8 error_counter_lane4[0x20];
11043 u8 error_counter_lane5[0x20];
11045 u8 error_counter_lane6[0x20];
11047 u8 error_counter_lane7[0x20];
11049 u8 error_counter_lane8[0x20];
11051 u8 error_counter_lane9[0x20];
11053 u8 error_counter_lane10[0x20];
11055 u8 error_counter_lane11[0x20];
11057 u8 error_counter_lane12[0x20];
11059 u8 error_counter_lane13[0x20];
11061 u8 error_counter_lane14[0x20];
11063 u8 error_counter_lane15[0x20];
11065 u8 reserved_at_240[0x580];
11069 u8 reserved_at_0[0x40];
11071 u8 error_counter_lane0[0x20];
11073 u8 error_counter_lane1[0x20];
11075 u8 error_counter_lane2[0x20];
11077 u8 error_counter_lane3[0x20];
11079 u8 error_counter_lane4[0x20];
11081 u8 error_counter_lane5[0x20];
11083 u8 error_counter_lane6[0x20];
11085 u8 error_counter_lane7[0x20];
11087 u8 error_counter_lane8[0x20];
11089 u8 error_counter_lane9[0x20];
11091 u8 error_counter_lane10[0x20];
11093 u8 error_counter_lane11[0x20];
11095 u8 error_counter_lane12[0x20];
11097 u8 error_counter_lane13[0x20];
11099 u8 error_counter_lane14[0x20];
11101 u8 error_counter_lane15[0x20];
11103 u8 reserved_at_240[0x580];
11107 u8 life_time_counter_high[0x20];
11109 u8 life_time_counter_low[0x20];
11111 u8 rx_errors[0x20];
11113 u8 tx_errors[0x20];
11115 u8 l0_to_recovery_eieos[0x20];
11117 u8 l0_to_recovery_ts[0x20];
11119 u8 l0_to_recovery_framing[0x20];
11121 u8 l0_to_recovery_retrain[0x20];
11123 u8 crc_error_dllp[0x20];
11125 u8 crc_error_tlp[0x20];
11127 u8 tx_overflow_buffer_pkt[0x40];
11129 u8 outbound_stalled_reads[0x20];
11131 u8 outbound_stalled_writes[0x20];
11133 u8 outbound_stalled_reads_events[0x20];
11135 u8 outbound_stalled_writes_events[0x20];
11137 u8 tx_overflow_buffer_marked_pkt[0x40];
11139 u8 reserved_at_240[0x580];
11143 u8 reserved_at_0[0x40];
11145 u8 rx_errors[0x20];
11147 u8 tx_errors[0x20];
11149 u8 reserved_at_80[0xc0];
11151 u8 tx_overflow_buffer_pkt[0x40];
11153 u8 outbound_stalled_reads[0x20];
11155 u8 outbound_stalled_writes[0x20];
11157 u8 outbound_stalled_reads_events[0x20];
11159 u8 outbound_stalled_writes_events[0x20];
11161 u8 tx_overflow_buffer_marked_pkt[0x40];
11163 u8 reserved_at_240[0x580];
11167 u8 life_time_counter_high[0x20];
11169 u8 life_time_counter_low[0x20];
11171 u8 time_to_boot_image_start[0x20];
11173 u8 time_to_link_image[0x20];
11175 u8 calibration_time[0x20];
11177 u8 time_to_first_perst[0x20];
11179 u8 time_to_detect_state[0x20];
11181 u8 time_to_l0[0x20];
11183 u8 time_to_crs_en[0x20];
11185 u8 time_to_plastic_image_start[0x20];
11187 u8 time_to_iron_image_start[0x20];
11189 u8 perst_handler[0x20];
11191 u8 times_in_l1[0x20];
11193 u8 times_in_l23[0x20];
11195 u8 dl_down[0x20];
11197 u8 config_cycle1usec[0x20];
11199 u8 config_cycle2to7usec[0x20];
11201 u8 config_cycle8to15usec[0x20];
11203 u8 config_cycle16to63usec[0x20];
11205 u8 config_cycle64usec[0x20];
11207 u8 correctable_err_msg_sent[0x20];
11209 u8 non_fatal_err_msg_sent[0x20];
11211 u8 fatal_err_msg_sent[0x20];
11213 u8 reserved_at_2e0[0x4e0];
11217 u8 reserved_at_0[0x40];
11219 u8 time_to_boot_image_start[0x20];
11221 u8 time_to_link_image[0x20];
11223 u8 calibration_time[0x20];
11225 u8 time_to_first_perst[0x20];
11227 u8 time_to_detect_state[0x20];
11229 u8 time_to_l0[0x20];
11231 u8 time_to_crs_en[0x20];
11233 u8 time_to_plastic_image_start[0x20];
11235 u8 time_to_iron_image_start[0x20];
11237 u8 perst_handler[0x20];
11239 u8 times_in_l1[0x20];
11241 u8 times_in_l23[0x20];
11243 u8 dl_down[0x20];
11245 u8 config_cycle1usec[0x20];
11247 u8 config_cycle2to7usec[0x20];
11249 u8 config_cycle8to15usec[0x20];
11251 u8 config_cycle16to63usec[0x20];
11253 u8 config_cycle64usec[0x20];
11255 u8 correctable_err_msg_sent[0x20];
11257 u8 non_fatal_err_msg_sent[0x20];
11259 u8 fatal_err_msg_sent[0x20];
11261 u8 reserved_at_2e0[0x4e0];
11268 u8 reserved_at_0[0x7c0];
11275 u8 reserved_at_0[0x7c0];
11279 u8 reserved_at_0[0x2];
11280 u8 depth[0x6];
11281 u8 pcie_index[0x8];
11282 u8 node[0x8];
11283 u8 reserved_at_18[0x2];
11284 u8 grp[0x6];
11286 u8 clr[0x1];
11287 u8 reserved_at_21[0x1f];
11293 u8 reserved_at_0[0x2];
11294 u8 depth[0x6];
11295 u8 pcie_index[0x8];
11296 u8 node[0x8];
11297 u8 reserved_at_18[0x2];
11298 u8 grp[0x6];
11300 u8 clr[0x1];
11301 u8 reserved_at_21[0x1f];
11307 u8 reserved_at_0[0x10];
11308 u8 monitor_opcode[0x10];
11313 u8 reserved_at_0[0x20];
11317 u8 reserved_at_0[0x10];
11318 u8 group_opcode[0x10];
11322 u8 user_feedback_data[0x10];
11323 u8 user_feedback_index[0x10];
11325 u8 status_message[0x760];
11331 u8 reserved_at_0[0x7c0];
11335 u8 reserved_at_0[0x8];
11336 u8 local_port[0x8];
11337 u8 pnat[0x2];
11338 u8 reserved_at_12[0xe];
11340 u8 reserved_at_20[0x18];
11341 u8 page_select[0x8];
11347 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN = 0x9050,
11348 MLX5_MPEIN_PWR_STATUS_INVALID = 0,
11354 u8 reserved_at_0[0x2];
11355 u8 depth[0x6];
11356 u8 pcie_index[0x8];
11357 u8 node[0x8];
11358 u8 reserved_at_18[0x8];
11360 u8 capability_mask[0x20];
11362 u8 reserved_at_40[0x8];
11363 u8 link_width_enabled[0x8];
11364 u8 link_speed_enabled[0x10];
11366 u8 lane0_physical_position[0x8];
11367 u8 link_width_active[0x8];
11368 u8 link_speed_active[0x10];
11370 u8 num_of_pfs[0x10];
11371 u8 num_of_vfs[0x10];
11373 u8 bdf0[0x10];
11374 u8 reserved_at_b0[0x10];
11376 u8 max_read_request_size[0x4];
11377 u8 max_payload_size[0x4];
11378 u8 reserved_at_c8[0x5];
11379 u8 pwr_status[0x3];
11380 u8 port_type[0x4];
11381 u8 reserved_at_d4[0xb];
11382 u8 lane_reversal[0x1];
11384 u8 reserved_at_e0[0x14];
11385 u8 pci_power[0xc];
11387 u8 reserved_at_100[0x20];
11389 u8 device_status[0x10];
11390 u8 port_state[0x8];
11391 u8 reserved_at_138[0x8];
11393 u8 reserved_at_140[0x10];
11394 u8 receiver_detect_result[0x10];
11396 u8 reserved_at_160[0x20];
11400 u8 reserved_at_0[0x2];
11401 u8 depth[0x6];
11402 u8 pcie_index[0x8];
11403 u8 node[0x8];
11404 u8 reserved_at_18[0x8];
11406 u8 reserved_at_20[0x20];
11408 u8 reserved_at_40[0x8];
11409 u8 link_width_enabled[0x8];
11410 u8 link_speed_enabled[0x10];
11412 u8 lane0_physical_position[0x8];
11413 u8 link_width_active[0x8];
11414 u8 link_speed_active[0x10];
11416 u8 num_of_pfs[0x10];
11417 u8 num_of_vfs[0x10];
11419 u8 bdf0[0x10];
11420 u8 reserved_at_b0[0x10];
11422 u8 max_read_request_size[0x4];
11423 u8 max_payload_size[0x4];
11424 u8 reserved_at_c8[0x5];
11425 u8 pwr_status[0x3];
11426 u8 port_type[0x4];
11427 u8 reserved_at_d4[0xb];
11428 u8 lane_reversal[0x1];
11432 u8 supported_info_bitmask[0x20];
11434 u8 component_size[0x20];
11436 u8 max_component_size[0x20];
11438 u8 log_mcda_word_size[0x4];
11439 u8 reserved_at_64[0xc];
11440 u8 mcda_max_write_size[0x10];
11442 u8 rd_en[0x1];
11443 u8 reserved_at_81[0x1];
11444 u8 match_chip_id[0x1];
11445 u8 match_psid[0x1];
11446 u8 check_user_timestamp[0x1];
11447 u8 match_base_guid_mac[0x1];
11448 u8 reserved_at_86[0x1a];
11452 u8 read_pending_component[0x1];
11453 u8 reserved_at_1[0xf];
11454 u8 component_index[0x10];
11456 u8 reserved_at_20[0x20];
11458 u8 reserved_at_40[0x1b];
11459 u8 info_type[0x5];
11461 u8 info_size[0x20];
11463 u8 offset[0x20];
11465 u8 reserved_at_a0[0x10];
11466 u8 data_size[0x10];
11468 u8 data[0][0x20];
11472 u8 reserved_at_0[0x4];
11473 u8 time_elapsed_since_last_cmd[0xc];
11474 u8 reserved_at_10[0x8];
11475 u8 instruction[0x8];
11477 u8 reserved_at_20[0x10];
11478 u8 component_index[0x10];
11480 u8 reserved_at_40[0x8];
11481 u8 update_handle[0x18];
11483 u8 handle_owner_type[0x4];
11484 u8 handle_owner_host_id[0x4];
11485 u8 reserved_at_68[0x1];
11486 u8 control_progress[0x7];
11487 u8 error_code[0x8];
11488 u8 reserved_at_78[0x4];
11489 u8 control_state[0x4];
11491 u8 component_size[0x20];
11493 u8 reserved_at_a0[0x60];
11497 u8 reserved_at_0[0x8];
11498 u8 update_handle[0x18];
11500 u8 offset[0x20];
11502 u8 reserved_at_40[0x10];
11503 u8 size[0x10];
11505 u8 reserved_at_60[0x20];
11507 u8 data[0][0x20];
11563 u8 reserved_0[0x7880];
11568 u8 reserved_0[0x200];
11580 u8 reserved_0[0x3160];
11586 u8 reserved_0[0x20120];
11590 u8 e[0x1];
11591 u8 reserved_at_01[0x0b];
11592 u8 prio[0x04];
11596 u8 reserved_at_0[0x8];
11597 u8 local_port[0x8];
11598 u8 reserved_at_10[0x10];
11603 u8 reserved_at_0[0x8];
11604 u8 local_port[0x8];
11605 u8 reserved_at_10[0x2d];
11606 u8 trust_state[0x3];
11610 u8 reserved_at_0[0x38];
11611 u8 reset_level[0x8];
11615 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP = 0x9009,
11616 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTECR = 0x9109,
11617 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP = 0x900a,
11618 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTWE = 0x900b,
11619 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTBR = 0x900f,
11620 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTEWE = 0x910b,
11625 u8 max_temperature[0x10];
11626 u8 temperature[0x10];
11630 u8 reserved_at_0[0x14];
11631 u8 base_sensor_index[0xc];
11633 u8 reserved_at_20[0x18];
11634 u8 num_rec[0x8];
11636 u8 reserved_at_40[0x40];
11642 u8 reserved_at_0[0x14];
11643 u8 base_sensor_index[0xc];
11645 u8 reserved_at_20[0x18];
11646 u8 num_rec[0x8];
11648 u8 reserved_at_40[0x40];
11654 u8 reserved_at_0[0x19];
11655 u8 sensor_count[0x7];
11657 u8 reserved_at_20[0x19];
11658 u8 internal_sensor_count[0x7];
11660 u8 sensor_map[0x40];
11664 u8 reserved_at_0[0x19];
11665 u8 sensor_count[0x7];
11667 u8 reserved_at_20[0x20];
11669 u8 sensor_map[0x40];
11673 u8 reserved_at_0[0x4];
11674 u8 last_sensor[0xc];
11675 u8 reserved_at_10[0x4];
11676 u8 sensor_count[0xc];
11678 u8 reserved_at_20[0x19];
11679 u8 internal_sensor_count[0x7];
11681 u8 sensor_map_0[0x20];
11683 u8 reserved_at_60[0x2a0];
11687 u8 reserved_at_0[0x4];
11688 u8 last_sensor[0xc];
11689 u8 reserved_at_10[0x4];
11690 u8 sensor_count[0xc];
11692 u8 reserved_at_20[0x20];
11694 u8 sensor_map_0[0x20];
11696 u8 reserved_at_60[0x2a0];
11700 u8 reserved_at_0[0x4];
11701 u8 last_sensor[0xc];
11702 u8 reserved_at_10[0x4];
11703 u8 sensor_count[0xc];
11705 u8 sensor_warning_0[0x20];
11707 u8 reserved_at_40[0x2a0];
11711 u8 reserved_at_0[0x4];
11712 u8 last_sensor[0xc];
11713 u8 reserved_at_10[0x4];
11714 u8 sensor_count[0xc];
11716 u8 sensor_warning_0[0x20];
11718 u8 reserved_at_40[0x2a0];
11722 u8 reserved_at_0[0x14];
11723 u8 sensor_index[0xc];
11725 u8 reserved_at_20[0x10];
11726 u8 temperature[0x10];
11728 u8 mte[0x1];
11729 u8 mtr[0x1];
11730 u8 reserved_at_42[0xe];
11731 u8 max_temperature[0x10];
11733 u8 tee[0x2];
11734 u8 reserved_at_62[0xe];
11735 u8 temperature_threshold_hi[0x10];
11737 u8 reserved_at_80[0x10];
11738 u8 temperature_threshold_lo[0x10];
11740 u8 reserved_at_a0[0x20];
11742 u8 sensor_name_hi[0x20];
11744 u8 sensor_name_lo[0x20];
11748 u8 reserved_at_0[0x14];
11749 u8 sensor_index[0xc];
11751 u8 reserved_at_20[0x10];
11752 u8 temperature[0x10];
11754 u8 mte[0x1];
11755 u8 mtr[0x1];
11756 u8 reserved_at_42[0xe];
11757 u8 max_temperature[0x10];
11759 u8 tee[0x2];
11760 u8 reserved_at_62[0xe];
11761 u8 temperature_threshold_hi[0x10];
11763 u8 reserved_at_80[0x10];
11764 u8 temperature_threshold_lo[0x10];
11766 u8 reserved_at_a0[0x20];
11768 u8 sensor_name_hi[0x20];
11770 u8 sensor_name_lo[0x20];
11774 u8 opcode[0x10];
11775 u8 uid[0x10];
11777 u8 vhca_tunnel_id[0x10];
11778 u8 obj_type[0x10];
11780 u8 obj_id[0x20];
11782 u8 reserved_at_60[0x20];
11786 u8 status[0x8];
11787 u8 reserved_at_8[0x18];
11789 u8 syndrome[0x20];
11791 u8 obj_id[0x20];
11793 u8 reserved_at_60[0x20];
11797 u8 reserved_at_0[0x80];
11799 u8 reserved_at_80[0x1b];
11800 u8 log_page_size[0x5];
11802 u8 page_offset[0x20];
11804 u8 num_of_mtt[0x40];
11806 struct mlx5_ifc_mtt_bits mtt[0];
11810 u8 cap[0x20];
11812 u8 reserved_at_20[0x160];
11816 u8 opcode[0x10];
11817 u8 uid[0x10];
11819 u8 reserved_at_20[0x10];
11820 u8 op_mod[0x10];
11822 u8 reserved_at_40[0x40];
11828 u8 opcode[0x10];
11829 u8 reserved_at_10[0x10];
11831 u8 reserved_at_20[0x10];
11832 u8 op_mod[0x10];
11834 u8 reserved_at_40[0x40];
11840 u8 opcode[0x10];
11841 u8 reserved_at_10[0x10];
11843 u8 reserved_at_20[0x10];
11844 u8 op_mod[0x10];
11846 u8 reserved_at_40[0x10];
11847 u8 uid[0x10];
11849 u8 reserved_at_60[0x20];
11853 u8 string_db_base_address[0x20];
11855 u8 reserved_at_20[0x8];
11856 u8 string_db_size[0x18];
11860 u8 trace_owner[0x1];
11861 u8 trace_to_memory[0x1];
11862 u8 reserved_at_2[0x4];
11863 u8 trc_ver[0x2];
11864 u8 reserved_at_8[0x14];
11865 u8 num_string_db[0x4];
11867 u8 first_string_trace[0x8];
11868 u8 num_string_trace[0x8];
11869 u8 reserved_at_30[0x28];
11871 u8 log_max_trace_buffer_size[0x8];
11873 u8 reserved_at_60[0x20];
11877 u8 reserved_at_280[0x180];
11881 u8 reserved_at_0[0x1c];
11882 u8 trace_mode[0x4];
11883 u8 reserved_at_20[0x18];
11884 u8 log_trace_buffer_size[0x8];
11885 u8 trace_mkey[0x20];
11886 u8 reserved_at_60[0x3a0];
11890 u8 string_db_index[0x4];
11891 u8 reserved_at_4[0x4];
11892 u8 read_size[0x18];
11893 u8 start_offset[0x20];
11894 u8 string_db_data[0];
11898 u8 trace_status[0x2];
11899 u8 reserved_at_2[0x2];
11900 u8 arm_event[0x1];
11901 u8 reserved_at_5[0xb];
11902 u8 modify_field_select[0x10];
11903 u8 reserved_at_20[0x2b];
11904 u8 current_timestamp52_32[0x15];
11905 u8 current_timestamp31_0[0x20];
11906 u8 reserved_at_80[0x180];
11910 u8 reserved_at_0[0x10];
11911 u8 obj_type[0x10];
11913 u8 obj_id[0x20];
11919 MLX5_FC_BULK_128 = (1 << 0),
11932 u8 ipsec_full_offload[0x1];
11933 u8 ipsec_crypto_offload[0x1];
11934 u8 ipsec_esn[0x1];
11935 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1];
11936 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1];
11937 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1];
11938 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1];
11939 u8 reserved_at_7[0x4];
11940 u8 log_max_ipsec_offload[0x5];
11941 u8 reserved_at_10[0x10];
11943 u8 min_log_ipsec_full_replay_window[0x8];
11944 u8 max_log_ipsec_full_replay_window[0x8];
11945 u8 reserved_at_30[0x7d0];
11953 MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
11954 MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
11955 MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
11956 MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
11960 MLX5_IPSEC_ASO_MODE = 0x0,
11961 MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
11962 MLX5_IPSEC_ASO_INC_SN = 0x2,
11966 MLX5_IPSEC_ASO_REPLAY_WIN_32BIT = 0x0,
11967 MLX5_IPSEC_ASO_REPLAY_WIN_64BIT = 0x1,
11968 MLX5_IPSEC_ASO_REPLAY_WIN_128BIT = 0x2,
11969 MLX5_IPSEC_ASO_REPLAY_WIN_256BIT = 0x3,
11973 u8 valid[0x1];
11974 u8 reserved_at_201[0x1];
11975 u8 mode[0x2];
11976 u8 window_sz[0x2];
11977 u8 soft_lft_arm[0x1];
11978 u8 hard_lft_arm[0x1];
11979 u8 remove_flow_enable[0x1];
11980 u8 esn_event_arm[0x1];
11981 u8 reserved_at_20a[0x16];
11983 u8 remove_flow_pkt_cnt[0x20];
11985 u8 remove_flow_soft_lft[0x20];
11987 u8 reserved_at_260[0x80];
11989 u8 mode_parameter[0x20];
11991 u8 replay_protection_window[0x100];
11995 u8 modify_field_select[0x40];
11996 u8 full_offload[0x1];
11997 u8 reserved_at_41[0x1];
11998 u8 esn_en[0x1];
11999 u8 esn_overlap[0x1];
12000 u8 reserved_at_44[0x2];
12001 u8 icv_length[0x2];
12002 u8 reserved_at_48[0x4];
12003 u8 aso_return_reg[0x4];
12004 u8 reserved_at_50[0x10];
12006 u8 esn_msb[0x20];
12008 u8 reserved_at_80[0x8];
12009 u8 dekn[0x18];
12011 u8 salt[0x20];
12013 u8 implicit_iv[0x40];
12015 u8 reserved_at_100[0x8];
12016 u8 ipsec_aso_access_pd[0x18];
12017 u8 reserved_at_120[0xe0];
12028 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = 1 << 0,
12043 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_TLS = 0x1,
12044 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_IPSEC = 0x2,
12045 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_PURPOSE_MACSEC = 0x4,