1 /*-
4  * SPDX-License-Identifier: BSD-3-Clause
13  *  igc_init_nvm_ops_generic - Initialize NVM function pointers
16  *  Setups up the function pointers to no-op functions
20 	struct igc_nvm_info *nvm = &hw->nvm;  in igc_init_nvm_ops_generic()
24 	nvm->ops.init_params = igc_null_ops_generic;  in igc_init_nvm_ops_generic()
25 	nvm->ops.acquire = igc_null_ops_generic;  in igc_init_nvm_ops_generic()
26 	nvm->ops.read = igc_null_read_nvm;  in igc_init_nvm_ops_generic()
27 	nvm->ops.release = igc_null_nvm_generic;  in igc_init_nvm_ops_generic()
28 	nvm->ops.reload = igc_reload_nvm_generic;  in igc_init_nvm_ops_generic()
29 	nvm->ops.update = igc_null_ops_generic;  in igc_init_nvm_ops_generic()
30 	nvm->ops.validate = igc_null_ops_generic;  in igc_init_nvm_ops_generic()
31 	nvm->ops.write = igc_null_write_nvm;  in igc_init_nvm_ops_generic()
35  *  igc_null_nvm_read - No-op function, return 0
50  *  igc_null_nvm_generic - No-op function, return void
60  *  igc_null_write_nvm - No-op function, return 0
75  *  igc_raise_eec_clk - Raise EEPROM clock
79  *  Enable/Raise the EEPROM clock bit.
86 	usec_delay(hw->nvm.delay_usec);  in igc_raise_eec_clk()
90  *  igc_lower_eec_clk - Lower EEPROM clock
101 	usec_delay(hw->nvm.delay_usec);  in igc_lower_eec_clk()
105  *  igc_shift_out_eec_bits - Shift data bits our to the EEPROM
108  *  @count: number of bits to shift out
110  *  We need to shift 'count' bits out to the EEPROM.  So, the value in the
116 	struct igc_nvm_info *nvm = &hw->nvm;  in igc_shift_out_eec_bits()
122 	mask = 0x01 << (count - 1);  in igc_shift_out_eec_bits()
123 	if (nvm->type == igc_nvm_eeprom_spi)  in igc_shift_out_eec_bits()
135 		usec_delay(nvm->delay_usec);  in igc_shift_out_eec_bits()
148  *  igc_shift_in_eec_bits - Shift data bits in from the EEPROM
150  *  @count: number of bits to shift in
152  *  In order to read a register from the EEPROM, we need to shift 'count' bits
188  *  igc_poll_eerd_eewr_done - Poll for EEPROM read/write completion
214 	return -IGC_ERR_NVM;  in igc_poll_eerd_eewr_done()
218  *  igc_acquire_nvm_generic - Generic request for access to EEPROM
223  *  EEPROM access and return -IGC_ERR_NVM (-1).
240 		timeout--;  in igc_acquire_nvm_generic()
247 		return -IGC_ERR_NVM;  in igc_acquire_nvm_generic()
254  *  igc_standby_nvm - Return EEPROM to standby state
261 	struct igc_nvm_info *nvm = &hw->nvm;  in igc_standby_nvm()
266 	if (nvm->type == igc_nvm_eeprom_spi) {  in igc_standby_nvm()
267 		/* Toggle CS to flush commands */  in igc_standby_nvm()
271 		usec_delay(nvm->delay_usec);  in igc_standby_nvm()
275 		usec_delay(nvm->delay_usec);  in igc_standby_nvm()
280  *  igc_stop_nvm - Terminate EEPROM command
292 	if (hw->nvm.type == igc_nvm_eeprom_spi) {  in igc_stop_nvm()
293 		/* Pull CS high */  in igc_stop_nvm()
300  *  igc_release_nvm_generic - Release exclusive access to EEPROM
319  *  igc_ready_nvm_eeprom - Prepares EEPROM for read/write
326 	struct igc_nvm_info *nvm = &hw->nvm;  in igc_ready_nvm_eeprom()
332 	if (nvm->type == igc_nvm_eeprom_spi) {  in igc_ready_nvm_eeprom()
335 		/* Clear SK and CS */  in igc_ready_nvm_eeprom()
348 						 hw->nvm.opcode_bits);  in igc_ready_nvm_eeprom()
355 			timeout--;  in igc_ready_nvm_eeprom()
360 			return -IGC_ERR_NVM;  in igc_ready_nvm_eeprom()
368  *  igc_read_nvm_eerd - Reads EEPROM using EERD register
378 	struct igc_nvm_info *nvm = &hw->nvm;  in igc_read_nvm_eerd()
387 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||  in igc_read_nvm_eerd()
390 		return -IGC_ERR_NVM;  in igc_read_nvm_eerd()
413  *  igc_write_nvm_spi - Write to EEPROM using SPI
426 	struct igc_nvm_info *nvm = &hw->nvm;  in igc_write_nvm_spi()
427 	s32 ret_val = -IGC_ERR_NVM;  in igc_write_nvm_spi()
435 	if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||  in igc_write_nvm_spi()
438 		return -IGC_ERR_NVM;  in igc_write_nvm_spi()
444 		ret_val = nvm->ops.acquire(hw);  in igc_write_nvm_spi()
450 			nvm->ops.release(hw);  in igc_write_nvm_spi()
456 		/* Send the WRITE ENABLE command (8 bit opcode) */  in igc_write_nvm_spi()
458 					 nvm->opcode_bits);  in igc_write_nvm_spi()
465 		if ((nvm->address_bits == 8) && (offset >= 128))  in igc_write_nvm_spi()
468 		/* Send the Write command (8-bit opcode + addr) */  in igc_write_nvm_spi()
469 		igc_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits);  in igc_write_nvm_spi()
471 					 nvm->address_bits);  in igc_write_nvm_spi()
480 			if ((((offset + widx) * 2) % nvm->page_size) == 0) {  in igc_write_nvm_spi()
486 		nvm->ops.release(hw);  in igc_write_nvm_spi()
493  *  igc_read_pba_string_generic - Read device part number
514 		return -IGC_ERR_INVALID_ARGUMENT;  in igc_read_pba_string_generic()
517 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data);  in igc_read_pba_string_generic()
523 	ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &pba_ptr);  in igc_read_pba_string_generic()
549 		pba_num[6] = '-';  in igc_read_pba_string_generic()
557 		/* switch all the data but the '-' to hex char */  in igc_read_pba_string_generic()
562 				pba_num[offset] += 'A' - 0xA;  in igc_read_pba_string_generic()
568 	ret_val = hw->nvm.ops.read(hw, pba_ptr, 1, &length);  in igc_read_pba_string_generic()
576 		return -IGC_ERR_NVM_PBA_SECTION;  in igc_read_pba_string_generic()
579 	if (pba_num_size < (((u32)length * 2) - 1)) {  in igc_read_pba_string_generic()
581 		return -IGC_ERR_NO_SPACE;  in igc_read_pba_string_generic()
586 	length--;  in igc_read_pba_string_generic()
589 		ret_val = hw->nvm.ops.read(hw, pba_ptr + offset, 1, &nvm_data);  in igc_read_pba_string_generic()
607  *  igc_read_mac_addr_generic - Read device MAC address
624 		hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8));  in igc_read_mac_addr_generic()
627 		hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8));  in igc_read_mac_addr_generic()
630 		hw->mac.addr[i] = hw->mac.perm_addr[i];  in igc_read_mac_addr_generic()
636  *  igc_validate_nvm_checksum_generic - Validate EEPROM checksum
651 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);  in igc_validate_nvm_checksum_generic()
661 		return -IGC_ERR_NVM;  in igc_validate_nvm_checksum_generic()
668  *  igc_update_nvm_checksum_generic - Update EEPROM checksum
684 		ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);  in igc_update_nvm_checksum_generic()
691 	checksum = (u16) NVM_SUM - checksum;  in igc_update_nvm_checksum_generic()
692 	ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum);  in igc_update_nvm_checksum_generic()
700  *  igc_reload_nvm_generic - Reloads EEPROM
720  *  igc_get_fw_version - Get firmware version information
738 	switch (hw->mac.type) {  in igc_get_fw_version()
740 		hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);  in igc_get_fw_version()
742 		hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset);  in igc_get_fw_version()
744 			hw->nvm.ops.read(hw, NVM_COMB_VER_OFF + comb_offset + 1,  in igc_get_fw_version()
746 			hw->nvm.ops.read(hw, NVM_COMB_VER_OFF + comb_offset,  in igc_get_fw_version()
753 				fw_vers->or_valid = true;  in igc_get_fw_version()
754 				fw_vers->or_major = comb_verl >>  in igc_get_fw_version()
756 				fw_vers->or_build = (comb_verl <<  in igc_get_fw_version()
760 				fw_vers->or_patch = comb_verh &  in igc_get_fw_version()
766 		hw->nvm.ops.read(hw, NVM_ETRACK_HIWORD, 1, &etrack_test);  in igc_get_fw_version()
769 	hw->nvm.ops.read(hw, NVM_VERSION, 1, &fw_version);  in igc_get_fw_version()
770 	fw_vers->eep_major = (fw_version & NVM_MAJOR_MASK)  in igc_get_fw_version()
787 	fw_vers->eep_minor = result;  in igc_get_fw_version()
790 		hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verl);  in igc_get_fw_version()
791 		hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verh);  in igc_get_fw_version()
792 		fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT)  in igc_get_fw_version()
795 		hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh);  in igc_get_fw_version()
796 		hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl);  in igc_get_fw_version()
797 		fw_vers->etrack_id = (eeprom_verh << NVM_ETRACK_SHIFT) |  in igc_get_fw_version()