160 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)  in reg_write()  function
180 		reg_write(sc, IG4_REG_INTR_MASK, val);  in ig4iic_set_intr_mask()
253 	reg_write(sc, IG4_REG_I2C_EN, ctl);  in set_controller()
353 	reg_write(sc, IG4_REG_TX_TL, 0);  in set_slave_addr()
366 	reg_write(sc, IG4_REG_CTL, ctl);  in set_slave_addr()
367 	reg_write(sc, IG4_REG_TAR_ADD, tar);  in set_slave_addr()
445 			reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT);  in ig4iic_read()
462 			reg_write(sc, IG4_REG_DATA_CMD, cmd);  in ig4iic_read()
478 				reg_write(sc, IG4_REG_RX_TL,  in ig4iic_read()
512 			reg_write(sc, IG4_REG_DATA_CMD, cmd);  in ig4iic_write()
520 			reg_write(sc, IG4_REG_TX_TL, lowat);  in ig4iic_write()
919 		reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED);  in ig4iic_set_config()
920 		reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);  in ig4iic_set_config()
926 		reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);  in ig4iic_set_config()
927 		reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);  in ig4iic_set_config()
929 		reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);  in ig4iic_set_config()
930 		reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);  in ig4iic_set_config()
946 			reg_write(sc, IG4_REG_GENERAL, v);  in ig4iic_set_config()
971 	reg_write(sc, IG4_REG_INTR_MASK, 0);  in ig4iic_set_config()
974 	reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt);  in ig4iic_set_config()
975 	reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt);  in ig4iic_set_config()
976 	reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt);  in ig4iic_set_config()
977 	reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt);  in ig4iic_set_config()
978 	reg_write(sc, IG4_REG_SDA_HOLD,  in ig4iic_set_config()
982 	reg_write(sc, IG4_REG_RX_TL, 0);  in ig4iic_set_config()
983 	reg_write(sc, IG4_REG_TX_TL, 0);  in ig4iic_set_config()
985 	reg_write(sc, IG4_REG_CTL,  in ig4iic_set_config()
1009 		reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK);  in ig4iic_get_fifo()
1012 		reg_write(sc, IG4_REG_TX_TL, v);  in ig4iic_get_fifo()
1016 		reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK);  in ig4iic_get_fifo()
1019 		reg_write(sc, IG4_REG_RX_TL, v);  in ig4iic_get_fifo()
1090 	reg_write(sc, IG4_REG_INTR_MASK, 0);  in ig4iic_detach()
1115 		reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE);  in ig4iic_suspend()
1121 		reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);  in ig4iic_suspend()