Lines Matching +full:1 +full:x

7  * 1. Redistributions of source code must retain the above copyright
36 	FW_EPERM		= 1,	/* operation not permitted */
181 #define V_FW_WR_OP(x)		((x) << S_FW_WR_OP)
182 #define G_FW_WR_OP(x)		(((x) >> S_FW_WR_OP) & M_FW_WR_OP)
188 #define V_FW_WR_ATOMIC(x)	((x) << S_FW_WR_ATOMIC)
189 #define G_FW_WR_ATOMIC(x)	\
190     (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC)
191 #define F_FW_WR_ATOMIC		V_FW_WR_ATOMIC(1U)
198 #define V_FW_WR_FLUSH(x)  ((x) << S_FW_WR_FLUSH)
199 #define G_FW_WR_FLUSH(x)  \
200     (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH)
201 #define F_FW_WR_FLUSH     V_FW_WR_FLUSH(1U)
207 #define V_FW_WR_COMPL(x)  ((x) << S_FW_WR_COMPL)
208 #define G_FW_WR_COMPL(x)  \
209     (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL)
210 #define F_FW_WR_COMPL     V_FW_WR_COMPL(1U)
217 #define V_FW_WR_IMMDLEN(x)	((x) << S_FW_WR_IMMDLEN)
218 #define G_FW_WR_IMMDLEN(x)	\
219     (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN)
225 #define V_FW_WR_EQUIQ(x)	((x) << S_FW_WR_EQUIQ)
226 #define G_FW_WR_EQUIQ(x)	(((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ)
227 #define F_FW_WR_EQUIQ		V_FW_WR_EQUIQ(1U)
233 #define V_FW_WR_EQUEQ(x)	((x) << S_FW_WR_EQUEQ)
234 #define G_FW_WR_EQUEQ(x)	(((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ)
235 #define F_FW_WR_EQUEQ		V_FW_WR_EQUEQ(1U)
241 #define V_FW_WR_FLOWID(x)	((x) << S_FW_WR_FLOWID)
242 #define G_FW_WR_FLOWID(x)	(((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID)
248 #define V_FW_WR_LEN16(x)	((x) << S_FW_WR_LEN16)
249 #define G_FW_WR_LEN16(x)	(((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16)
259 #define V_FW_FRAG_WR_EOF(x)	((x) << S_FW_FRAG_WR_EOF)
260 #define G_FW_FRAG_WR_EOF(x)	(((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF)
261 #define F_FW_FRAG_WR_EOF	V_FW_FRAG_WR_EOF(1U)
265 #define V_FW_FRAG_WR_FRAGOFF16(x)	((x) << S_FW_FRAG_WR_FRAGOFF16)
266 #define G_FW_FRAG_WR_FRAGOFF16(x)	\
267     (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16)
413 #define V_FW_FILTER_WR_TID(x)	((x) << S_FW_FILTER_WR_TID)
414 #define G_FW_FILTER_WR_TID(x)	\
415     (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID)
419 #define V_FW_FILTER_WR_RQTYPE(x)	((x) << S_FW_FILTER_WR_RQTYPE)
420 #define G_FW_FILTER_WR_RQTYPE(x)	\
421     (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE)
422 #define F_FW_FILTER_WR_RQTYPE	V_FW_FILTER_WR_RQTYPE(1U)
426 #define V_FW_FILTER_WR_NOREPLY(x)	((x) << S_FW_FILTER_WR_NOREPLY)
427 #define G_FW_FILTER_WR_NOREPLY(x)	\
428     (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY)
429 #define F_FW_FILTER_WR_NOREPLY	V_FW_FILTER_WR_NOREPLY(1U)
433 #define V_FW_FILTER_WR_IQ(x)	((x) << S_FW_FILTER_WR_IQ)
434 #define G_FW_FILTER_WR_IQ(x)	\
435     (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ)
439 #define V_FW_FILTER_WR_DEL_FILTER(x)	((x) << S_FW_FILTER_WR_DEL_FILTER)
440 #define G_FW_FILTER_WR_DEL_FILTER(x)	\
441     (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER)
442 #define F_FW_FILTER_WR_DEL_FILTER	V_FW_FILTER_WR_DEL_FILTER(1U)
446 #define V_FW_FILTER2_WR_DROP_ENCAP(x)	((x) << S_FW_FILTER2_WR_DROP_ENCAP)
447 #define G_FW_FILTER2_WR_DROP_ENCAP(x)	\
448     (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP)
449 #define F_FW_FILTER2_WR_DROP_ENCAP	V_FW_FILTER2_WR_DROP_ENCAP(1U)
453 #define V_FW_FILTER2_WR_TX_LOOP(x)      ((x) << S_FW_FILTER2_WR_TX_LOOP)
454 #define G_FW_FILTER2_WR_TX_LOOP(x)      \
455 	    (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP)
456 #define F_FW_FILTER2_WR_TX_LOOP         V_FW_FILTER2_WR_TX_LOOP(1U)
460 #define V_FW_FILTER_WR_RPTTID(x)	((x) << S_FW_FILTER_WR_RPTTID)
461 #define G_FW_FILTER_WR_RPTTID(x)	\
462     (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID)
463 #define F_FW_FILTER_WR_RPTTID	V_FW_FILTER_WR_RPTTID(1U)
467 #define V_FW_FILTER_WR_DROP(x)	((x) << S_FW_FILTER_WR_DROP)
468 #define G_FW_FILTER_WR_DROP(x)	\
469     (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP)
470 #define F_FW_FILTER_WR_DROP	V_FW_FILTER_WR_DROP(1U)
474 #define V_FW_FILTER_WR_DIRSTEER(x)	((x) << S_FW_FILTER_WR_DIRSTEER)
475 #define G_FW_FILTER_WR_DIRSTEER(x)	\
476     (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER)
477 #define F_FW_FILTER_WR_DIRSTEER	V_FW_FILTER_WR_DIRSTEER(1U)
481 #define V_FW_FILTER_WR_MASKHASH(x)	((x) << S_FW_FILTER_WR_MASKHASH)
482 #define G_FW_FILTER_WR_MASKHASH(x)	\
483     (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH)
484 #define F_FW_FILTER_WR_MASKHASH	V_FW_FILTER_WR_MASKHASH(1U)
488 #define V_FW_FILTER_WR_DIRSTEERHASH(x)	((x) << S_FW_FILTER_WR_DIRSTEERHASH)
489 #define G_FW_FILTER_WR_DIRSTEERHASH(x)	\
490     (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH)
491 #define F_FW_FILTER_WR_DIRSTEERHASH	V_FW_FILTER_WR_DIRSTEERHASH(1U)
495 #define V_FW_FILTER_WR_LPBK(x)	((x) << S_FW_FILTER_WR_LPBK)
496 #define G_FW_FILTER_WR_LPBK(x)	\
497     (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK)
498 #define F_FW_FILTER_WR_LPBK	V_FW_FILTER_WR_LPBK(1U)
502 #define V_FW_FILTER_WR_DMAC(x)	((x) << S_FW_FILTER_WR_DMAC)
503 #define G_FW_FILTER_WR_DMAC(x)	\
504     (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC)
505 #define F_FW_FILTER_WR_DMAC	V_FW_FILTER_WR_DMAC(1U)
509 #define V_FW_FILTER_WR_SMAC(x)	((x) << S_FW_FILTER_WR_SMAC)
510 #define G_FW_FILTER_WR_SMAC(x)	\
511     (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC)
512 #define F_FW_FILTER_WR_SMAC	V_FW_FILTER_WR_SMAC(1U)
516 #define V_FW_FILTER_WR_INSVLAN(x)	((x) << S_FW_FILTER_WR_INSVLAN)
517 #define G_FW_FILTER_WR_INSVLAN(x)	\
518     (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN)
519 #define F_FW_FILTER_WR_INSVLAN	V_FW_FILTER_WR_INSVLAN(1U)
523 #define V_FW_FILTER_WR_RMVLAN(x)	((x) << S_FW_FILTER_WR_RMVLAN)
524 #define G_FW_FILTER_WR_RMVLAN(x)	\
525     (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN)
526 #define F_FW_FILTER_WR_RMVLAN	V_FW_FILTER_WR_RMVLAN(1U)
530 #define V_FW_FILTER_WR_HITCNTS(x)	((x) << S_FW_FILTER_WR_HITCNTS)
531 #define G_FW_FILTER_WR_HITCNTS(x)	\
532     (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS)
533 #define F_FW_FILTER_WR_HITCNTS	V_FW_FILTER_WR_HITCNTS(1U)
537 #define V_FW_FILTER_WR_TXCHAN(x)	((x) << S_FW_FILTER_WR_TXCHAN)
538 #define G_FW_FILTER_WR_TXCHAN(x)	\
539     (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN)
543 #define V_FW_FILTER_WR_PRIO(x)	((x) << S_FW_FILTER_WR_PRIO)
544 #define G_FW_FILTER_WR_PRIO(x)	\
545     (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO)
546 #define F_FW_FILTER_WR_PRIO	V_FW_FILTER_WR_PRIO(1U)
550 #define V_FW_FILTER_WR_L2TIX(x)	((x) << S_FW_FILTER_WR_L2TIX)
551 #define G_FW_FILTER_WR_L2TIX(x)	\
552     (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX)
556 #define V_FW_FILTER_WR_FRAG(x)	((x) << S_FW_FILTER_WR_FRAG)
557 #define G_FW_FILTER_WR_FRAG(x)	\
558     (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG)
559 #define F_FW_FILTER_WR_FRAG	V_FW_FILTER_WR_FRAG(1U)
563 #define V_FW_FILTER_WR_FRAGM(x)	((x) << S_FW_FILTER_WR_FRAGM)
564 #define G_FW_FILTER_WR_FRAGM(x)	\
565     (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM)
566 #define F_FW_FILTER_WR_FRAGM	V_FW_FILTER_WR_FRAGM(1U)
570 #define V_FW_FILTER_WR_IVLAN_VLD(x)	((x) << S_FW_FILTER_WR_IVLAN_VLD)
571 #define G_FW_FILTER_WR_IVLAN_VLD(x)	\
572     (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD)
573 #define F_FW_FILTER_WR_IVLAN_VLD	V_FW_FILTER_WR_IVLAN_VLD(1U)
577 #define V_FW_FILTER_WR_OVLAN_VLD(x)	((x) << S_FW_FILTER_WR_OVLAN_VLD)
578 #define G_FW_FILTER_WR_OVLAN_VLD(x)	\
579     (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD)
580 #define F_FW_FILTER_WR_OVLAN_VLD	V_FW_FILTER_WR_OVLAN_VLD(1U)
584 #define V_FW_FILTER_WR_IVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_IVLAN_VLDM)
585 #define G_FW_FILTER_WR_IVLAN_VLDM(x)	\
586     (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM)
587 #define F_FW_FILTER_WR_IVLAN_VLDM	V_FW_FILTER_WR_IVLAN_VLDM(1U)
591 #define V_FW_FILTER_WR_OVLAN_VLDM(x)	((x) << S_FW_FILTER_WR_OVLAN_VLDM)
592 #define G_FW_FILTER_WR_OVLAN_VLDM(x)	\
593     (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM)
594 #define F_FW_FILTER_WR_OVLAN_VLDM	V_FW_FILTER_WR_OVLAN_VLDM(1U)
598 #define V_FW_FILTER_WR_RX_CHAN(x)	((x) << S_FW_FILTER_WR_RX_CHAN)
599 #define G_FW_FILTER_WR_RX_CHAN(x)	\
600     (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN)
601 #define F_FW_FILTER_WR_RX_CHAN	V_FW_FILTER_WR_RX_CHAN(1U)
605 #define V_FW_FILTER_WR_RX_RPL_IQ(x)	((x) << S_FW_FILTER_WR_RX_RPL_IQ)
606 #define G_FW_FILTER_WR_RX_RPL_IQ(x)	\
607     (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ)
609 #define S_FW_FILTER2_WR_FILTER_TYPE	1
611 #define V_FW_FILTER2_WR_FILTER_TYPE(x)	((x) << S_FW_FILTER2_WR_FILTER_TYPE)
612 #define G_FW_FILTER2_WR_FILTER_TYPE(x)	\
613     (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE)
614 #define F_FW_FILTER2_WR_FILTER_TYPE	V_FW_FILTER2_WR_FILTER_TYPE(1U)
618 #define V_FW_FILTER2_WR_SWAPMAC(x)	((x) << S_FW_FILTER2_WR_SWAPMAC)
619 #define G_FW_FILTER2_WR_SWAPMAC(x)	\
620     (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC)
621 #define F_FW_FILTER2_WR_SWAPMAC		V_FW_FILTER2_WR_SWAPMAC(1U)
625 #define V_FW_FILTER2_WR_NATMODE(x)	((x) << S_FW_FILTER2_WR_NATMODE)
626 #define G_FW_FILTER2_WR_NATMODE(x)	\
627     (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE)
631 #define V_FW_FILTER2_WR_NATFLAGCHECK(x)	((x) << S_FW_FILTER2_WR_NATFLAGCHECK)
632 #define G_FW_FILTER2_WR_NATFLAGCHECK(x)	\
633     (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK)
634 #define F_FW_FILTER2_WR_NATFLAGCHECK	V_FW_FILTER2_WR_NATFLAGCHECK(1U)
638 #define V_FW_FILTER2_WR_ULP_TYPE(x)	((x) << S_FW_FILTER2_WR_ULP_TYPE)
639 #define G_FW_FILTER2_WR_ULP_TYPE(x)	\
640     (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE)
644 #define V_FW_FILTER_WR_MACI(x)	((x) << S_FW_FILTER_WR_MACI)
645 #define G_FW_FILTER_WR_MACI(x)	\
646     (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI)
650 #define V_FW_FILTER_WR_MACIM(x)	((x) << S_FW_FILTER_WR_MACIM)
651 #define G_FW_FILTER_WR_MACIM(x)	\
652     (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM)
656 #define V_FW_FILTER_WR_FCOE(x)	((x) << S_FW_FILTER_WR_FCOE)
657 #define G_FW_FILTER_WR_FCOE(x)	\
658     (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE)
659 #define F_FW_FILTER_WR_FCOE	V_FW_FILTER_WR_FCOE(1U)
663 #define V_FW_FILTER_WR_FCOEM(x)	((x) << S_FW_FILTER_WR_FCOEM)
664 #define G_FW_FILTER_WR_FCOEM(x)	\
665     (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM)
666 #define F_FW_FILTER_WR_FCOEM	V_FW_FILTER_WR_FCOEM(1U)
670 #define V_FW_FILTER_WR_PORT(x)	((x) << S_FW_FILTER_WR_PORT)
671 #define G_FW_FILTER_WR_PORT(x)	\
672     (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT)
676 #define V_FW_FILTER_WR_PORTM(x)	((x) << S_FW_FILTER_WR_PORTM)
677 #define G_FW_FILTER_WR_PORTM(x)	\
678     (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM)
682 #define V_FW_FILTER_WR_MATCHTYPE(x)	((x) << S_FW_FILTER_WR_MATCHTYPE)
683 #define G_FW_FILTER_WR_MATCHTYPE(x)	\
684     (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE)
688 #define V_FW_FILTER_WR_MATCHTYPEM(x)	((x) << S_FW_FILTER_WR_MATCHTYPEM)
689 #define G_FW_FILTER_WR_MATCHTYPEM(x)	\
690     (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM)
694 #define V_FW_FILTER2_WR_ROCEV2(x)	((x) << S_FW_FILTER2_WR_ROCEV2)
695 #define G_FW_FILTER2_WR_ROCEV2(x)	\
696     (((x) >> S_FW_FILTER2_WR_ROCEV2) & M_FW_FILTER2_WR_ROCEV2)
697 #define F_FW_FILTER2_WR_ROCEV2	V_FW_FILTER2_WR_ROCEV2(1U)
701 #define V_FW_FILTER2_WR_QPN(x)	((x) << S_FW_FILTER2_WR_QPN)
702 #define G_FW_FILTER2_WR_QPN(x)	\
703     (((x) >> S_FW_FILTER2_WR_QPN) & M_FW_FILTER2_WR_QPN)
711 /*	flag for packet type - control packet (0), data packet (1)
715 #define V_FW_ULPTX_WR_DATA(x)	((x) << S_FW_ULPTX_WR_DATA)
716 #define G_FW_ULPTX_WR_DATA(x)	\
717     (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA)
718 #define F_FW_ULPTX_WR_DATA	V_FW_ULPTX_WR_DATA(1U)
734 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN)
735 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x)	\
736     (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN)
747 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN)
748 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x)	\
749     (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN)
753 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
754     ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE)
755 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x)	\
756     (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \
759     V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U)
763 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
764     ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE)
765 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x)	\
766     (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \
769     V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U)
773 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLAN)
774 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x)	\
775     (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN)
776 #define F_FW_ETH_TX_PKT2_WR_IVLAN	V_FW_ETH_TX_PKT2_WR_IVLAN(1U)
780 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG)
781 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x)	\
782     (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG)
786 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE)
787 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x)	\
788     (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE)
792 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN)
793 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x)	\
794     (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN)
807 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x)   ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN)
808 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x)   \
809     (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN)
888 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x)	((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
889 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x)	\
890     (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
894 #define V_FW_ETH_TX_EO_WR_TSCLK(x)	((x) << S_FW_ETH_TX_EO_WR_TSCLK)
895 #define G_FW_ETH_TX_EO_WR_TSCLK(x)	\
896     (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
900 #define V_FW_ETH_TX_EO_WR_TSOFF(x)	((x) << S_FW_ETH_TX_EO_WR_TSOFF)
901 #define G_FW_ETH_TX_EO_WR_TSOFF(x)	\
902     (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
955 #define V_FW_OFLD_CONNECTION_WR_VERSION(x)	\
956     ((x) << S_FW_OFLD_CONNECTION_WR_VERSION)
957 #define G_FW_OFLD_CONNECTION_WR_VERSION(x)	\
958     (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \
960 #define F_FW_OFLD_CONNECTION_WR_VERSION	V_FW_OFLD_CONNECTION_WR_VERSION(1U)
964 #define V_FW_OFLD_CONNECTION_WR_CPL(x)	((x) << S_FW_OFLD_CONNECTION_WR_CPL)
965 #define G_FW_OFLD_CONNECTION_WR_CPL(x)	\
966     (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL)
967 #define F_FW_OFLD_CONNECTION_WR_CPL	V_FW_OFLD_CONNECTION_WR_CPL(1U)
971 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
972     ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE)
973 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x)	\
974     (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \
979 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
980     ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE)
981 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x)	\
982     (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \
987 #define V_FW_OFLD_CONNECTION_WR_ASTID(x)	\
988     ((x) << S_FW_OFLD_CONNECTION_WR_ASTID)
989 #define G_FW_OFLD_CONNECTION_WR_ASTID(x)	\
990     (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID)
994 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
995     ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK)
996 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x)	\
997     (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \
1000     V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U)
1004 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
1005     ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL)
1006 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x)	\
1007     (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \
1010     V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U)
1014 	FW_FLOWC_MNEM_TCPSTATE_LISTEN	= 1, /* illegal */
1038 	FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
1049 	FW_FLOWC_MNEM_CH		= 1,
1086 #define V_FW_FLOWC_WR_NPARAMS(x)	((x) << S_FW_FLOWC_WR_NPARAMS)
1087 #define G_FW_FLOWC_WR_NPARAMS(x)	\
1088     (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS)
1099 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
1100     ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE)
1101 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x)	\
1102     (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \
1104 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE	V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U)
1108 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
1109     ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1110 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x)	\
1111     (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD)
1112 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD	V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U)
1116 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
1117     ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE)
1118 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x)	\
1119     (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \
1122     V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U)
1126 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x)	((x) << S_FW_OFLD_TX_DATA_WR_FLAGS)
1127 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x)	\
1128     (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS)
1134 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)	\
1135     ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1136 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x)	\
1137     (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI)
1141 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
1142     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO)
1143 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
1144     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \
1147     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U)
1151 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)	\
1152     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI)
1153 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x)	\
1154     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \
1157     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U)
1161 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
1162     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC)
1163 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
1164     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \
1167     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
1171 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
1172     ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC)
1173 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
1174     (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \
1177     V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
1181 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)	\
1182     ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1183 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x)	\
1184     (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO)
1200 #define V_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(x)	\
1201     ((x) << S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE)
1202 #define G_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(x)	\
1203     (((x) >> S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE) & \
1206     V_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(1U)
1210 #define V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(x)	\
1211     ((x) << S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD)
1212 #define G_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(x)	\
1213     (((x) >> S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD) & \
1216     V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(1U)
1220 #define V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(x)	\
1221     ((x) << S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE)
1222 #define G_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(x)	\
1223     (((x) >> S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE) & \
1226     V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(1U)
1230 #define V_FW_OFLD_TX_DATA_V2_WR_FLAGS(x)	\
1231     ((x) << S_FW_OFLD_TX_DATA_V2_WR_FLAGS)
1232 #define G_FW_OFLD_TX_DATA_V2_WR_FLAGS(x)	\
1233     (((x) >> S_FW_OFLD_TX_DATA_V2_WR_FLAGS) & M_FW_OFLD_TX_DATA_V2_WR_FLAGS)
1243 #define V_FW_CMD_WR_DMA(x)	((x) << S_FW_CMD_WR_DMA)
1244 #define G_FW_CMD_WR_DMA(x)	(((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA)
1245 #define F_FW_CMD_WR_DMA	V_FW_CMD_WR_DMA(1U)
1457 #define V_FW_RI_TPTE_VALID(x)		((x) << S_FW_RI_TPTE_VALID)
1458 #define G_FW_RI_TPTE_VALID(x)		\
1459     (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID)
1460 #define F_FW_RI_TPTE_VALID		V_FW_RI_TPTE_VALID(1U)
1464 #define V_FW_RI_TPTE_STAGKEY(x)		((x) << S_FW_RI_TPTE_STAGKEY)
1465 #define G_FW_RI_TPTE_STAGKEY(x)		\
1466     (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY)
1470 #define V_FW_RI_TPTE_STAGSTATE(x)	((x) << S_FW_RI_TPTE_STAGSTATE)
1471 #define G_FW_RI_TPTE_STAGSTATE(x)	\
1472     (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE)
1473 #define F_FW_RI_TPTE_STAGSTATE		V_FW_RI_TPTE_STAGSTATE(1U)
1477 #define V_FW_RI_TPTE_STAGTYPE(x)	((x) << S_FW_RI_TPTE_STAGTYPE)
1478 #define G_FW_RI_TPTE_STAGTYPE(x)	\
1479     (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE)
1483 #define V_FW_RI_TPTE_PDID(x)		((x) << S_FW_RI_TPTE_PDID)
1484 #define G_FW_RI_TPTE_PDID(x)		\
1485     (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID)
1489 #define V_FW_RI_TPTE_PERM(x)		((x) << S_FW_RI_TPTE_PERM)
1490 #define G_FW_RI_TPTE_PERM(x)		\
1491     (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM)
1495 #define V_FW_RI_TPTE_REMINVDIS(x)	((x) << S_FW_RI_TPTE_REMINVDIS)
1496 #define G_FW_RI_TPTE_REMINVDIS(x)	\
1497     (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS)
1498 #define F_FW_RI_TPTE_REMINVDIS		V_FW_RI_TPTE_REMINVDIS(1U)
1501 #define M_FW_RI_TPTE_ADDRTYPE		1
1502 #define V_FW_RI_TPTE_ADDRTYPE(x)	((x) << S_FW_RI_TPTE_ADDRTYPE)
1503 #define G_FW_RI_TPTE_ADDRTYPE(x)	\
1504     (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE)
1505 #define F_FW_RI_TPTE_ADDRTYPE		V_FW_RI_TPTE_ADDRTYPE(1U)
1509 #define V_FW_RI_TPTE_MWBINDEN(x)	((x) << S_FW_RI_TPTE_MWBINDEN)
1510 #define G_FW_RI_TPTE_MWBINDEN(x)	\
1511     (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN)
1512 #define F_FW_RI_TPTE_MWBINDEN		V_FW_RI_TPTE_MWBINDEN(1U)
1516 #define V_FW_RI_TPTE_PS(x)		((x) << S_FW_RI_TPTE_PS)
1517 #define G_FW_RI_TPTE_PS(x)		\
1518     (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS)
1522 #define V_FW_RI_TPTE_QPID(x)		((x) << S_FW_RI_TPTE_QPID)
1523 #define G_FW_RI_TPTE_QPID(x)		\
1524     (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID)
1528 #define V_FW_RI_TPTE_NOSNOOP(x)		((x) << S_FW_RI_TPTE_NOSNOOP)
1529 #define G_FW_RI_TPTE_NOSNOOP(x)		\
1530     (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP)
1531 #define F_FW_RI_TPTE_NOSNOOP		V_FW_RI_TPTE_NOSNOOP(1U)
1535 #define V_FW_RI_TPTE_PBLADDR(x)		((x) << S_FW_RI_TPTE_PBLADDR)
1536 #define G_FW_RI_TPTE_PBLADDR(x)		\
1537     (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR)
1541 #define V_FW_RI_TPTE_DCA(x)		((x) << S_FW_RI_TPTE_DCA)
1542 #define G_FW_RI_TPTE_DCA(x)		\
1543     (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA)
1547 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x)	\
1548     ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG)
1549 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x)	\
1550     (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG)
1583 #define V_FW_RI_CQE_QPID(x)   ((x) << S_FW_RI_CQE_QPID)
1584 #define G_FW_RI_CQE_QPID(x)   \
1585     (((x) >> S_FW_RI_CQE_QPID) &  M_FW_RI_CQE_QPID)
1589 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY)
1590 #define G_FW_RI_CQE_NOTIFY(x) \
1591     (((x) >> S_FW_RI_CQE_NOTIFY) &  M_FW_RI_CQE_NOTIFY)
1595 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS)
1596 #define G_FW_RI_CQE_STATUS(x) \
1597     (((x) >> S_FW_RI_CQE_STATUS) &  M_FW_RI_CQE_STATUS)
1602 #define V_FW_RI_CQE_RXTX(x)   ((x) << S_FW_RI_CQE_RXTX)
1603 #define G_FW_RI_CQE_RXTX(x)   \
1604     (((x) >> S_FW_RI_CQE_RXTX) &  M_FW_RI_CQE_RXTX)
1608 #define V_FW_RI_CQE_TYPE(x)   ((x) << S_FW_RI_CQE_TYPE)
1609 #define G_FW_RI_CQE_TYPE(x)   \
1610     (((x) >> S_FW_RI_CQE_TYPE) &  M_FW_RI_CQE_TYPE)
1679 #define V_FW_QP_RES_WR_TRANSPORT_TYPE(x)	\
1680     ((x) << S_FW_QP_RES_WR_TRANSPORT_TYPE)
1681 #define G_FW_QP_RES_WR_TRANSPORT_TYPE(x)	\
1682     (((x) >> S_FW_QP_RES_WR_TRANSPORT_TYPE) & M_FW_QP_RES_WR_TRANSPORT_TYPE)
1686 #define V_FW_QP_RES_WR_VFN(x)	((x) << S_FW_QP_RES_WR_VFN)
1687 #define G_FW_QP_RES_WR_VFN(x)	\
1688     (((x) >> S_FW_QP_RES_WR_VFN) & M_FW_QP_RES_WR_VFN)
1692 #define V_FW_QP_RES_WR_NRES(x)	((x) << S_FW_QP_RES_WR_NRES)
1693 #define G_FW_QP_RES_WR_NRES(x)	\
1694     (((x) >> S_FW_QP_RES_WR_NRES) & M_FW_QP_RES_WR_NRES)
1698 #define V_FW_QP_RES_WR_FETCHSZM(x)	((x) << S_FW_QP_RES_WR_FETCHSZM)
1699 #define G_FW_QP_RES_WR_FETCHSZM(x)	\
1700     (((x) >> S_FW_QP_RES_WR_FETCHSZM) & M_FW_QP_RES_WR_FETCHSZM)
1701 #define F_FW_QP_RES_WR_FETCHSZM	V_FW_QP_RES_WR_FETCHSZM(1U)
1705 #define V_FW_QP_RES_WR_STATUSPGNS(x)	((x) << S_FW_QP_RES_WR_STATUSPGNS)
1706 #define G_FW_QP_RES_WR_STATUSPGNS(x)	\
1707     (((x) >> S_FW_QP_RES_WR_STATUSPGNS) & M_FW_QP_RES_WR_STATUSPGNS)
1708 #define F_FW_QP_RES_WR_STATUSPGNS	V_FW_QP_RES_WR_STATUSPGNS(1U)
1712 #define V_FW_QP_RES_WR_STATUSPGRO(x)	((x) << S_FW_QP_RES_WR_STATUSPGRO)
1713 #define G_FW_QP_RES_WR_STATUSPGRO(x)	\
1714     (((x) >> S_FW_QP_RES_WR_STATUSPGRO) & M_FW_QP_RES_WR_STATUSPGRO)
1715 #define F_FW_QP_RES_WR_STATUSPGRO	V_FW_QP_RES_WR_STATUSPGRO(1U)
1719 #define V_FW_QP_RES_WR_FETCHNS(x)	((x) << S_FW_QP_RES_WR_FETCHNS)
1720 #define G_FW_QP_RES_WR_FETCHNS(x)	\
1721     (((x) >> S_FW_QP_RES_WR_FETCHNS) & M_FW_QP_RES_WR_FETCHNS)
1722 #define F_FW_QP_RES_WR_FETCHNS	V_FW_QP_RES_WR_FETCHNS(1U)
1726 #define V_FW_QP_RES_WR_FETCHRO(x)	((x) << S_FW_QP_RES_WR_FETCHRO)
1727 #define G_FW_QP_RES_WR_FETCHRO(x)	\
1728     (((x) >> S_FW_QP_RES_WR_FETCHRO) & M_FW_QP_RES_WR_FETCHRO)
1729 #define F_FW_QP_RES_WR_FETCHRO	V_FW_QP_RES_WR_FETCHRO(1U)
1733 #define V_FW_QP_RES_WR_HOSTFCMODE(x)	((x) << S_FW_QP_RES_WR_HOSTFCMODE)
1734 #define G_FW_QP_RES_WR_HOSTFCMODE(x)	\
1735     (((x) >> S_FW_QP_RES_WR_HOSTFCMODE) & M_FW_QP_RES_WR_HOSTFCMODE)
1739 #define V_FW_QP_RES_WR_CPRIO(x)	((x) << S_FW_QP_RES_WR_CPRIO)
1740 #define G_FW_QP_RES_WR_CPRIO(x)	\
1741     (((x) >> S_FW_QP_RES_WR_CPRIO) & M_FW_QP_RES_WR_CPRIO)
1742 #define F_FW_QP_RES_WR_CPRIO	V_FW_QP_RES_WR_CPRIO(1U)
1746 #define V_FW_QP_RES_WR_ONCHIP(x)	((x) << S_FW_QP_RES_WR_ONCHIP)
1747 #define G_FW_QP_RES_WR_ONCHIP(x)	\
1748     (((x) >> S_FW_QP_RES_WR_ONCHIP) & M_FW_QP_RES_WR_ONCHIP)
1749 #define F_FW_QP_RES_WR_ONCHIP	V_FW_QP_RES_WR_ONCHIP(1U)
1753 #define V_FW_QP_RES_WR_PCIECHN(x)	((x) << S_FW_QP_RES_WR_PCIECHN)
1754 #define G_FW_QP_RES_WR_PCIECHN(x)	\
1755     (((x) >> S_FW_QP_RES_WR_PCIECHN) & M_FW_QP_RES_WR_PCIECHN)
1759 #define V_FW_QP_RES_WR_IQID(x)	((x) << S_FW_QP_RES_WR_IQID)
1760 #define G_FW_QP_RES_WR_IQID(x)	\
1761     (((x) >> S_FW_QP_RES_WR_IQID) & M_FW_QP_RES_WR_IQID)
1765 #define V_FW_QP_RES_WR_DCAEN(x)	((x) << S_FW_QP_RES_WR_DCAEN)
1766 #define G_FW_QP_RES_WR_DCAEN(x)	\
1767     (((x) >> S_FW_QP_RES_WR_DCAEN) & M_FW_QP_RES_WR_DCAEN)
1768 #define F_FW_QP_RES_WR_DCAEN	V_FW_QP_RES_WR_DCAEN(1U)
1772 #define V_FW_QP_RES_WR_DCACPU(x)	((x) << S_FW_QP_RES_WR_DCACPU)
1773 #define G_FW_QP_RES_WR_DCACPU(x)	\
1774     (((x) >> S_FW_QP_RES_WR_DCACPU) & M_FW_QP_RES_WR_DCACPU)
1778 #define V_FW_QP_RES_WR_FBMIN(x)	((x) << S_FW_QP_RES_WR_FBMIN)
1779 #define G_FW_QP_RES_WR_FBMIN(x)	\
1780     (((x) >> S_FW_QP_RES_WR_FBMIN) & M_FW_QP_RES_WR_FBMIN)
1784 #define V_FW_QP_RES_WR_FBMAX(x)	((x) << S_FW_QP_RES_WR_FBMAX)
1785 #define G_FW_QP_RES_WR_FBMAX(x)	\
1786     (((x) >> S_FW_QP_RES_WR_FBMAX) & M_FW_QP_RES_WR_FBMAX)
1790 #define V_FW_QP_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_QP_RES_WR_CIDXFTHRESHO)
1791 #define G_FW_QP_RES_WR_CIDXFTHRESHO(x)	\
1792     (((x) >> S_FW_QP_RES_WR_CIDXFTHRESHO) & M_FW_QP_RES_WR_CIDXFTHRESHO)
1793 #define F_FW_QP_RES_WR_CIDXFTHRESHO	V_FW_QP_RES_WR_CIDXFTHRESHO(1U)
1797 #define V_FW_QP_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_QP_RES_WR_CIDXFTHRESH)
1798 #define G_FW_QP_RES_WR_CIDXFTHRESH(x)	\
1799     (((x) >> S_FW_QP_RES_WR_CIDXFTHRESH) & M_FW_QP_RES_WR_CIDXFTHRESH)
1803 #define V_FW_QP_RES_WR_EQSIZE(x)	((x) << S_FW_QP_RES_WR_EQSIZE)
1804 #define G_FW_QP_RES_WR_EQSIZE(x)	\
1805     (((x) >> S_FW_QP_RES_WR_EQSIZE) & M_FW_QP_RES_WR_EQSIZE)
1809 #define V_FW_QP_RES_WR_IQANDST(x)	((x) << S_FW_QP_RES_WR_IQANDST)
1810 #define G_FW_QP_RES_WR_IQANDST(x)	\
1811     (((x) >> S_FW_QP_RES_WR_IQANDST) & M_FW_QP_RES_WR_IQANDST)
1812 #define F_FW_QP_RES_WR_IQANDST	V_FW_QP_RES_WR_IQANDST(1U)
1816 #define V_FW_QP_RES_WR_IQANUS(x)	((x) << S_FW_QP_RES_WR_IQANUS)
1817 #define G_FW_QP_RES_WR_IQANUS(x)	\
1818     (((x) >> S_FW_QP_RES_WR_IQANUS) & M_FW_QP_RES_WR_IQANUS)
1819 #define F_FW_QP_RES_WR_IQANUS	V_FW_QP_RES_WR_IQANUS(1U)
1823 #define V_FW_QP_RES_WR_IQANUD(x)	((x) << S_FW_QP_RES_WR_IQANUD)
1824 #define G_FW_QP_RES_WR_IQANUD(x)	\
1825     (((x) >> S_FW_QP_RES_WR_IQANUD) & M_FW_QP_RES_WR_IQANUD)
1829 #define V_FW_QP_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_QP_RES_WR_IQANDSTINDEX)
1830 #define G_FW_QP_RES_WR_IQANDSTINDEX(x)	\
1831     (((x) >> S_FW_QP_RES_WR_IQANDSTINDEX) & M_FW_QP_RES_WR_IQANDSTINDEX)
1835 #define V_FW_QP_RES_WR_IQDROPRSS(x)	((x) << S_FW_QP_RES_WR_IQDROPRSS)
1836 #define G_FW_QP_RES_WR_IQDROPRSS(x)	\
1837     (((x) >> S_FW_QP_RES_WR_IQDROPRSS) & M_FW_QP_RES_WR_IQDROPRSS)
1838 #define F_FW_QP_RES_WR_IQDROPRSS	V_FW_QP_RES_WR_IQDROPRSS(1U)
1842 #define V_FW_QP_RES_WR_IQGTSMODE(x)	((x) << S_FW_QP_RES_WR_IQGTSMODE)
1843 #define G_FW_QP_RES_WR_IQGTSMODE(x)	\
1844     (((x) >> S_FW_QP_RES_WR_IQGTSMODE) & M_FW_QP_RES_WR_IQGTSMODE)
1845 #define F_FW_QP_RES_WR_IQGTSMODE	V_FW_QP_RES_WR_IQGTSMODE(1U)
1849 #define V_FW_QP_RES_WR_IQPCIECH(x)	((x) << S_FW_QP_RES_WR_IQPCIECH)
1850 #define G_FW_QP_RES_WR_IQPCIECH(x)	\
1851     (((x) >> S_FW_QP_RES_WR_IQPCIECH) & M_FW_QP_RES_WR_IQPCIECH)
1855 #define V_FW_QP_RES_WR_IQDCAEN(x)	((x) << S_FW_QP_RES_WR_IQDCAEN)
1856 #define G_FW_QP_RES_WR_IQDCAEN(x)	\
1857     (((x) >> S_FW_QP_RES_WR_IQDCAEN) & M_FW_QP_RES_WR_IQDCAEN)
1858 #define F_FW_QP_RES_WR_IQDCAEN	V_FW_QP_RES_WR_IQDCAEN(1U)
1862 #define V_FW_QP_RES_WR_IQDCACPU(x)	((x) << S_FW_QP_RES_WR_IQDCACPU)
1863 #define G_FW_QP_RES_WR_IQDCACPU(x)	\
1864     (((x) >> S_FW_QP_RES_WR_IQDCACPU) & M_FW_QP_RES_WR_IQDCACPU)
1868 #define V_FW_QP_RES_WR_IQINTCNTTHRESH(x)	\
1869     ((x) << S_FW_QP_RES_WR_IQINTCNTTHRESH)
1870 #define G_FW_QP_RES_WR_IQINTCNTTHRESH(x)	\
1871     (((x) >> S_FW_QP_RES_WR_IQINTCNTTHRESH) & M_FW_QP_RES_WR_IQINTCNTTHRESH)
1875 #define V_FW_QP_RES_WR_IQO(x)	((x) << S_FW_QP_RES_WR_IQO)
1876 #define G_FW_QP_RES_WR_IQO(x)	\
1877     (((x) >> S_FW_QP_RES_WR_IQO) & M_FW_QP_RES_WR_IQO)
1878 #define F_FW_QP_RES_WR_IQO	V_FW_QP_RES_WR_IQO(1U)
1882 #define V_FW_QP_RES_WR_IQCPRIO(x)	((x) << S_FW_QP_RES_WR_IQCPRIO)
1883 #define G_FW_QP_RES_WR_IQCPRIO(x)	\
1884     (((x) >> S_FW_QP_RES_WR_IQCPRIO) & M_FW_QP_RES_WR_IQCPRIO)
1885 #define F_FW_QP_RES_WR_IQCPRIO	V_FW_QP_RES_WR_IQCPRIO(1U)
1889 #define V_FW_QP_RES_WR_IQESIZE(x)	((x) << S_FW_QP_RES_WR_IQESIZE)
1890 #define G_FW_QP_RES_WR_IQESIZE(x)	\
1891     (((x) >> S_FW_QP_RES_WR_IQESIZE) & M_FW_QP_RES_WR_IQESIZE)
1895 #define V_FW_QP_RES_WR_IQNS(x)	((x) << S_FW_QP_RES_WR_IQNS)
1896 #define G_FW_QP_RES_WR_IQNS(x)	\
1897     (((x) >> S_FW_QP_RES_WR_IQNS) & M_FW_QP_RES_WR_IQNS)
1898 #define F_FW_QP_RES_WR_IQNS	V_FW_QP_RES_WR_IQNS(1U)
1902 #define V_FW_QP_RES_WR_IQRO(x)	((x) << S_FW_QP_RES_WR_IQRO)
1903 #define G_FW_QP_RES_WR_IQRO(x)	\
1904     (((x) >> S_FW_QP_RES_WR_IQRO) & M_FW_QP_RES_WR_IQRO)
1905 #define F_FW_QP_RES_WR_IQRO	V_FW_QP_RES_WR_IQRO(1U)
1962 #define V_FW_RI_RES_WR_TRANSPORT_TYPE(x)	\
1963     ((x) << S_FW_RI_RES_WR_TRANSPORT_TYPE)
1964 #define G_FW_RI_RES_WR_TRANSPORT_TYPE(x)	\
1965     (((x) >> S_FW_RI_RES_WR_TRANSPORT_TYPE) & M_FW_RI_RES_WR_TRANSPORT_TYPE)
1969 #define V_FW_RI_RES_WR_VFN(x)		((x) << S_FW_RI_RES_WR_VFN)
1970 #define G_FW_RI_RES_WR_VFN(x)		\
1971     (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN)
1975 #define V_FW_RI_RES_WR_NRES(x)	((x) << S_FW_RI_RES_WR_NRES)
1976 #define G_FW_RI_RES_WR_NRES(x)	\
1977     (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES)
1981 #define V_FW_RI_RES_WR_FETCHSZM(x)	((x) << S_FW_RI_RES_WR_FETCHSZM)
1982 #define G_FW_RI_RES_WR_FETCHSZM(x)	\
1983     (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM)
1984 #define F_FW_RI_RES_WR_FETCHSZM	V_FW_RI_RES_WR_FETCHSZM(1U)
1988 #define V_FW_RI_RES_WR_STATUSPGNS(x)	((x) << S_FW_RI_RES_WR_STATUSPGNS)
1989 #define G_FW_RI_RES_WR_STATUSPGNS(x)	\
1990     (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS)
1991 #define F_FW_RI_RES_WR_STATUSPGNS	V_FW_RI_RES_WR_STATUSPGNS(1U)
1995 #define V_FW_RI_RES_WR_STATUSPGRO(x)	((x) << S_FW_RI_RES_WR_STATUSPGRO)
1996 #define G_FW_RI_RES_WR_STATUSPGRO(x)	\
1997     (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO)
1998 #define F_FW_RI_RES_WR_STATUSPGRO	V_FW_RI_RES_WR_STATUSPGRO(1U)
2002 #define V_FW_RI_RES_WR_FETCHNS(x)	((x) << S_FW_RI_RES_WR_FETCHNS)
2003 #define G_FW_RI_RES_WR_FETCHNS(x)	\
2004     (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS)
2005 #define F_FW_RI_RES_WR_FETCHNS	V_FW_RI_RES_WR_FETCHNS(1U)
2009 #define V_FW_RI_RES_WR_FETCHRO(x)	((x) << S_FW_RI_RES_WR_FETCHRO)
2010 #define G_FW_RI_RES_WR_FETCHRO(x)	\
2011     (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO)
2012 #define F_FW_RI_RES_WR_FETCHRO	V_FW_RI_RES_WR_FETCHRO(1U)
2016 #define V_FW_RI_RES_WR_HOSTFCMODE(x)	((x) << S_FW_RI_RES_WR_HOSTFCMODE)
2017 #define G_FW_RI_RES_WR_HOSTFCMODE(x)	\
2018     (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE)
2022 #define V_FW_RI_RES_WR_CPRIO(x)	((x) << S_FW_RI_RES_WR_CPRIO)
2023 #define G_FW_RI_RES_WR_CPRIO(x)	\
2024     (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO)
2025 #define F_FW_RI_RES_WR_CPRIO	V_FW_RI_RES_WR_CPRIO(1U)
2029 #define V_FW_RI_RES_WR_ONCHIP(x)	((x) << S_FW_RI_RES_WR_ONCHIP)
2030 #define G_FW_RI_RES_WR_ONCHIP(x)	\
2031     (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP)
2032 #define F_FW_RI_RES_WR_ONCHIP	V_FW_RI_RES_WR_ONCHIP(1U)
2036 #define V_FW_RI_RES_WR_PCIECHN(x)	((x) << S_FW_RI_RES_WR_PCIECHN)
2037 #define G_FW_RI_RES_WR_PCIECHN(x)	\
2038     (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN)
2042 #define V_FW_RI_RES_WR_IQID(x)	((x) << S_FW_RI_RES_WR_IQID)
2043 #define G_FW_RI_RES_WR_IQID(x)	\
2044     (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID)
2048 #define V_FW_RI_RES_WR_DCAEN(x)	((x) << S_FW_RI_RES_WR_DCAEN)
2049 #define G_FW_RI_RES_WR_DCAEN(x)	\
2050     (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN)
2051 #define F_FW_RI_RES_WR_DCAEN	V_FW_RI_RES_WR_DCAEN(1U)
2055 #define V_FW_RI_RES_WR_DCACPU(x)	((x) << S_FW_RI_RES_WR_DCACPU)
2056 #define G_FW_RI_RES_WR_DCACPU(x)	\
2057     (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU)
2061 #define V_FW_RI_RES_WR_FBMIN(x)	((x) << S_FW_RI_RES_WR_FBMIN)
2062 #define G_FW_RI_RES_WR_FBMIN(x)	\
2063     (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN)
2067 #define V_FW_RI_RES_WR_FBMAX(x)	((x) << S_FW_RI_RES_WR_FBMAX)
2068 #define G_FW_RI_RES_WR_FBMAX(x)	\
2069     (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX)
2073 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESHO)
2074 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x)	\
2075     (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO)
2076 #define F_FW_RI_RES_WR_CIDXFTHRESHO	V_FW_RI_RES_WR_CIDXFTHRESHO(1U)
2080 #define V_FW_RI_RES_WR_CIDXFTHRESH(x)	((x) << S_FW_RI_RES_WR_CIDXFTHRESH)
2081 #define G_FW_RI_RES_WR_CIDXFTHRESH(x)	\
2082     (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH)
2086 #define V_FW_RI_RES_WR_EQSIZE(x)	((x) << S_FW_RI_RES_WR_EQSIZE)
2087 #define G_FW_RI_RES_WR_EQSIZE(x)	\
2088     (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE)
2092 #define V_FW_RI_RES_WR_IQANDST(x)	((x) << S_FW_RI_RES_WR_IQANDST)
2093 #define G_FW_RI_RES_WR_IQANDST(x)	\
2094     (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST)
2095 #define F_FW_RI_RES_WR_IQANDST	V_FW_RI_RES_WR_IQANDST(1U)
2099 #define V_FW_RI_RES_WR_IQANUS(x)	((x) << S_FW_RI_RES_WR_IQANUS)
2100 #define G_FW_RI_RES_WR_IQANUS(x)	\
2101     (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS)
2102 #define F_FW_RI_RES_WR_IQANUS	V_FW_RI_RES_WR_IQANUS(1U)
2106 #define V_FW_RI_RES_WR_IQANUD(x)	((x) << S_FW_RI_RES_WR_IQANUD)
2107 #define G_FW_RI_RES_WR_IQANUD(x)	\
2108     (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD)
2112 #define V_FW_RI_RES_WR_IQANDSTINDEX(x)	((x) << S_FW_RI_RES_WR_IQANDSTINDEX)
2113 #define G_FW_RI_RES_WR_IQANDSTINDEX(x)	\
2114     (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX)
2118 #define V_FW_RI_RES_WR_IQDROPRSS(x)	((x) << S_FW_RI_RES_WR_IQDROPRSS)
2119 #define G_FW_RI_RES_WR_IQDROPRSS(x)	\
2120     (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS)
2121 #define F_FW_RI_RES_WR_IQDROPRSS	V_FW_RI_RES_WR_IQDROPRSS(1U)
2125 #define V_FW_RI_RES_WR_IQGTSMODE(x)	((x) << S_FW_RI_RES_WR_IQGTSMODE)
2126 #define G_FW_RI_RES_WR_IQGTSMODE(x)	\
2127     (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE)
2128 #define F_FW_RI_RES_WR_IQGTSMODE	V_FW_RI_RES_WR_IQGTSMODE(1U)
2132 #define V_FW_RI_RES_WR_IQPCIECH(x)	((x) << S_FW_RI_RES_WR_IQPCIECH)
2133 #define G_FW_RI_RES_WR_IQPCIECH(x)	\
2134     (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH)
2138 #define V_FW_RI_RES_WR_IQDCAEN(x)	((x) << S_FW_RI_RES_WR_IQDCAEN)
2139 #define G_FW_RI_RES_WR_IQDCAEN(x)	\
2140     (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN)
2141 #define F_FW_RI_RES_WR_IQDCAEN	V_FW_RI_RES_WR_IQDCAEN(1U)
2145 #define V_FW_RI_RES_WR_IQDCACPU(x)	((x) << S_FW_RI_RES_WR_IQDCACPU)
2146 #define G_FW_RI_RES_WR_IQDCACPU(x)	\
2147     (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU)
2151 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
2152     ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH)
2153 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x)	\
2154     (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH)
2158 #define V_FW_RI_RES_WR_IQO(x)	((x) << S_FW_RI_RES_WR_IQO)
2159 #define G_FW_RI_RES_WR_IQO(x)	\
2160     (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO)
2161 #define F_FW_RI_RES_WR_IQO	V_FW_RI_RES_WR_IQO(1U)
2165 #define V_FW_RI_RES_WR_IQCPRIO(x)	((x) << S_FW_RI_RES_WR_IQCPRIO)
2166 #define G_FW_RI_RES_WR_IQCPRIO(x)	\
2167     (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO)
2168 #define F_FW_RI_RES_WR_IQCPRIO	V_FW_RI_RES_WR_IQCPRIO(1U)
2172 #define V_FW_RI_RES_WR_IQESIZE(x)	((x) << S_FW_RI_RES_WR_IQESIZE)
2173 #define G_FW_RI_RES_WR_IQESIZE(x)	\
2174     (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE)
2178 #define V_FW_RI_RES_WR_IQNS(x)	((x) << S_FW_RI_RES_WR_IQNS)
2179 #define G_FW_RI_RES_WR_IQNS(x)	\
2180     (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS)
2181 #define F_FW_RI_RES_WR_IQNS	V_FW_RI_RES_WR_IQNS(1U)
2185 #define V_FW_RI_RES_WR_IQRO(x)	((x) << S_FW_RI_RES_WR_IQRO)
2186 #define G_FW_RI_RES_WR_IQRO(x)	\
2187     (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO)
2188 #define F_FW_RI_RES_WR_IQRO	V_FW_RI_RES_WR_IQRO(1U)
2229 #define V_FW_RI_SEND_WR_SENDOP(x)	((x) << S_FW_RI_SEND_WR_SENDOP)
2230 #define G_FW_RI_SEND_WR_SENDOP(x)	\
2231     (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP)
2310 #define V_FW_RI_BIND_MW_WR_QPBINDE(x)	((x) << S_FW_RI_BIND_MW_WR_QPBINDE)
2311 #define G_FW_RI_BIND_MW_WR_QPBINDE(x)	\
2312     (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE)
2313 #define F_FW_RI_BIND_MW_WR_QPBINDE	V_FW_RI_BIND_MW_WR_QPBINDE(1U)
2317 #define V_FW_RI_BIND_MW_WR_NS(x)	((x) << S_FW_RI_BIND_MW_WR_NS)
2318 #define G_FW_RI_BIND_MW_WR_NS(x)	\
2319     (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS)
2320 #define F_FW_RI_BIND_MW_WR_NS	V_FW_RI_BIND_MW_WR_NS(1U)
2324 #define V_FW_RI_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_BIND_MW_WR_DCACPU)
2325 #define G_FW_RI_BIND_MW_WR_DCACPU(x)	\
2326     (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU)
2347 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x)	((x) << S_FW_RI_FR_NSMR_WR_QPBINDE)
2348 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x)	\
2349     (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE)
2350 #define F_FW_RI_FR_NSMR_WR_QPBINDE	V_FW_RI_FR_NSMR_WR_QPBINDE(1U)
2354 #define V_FW_RI_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_FR_NSMR_WR_NS)
2355 #define G_FW_RI_FR_NSMR_WR_NS(x)	\
2356     (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS)
2357 #define F_FW_RI_FR_NSMR_WR_NS	V_FW_RI_FR_NSMR_WR_NS(1U)
2361 #define V_FW_RI_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_FR_NSMR_WR_DCACPU)
2362 #define G_FW_RI_FR_NSMR_WR_DCACPU(x)	\
2363     (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU)
2405 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
2406     ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP)
2407 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x)	\
2408     (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \
2443 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x)	((x) << S_FW_RI_ATOMIC_WR_ATOMICOP)
2444 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x)	\
2445     (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP)
2449 #define V_FW_RI_ATOMIC_WR_AOPCODE(x)	((x) << S_FW_RI_ATOMIC_WR_AOPCODE)
2450 #define G_FW_RI_ATOMIC_WR_AOPCODE(x)	\
2451     (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE)
2470 	FW_RI_INIT_RQEQID_SRQ			= 1 << 31,
2475 	FW_NVMET_ULPSUBMODE_DCRC		= 0x1<<1,
2579 #define V_FW_RI_WR_TRANSPORT_TYPE(x)	((x) << S_FW_RI_WR_TRANSPORT_TYPE)
2580 #define G_FW_RI_WR_TRANSPORT_TYPE(x)	\
2581     (((x) >> S_FW_RI_WR_TRANSPORT_TYPE) & M_FW_RI_WR_TRANSPORT_TYPE)
2585 #define V_FW_RI_WR_MPAREQBIT(x)	((x) << S_FW_RI_WR_MPAREQBIT)
2586 #define G_FW_RI_WR_MPAREQBIT(x)	\
2587     (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT)
2588 #define F_FW_RI_WR_MPAREQBIT	V_FW_RI_WR_MPAREQBIT(1U)
2592 #define V_FW_RI_WR_0BRRBIT(x)	((x) << S_FW_RI_WR_0BRRBIT)
2593 #define G_FW_RI_WR_0BRRBIT(x)	\
2594     (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT)
2595 #define F_FW_RI_WR_0BRRBIT	V_FW_RI_WR_0BRRBIT(1U)
2599 #define V_FW_RI_WR_P2PTYPE(x)	((x) << S_FW_RI_WR_P2PTYPE)
2600 #define G_FW_RI_WR_P2PTYPE(x)	\
2601     (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE)
2605 #define V_FW_RI_WR_PSN(x)	((x) << S_FW_RI_WR_PSN)
2606 #define G_FW_RI_WR_PSN(x)	(((x) >> S_FW_RI_WR_PSN) & M_FW_RI_WR_PSN)
2610 #define V_FW_RI_WR_EPSN(x)	((x) << S_FW_RI_WR_EPSN)
2611 #define G_FW_RI_WR_EPSN(x)	(((x) >> S_FW_RI_WR_EPSN) & M_FW_RI_WR_EPSN)
2615 #define V_FW_RI_WR_NVMT_PDA(x)	((x) << S_FW_RI_WR_NVMT_PDA)
2616 #define G_FW_RI_WR_NVMT_PDA(x)	\
2617     (((x) >> S_FW_RI_WR_NVMT_PDA) & M_FW_RI_WR_NVMT_PDA)
2619 #define S_FW_RI_WR_CMP_IMM_SZ		1
2621 #define V_FW_RI_WR_CMP_IMM_SZ(x)	((x) << S_FW_RI_WR_CMP_IMM_SZ)
2622 #define G_FW_RI_WR_CMP_IMM_SZ(x)	\
2623     (((x) >> S_FW_RI_WR_CMP_IMM_SZ) & M_FW_RI_WR_CMP_IMM_SZ)
2627 #define V_FW_RI_WR_TPT_OFFSET(x)	((x) << S_FW_RI_WR_TPT_OFFSET)
2628 #define G_FW_RI_WR_TPT_OFFSET(x)	\
2629     (((x) >> S_FW_RI_WR_TPT_OFFSET) & M_FW_RI_WR_TPT_OFFSET)
2633 #define V_FW_RI_WR_T10_CONFIG(x)	((x) << S_FW_RI_WR_T10_CONFIG)
2634 #define G_FW_RI_WR_T10_CONFIG(x)	\
2635     (((x) >> S_FW_RI_WR_T10_CONFIG) & M_FW_RI_WR_T10_CONFIG)
2723 #define V_FW_RI_V2_RDMA_WRITE_WR_PSN(x)	((x) << S_FW_RI_V2_RDMA_WRITE_WR_PSN)
2724 #define G_FW_RI_V2_RDMA_WRITE_WR_PSN(x)	\
2725     (((x) >> S_FW_RI_V2_RDMA_WRITE_WR_PSN) & M_FW_RI_V2_RDMA_WRITE_WR_PSN)
2752 #define V_FW_RI_V2_SEND_WR_SENDOP(x)	((x) << S_FW_RI_V2_SEND_WR_SENDOP)
2753 #define G_FW_RI_V2_SEND_WR_SENDOP(x)	\
2754     (((x) >> S_FW_RI_V2_SEND_WR_SENDOP) & M_FW_RI_V2_SEND_WR_SENDOP)
2758 #define V_FW_RI_V2_SEND_WR_PSN(x)	((x) << S_FW_RI_V2_SEND_WR_PSN)
2759 #define G_FW_RI_V2_SEND_WR_PSN(x)	\
2760     (((x) >> S_FW_RI_V2_SEND_WR_PSN) & M_FW_RI_V2_SEND_WR_PSN)
2773 	struct fw_ri_isgl isgl_sink; /* RRQ, max 4 nsge in rocev2, 1 in iwarp */
2778 #define V_FW_RI_V2_RDMA_READ_WR_PSN(x)	((x) << S_FW_RI_V2_RDMA_READ_WR_PSN)
2779 #define G_FW_RI_V2_RDMA_READ_WR_PSN(x)	\
2780     (((x) >> S_FW_RI_V2_RDMA_READ_WR_PSN) & M_FW_RI_V2_RDMA_READ_WR_PSN)
2794 #define V_FW_RI_V2_ATOMIC_WR_ATOMICOP(x)	\
2795     ((x) << S_FW_RI_V2_ATOMIC_WR_ATOMICOP)
2796 #define G_FW_RI_V2_ATOMIC_WR_ATOMICOP(x)	\
2797     (((x) >> S_FW_RI_V2_ATOMIC_WR_ATOMICOP) & M_FW_RI_V2_ATOMIC_WR_ATOMICOP)
2801 #define V_FW_RI_V2_ATOMIC_WR_PSN(x)	((x) << S_FW_RI_V2_ATOMIC_WR_PSN)
2802 #define G_FW_RI_V2_ATOMIC_WR_PSN(x)	\
2803     (((x) >> S_FW_RI_V2_ATOMIC_WR_PSN) & M_FW_RI_V2_ATOMIC_WR_PSN)
2829 #define V_FW_RI_V2_BIND_MW_WR_QPBINDE(x)	\
2830     ((x) << S_FW_RI_V2_BIND_MW_WR_QPBINDE)
2831 #define G_FW_RI_V2_BIND_MW_WR_QPBINDE(x)	\
2832     (((x) >> S_FW_RI_V2_BIND_MW_WR_QPBINDE) & M_FW_RI_V2_BIND_MW_WR_QPBINDE)
2833 #define F_FW_RI_V2_BIND_MW_WR_QPBINDE	V_FW_RI_V2_BIND_MW_WR_QPBINDE(1U)
2837 #define V_FW_RI_V2_BIND_MW_WR_NS(x)	((x) << S_FW_RI_V2_BIND_MW_WR_NS)
2838 #define G_FW_RI_V2_BIND_MW_WR_NS(x)	\
2839     (((x) >> S_FW_RI_V2_BIND_MW_WR_NS) & M_FW_RI_V2_BIND_MW_WR_NS)
2840 #define F_FW_RI_V2_BIND_MW_WR_NS	V_FW_RI_V2_BIND_MW_WR_NS(1U)
2844 #define V_FW_RI_V2_BIND_MW_WR_DCACPU(x)	((x) << S_FW_RI_V2_BIND_MW_WR_DCACPU)
2845 #define G_FW_RI_V2_BIND_MW_WR_DCACPU(x)	\
2846     (((x) >> S_FW_RI_V2_BIND_MW_WR_DCACPU) & M_FW_RI_V2_BIND_MW_WR_DCACPU)
2870 #define V_FW_RI_V2_FR_NSMR_WR_QPBINDE(x)	\
2871     ((x) << S_FW_RI_V2_FR_NSMR_WR_QPBINDE)
2872 #define G_FW_RI_V2_FR_NSMR_WR_QPBINDE(x)	\
2873     (((x) >> S_FW_RI_V2_FR_NSMR_WR_QPBINDE) & M_FW_RI_V2_FR_NSMR_WR_QPBINDE)
2874 #define F_FW_RI_V2_FR_NSMR_WR_QPBINDE	V_FW_RI_V2_FR_NSMR_WR_QPBINDE(1U)
2878 #define V_FW_RI_V2_FR_NSMR_WR_NS(x)	((x) << S_FW_RI_V2_FR_NSMR_WR_NS)
2879 #define G_FW_RI_V2_FR_NSMR_WR_NS(x)	\
2880     (((x) >> S_FW_RI_V2_FR_NSMR_WR_NS) & M_FW_RI_V2_FR_NSMR_WR_NS)
2881 #define F_FW_RI_V2_FR_NSMR_WR_NS	V_FW_RI_V2_FR_NSMR_WR_NS(1U)
2885 #define V_FW_RI_V2_FR_NSMR_WR_DCACPU(x)	((x) << S_FW_RI_V2_FR_NSMR_WR_DCACPU)
2886 #define G_FW_RI_V2_FR_NSMR_WR_DCACPU(x)	\
2887     (((x) >> S_FW_RI_V2_FR_NSMR_WR_DCACPU) & M_FW_RI_V2_FR_NSMR_WR_DCACPU)
2910 #define V_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(x)	\
2911     ((x) << S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL)
2912 #define G_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(x)	\
2913     (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL) & \
2916     V_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(1U)
2920 #define V_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(x)	\
2921     ((x) << S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM)
2922 #define G_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(x)	\
2923     (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM) & \
2926     V_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(1U)
2930 #define V_FW_NVMET_V2_FR_NSMR_WR_WRID(x)	\
2931     ((x) << S_FW_NVMET_V2_FR_NSMR_WR_WRID)
2932 #define G_FW_NVMET_V2_FR_NSMR_WR_WRID(x)	\
2933     (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_WRID) & M_FW_NVMET_V2_FR_NSMR_WR_WRID)
2956 #define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x)	\
2957     ((x) << S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI)
2958 #define G_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x)	\
2959     (((x) >> S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI) & \
2964 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
2965     ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO)
2966 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(x)	\
2967     (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO) & \
2970     V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(1U)
2974 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(x)	\
2975     ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI)
2976 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(x)	\
2977     (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI) & \
2980     V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(1U)
2984 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
2985     ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC)
2986 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(x)	\
2987     (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC) & \
2990     V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(1U)
2994 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
2995     ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC)
2996 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(x)	\
2997     (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC) & \
3000     V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(1U)
3004 #define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO(x)	\
3005     ((x) << S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO)
3006 #define G_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO(x)	\
3007     (((x) >> S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO) & \
3112 #define S_FW_CHNET_IFCONF_WR_PING_MACBIT	1
3114 #define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x)	\
3115     ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT)
3116 #define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x)	\
3117     (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \
3120     V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U)
3124 #define V_FW_CHNET_IFCONF_WR_FIN_BIT(x)	((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT)
3125 #define G_FW_CHNET_IFCONF_WR_FIN_BIT(x)	\
3126     (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT)
3127 #define F_FW_CHNET_IFCONF_WR_FIN_BIT	V_FW_CHNET_IFCONF_WR_FIN_BIT(1U)
3159 	FW_FOISCSI_WR_SUBOP_ADD = 1,
3165 	FW_COISCSI_WR_SUBOP_TOT = 1,
3173 	FW_FOISCSI_CTRL_STATE_ONLINE = 1,
3238 #define V_FW_RDEV_WR_IMMDLEN(x)	((x) << S_FW_RDEV_WR_IMMDLEN)
3239 #define G_FW_RDEV_WR_IMMDLEN(x)	\
3240     (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN)
3244 #define V_FW_RDEV_WR_ALLOC(x)	((x) << S_FW_RDEV_WR_ALLOC)
3245 #define G_FW_RDEV_WR_ALLOC(x)	\
3246     (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC)
3247 #define F_FW_RDEV_WR_ALLOC	V_FW_RDEV_WR_ALLOC(1U)
3251 #define V_FW_RDEV_WR_FREE(x)	((x) << S_FW_RDEV_WR_FREE)
3252 #define G_FW_RDEV_WR_FREE(x)	\
3253     (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE)
3254 #define F_FW_RDEV_WR_FREE	V_FW_RDEV_WR_FREE(1U)
3258 #define V_FW_RDEV_WR_MODIFY(x)	((x) << S_FW_RDEV_WR_MODIFY)
3259 #define G_FW_RDEV_WR_MODIFY(x)	\
3260     (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY)
3261 #define F_FW_RDEV_WR_MODIFY	V_FW_RDEV_WR_MODIFY(1U)
3265 #define V_FW_RDEV_WR_FLOWID(x)	((x) << S_FW_RDEV_WR_FLOWID)
3266 #define G_FW_RDEV_WR_FLOWID(x)	\
3267     (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID)
3271 #define V_FW_RDEV_WR_LEN16(x)	((x) << S_FW_RDEV_WR_LEN16)
3272 #define G_FW_RDEV_WR_LEN16(x)	\
3273     (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16)
3277 #define V_FW_RDEV_WR_FLAGS(x)	((x) << S_FW_RDEV_WR_FLAGS)
3278 #define G_FW_RDEV_WR_FLAGS(x)	\
3279     (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS)
3283 #define V_FW_RDEV_WR_GET_NEXT(x)	((x) << S_FW_RDEV_WR_GET_NEXT)
3284 #define G_FW_RDEV_WR_GET_NEXT(x)	\
3285     (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT)
3289 #define V_FW_RDEV_WR_ASSOC_FLOWID(x)	((x) << S_FW_RDEV_WR_ASSOC_FLOWID)
3290 #define G_FW_RDEV_WR_ASSOC_FLOWID(x)	\
3291     (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID)
3295 #define V_FW_RDEV_WR_RJT(x)	((x) << S_FW_RDEV_WR_RJT)
3296 #define G_FW_RDEV_WR_RJT(x)	(((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT)
3297 #define F_FW_RDEV_WR_RJT	V_FW_RDEV_WR_RJT(1U)
3301 #define V_FW_RDEV_WR_REASON(x)	((x) << S_FW_RDEV_WR_REASON)
3302 #define G_FW_RDEV_WR_REASON(x)	\
3303     (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON)
3307 #define V_FW_RDEV_WR_RD_XFER_RDY(x)	((x) << S_FW_RDEV_WR_RD_XFER_RDY)
3308 #define G_FW_RDEV_WR_RD_XFER_RDY(x)	\
3309     (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY)
3310 #define F_FW_RDEV_WR_RD_XFER_RDY	V_FW_RDEV_WR_RD_XFER_RDY(1U)
3314 #define V_FW_RDEV_WR_WR_XFER_RDY(x)	((x) << S_FW_RDEV_WR_WR_XFER_RDY)
3315 #define G_FW_RDEV_WR_WR_XFER_RDY(x)	\
3316     (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY)
3317 #define F_FW_RDEV_WR_WR_XFER_RDY	V_FW_RDEV_WR_WR_XFER_RDY(1U)
3321 #define V_FW_RDEV_WR_FC_SP(x)	((x) << S_FW_RDEV_WR_FC_SP)
3322 #define G_FW_RDEV_WR_FC_SP(x)	\
3323     (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP)
3324 #define F_FW_RDEV_WR_FC_SP	V_FW_RDEV_WR_FC_SP(1U)
3328 #define V_FW_RDEV_WR_RPORT_TYPE(x)	((x) << S_FW_RDEV_WR_RPORT_TYPE)
3329 #define G_FW_RDEV_WR_RPORT_TYPE(x)	\
3330     (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE)
3334 #define V_FW_RDEV_WR_VFT(x)	((x) << S_FW_RDEV_WR_VFT)
3335 #define G_FW_RDEV_WR_VFT(x)	(((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT)
3336 #define F_FW_RDEV_WR_VFT	V_FW_RDEV_WR_VFT(1U)
3340 #define V_FW_RDEV_WR_NPIV(x)	((x) << S_FW_RDEV_WR_NPIV)
3341 #define G_FW_RDEV_WR_NPIV(x)	\
3342     (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV)
3343 #define F_FW_RDEV_WR_NPIV	V_FW_RDEV_WR_NPIV(1U)
3347 #define V_FW_RDEV_WR_CLASS(x)	((x) << S_FW_RDEV_WR_CLASS)
3348 #define G_FW_RDEV_WR_CLASS(x)	\
3349     (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS)
3353 #define V_FW_RDEV_WR_SEQ_DEL(x)	((x) << S_FW_RDEV_WR_SEQ_DEL)
3354 #define G_FW_RDEV_WR_SEQ_DEL(x)	\
3355     (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL)
3356 #define F_FW_RDEV_WR_SEQ_DEL	V_FW_RDEV_WR_SEQ_DEL(1U)
3360 #define V_FW_RDEV_WR_PRIO_PREEMP(x)	((x) << S_FW_RDEV_WR_PRIO_PREEMP)
3361 #define G_FW_RDEV_WR_PRIO_PREEMP(x)	\
3362     (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP)
3363 #define F_FW_RDEV_WR_PRIO_PREEMP	V_FW_RDEV_WR_PRIO_PREEMP(1U)
3365 #define S_FW_RDEV_WR_PREF	1
3367 #define V_FW_RDEV_WR_PREF(x)	((x) << S_FW_RDEV_WR_PREF)
3368 #define G_FW_RDEV_WR_PREF(x)	\
3369     (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF)
3370 #define F_FW_RDEV_WR_PREF	V_FW_RDEV_WR_PREF(1U)
3374 #define V_FW_RDEV_WR_QOS(x)	((x) << S_FW_RDEV_WR_QOS)
3375 #define G_FW_RDEV_WR_QOS(x)	(((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS)
3376 #define F_FW_RDEV_WR_QOS	V_FW_RDEV_WR_QOS(1U)
3380 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC)
3381 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x)	\
3382     (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC)
3383 #define F_FW_RDEV_WR_ORG_PROC_ASSOC	V_FW_RDEV_WR_ORG_PROC_ASSOC(1U)
3387 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x)	((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC)
3388 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x)	\
3389     (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC)
3390 #define F_FW_RDEV_WR_RSP_PROC_ASSOC	V_FW_RDEV_WR_RSP_PROC_ASSOC(1U)
3394 #define V_FW_RDEV_WR_IMAGE_PAIR(x)	((x) << S_FW_RDEV_WR_IMAGE_PAIR)
3395 #define G_FW_RDEV_WR_IMAGE_PAIR(x)	\
3396     (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR)
3397 #define F_FW_RDEV_WR_IMAGE_PAIR	V_FW_RDEV_WR_IMAGE_PAIR(1U)
3401 #define V_FW_RDEV_WR_ACC_RSP_CODE(x)	((x) << S_FW_RDEV_WR_ACC_RSP_CODE)
3402 #define G_FW_RDEV_WR_ACC_RSP_CODE(x)	\
3403     (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE)
3407 #define V_FW_RDEV_WR_ENH_DISC(x)	((x) << S_FW_RDEV_WR_ENH_DISC)
3408 #define G_FW_RDEV_WR_ENH_DISC(x)	\
3409     (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC)
3410 #define F_FW_RDEV_WR_ENH_DISC	V_FW_RDEV_WR_ENH_DISC(1U)
3414 #define V_FW_RDEV_WR_REC(x)	((x) << S_FW_RDEV_WR_REC)
3415 #define G_FW_RDEV_WR_REC(x)	(((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC)
3416 #define F_FW_RDEV_WR_REC	V_FW_RDEV_WR_REC(1U)
3420 #define V_FW_RDEV_WR_TASK_RETRY_ID(x)	((x) << S_FW_RDEV_WR_TASK_RETRY_ID)
3421 #define G_FW_RDEV_WR_TASK_RETRY_ID(x)	\
3422     (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID)
3423 #define F_FW_RDEV_WR_TASK_RETRY_ID	V_FW_RDEV_WR_TASK_RETRY_ID(1U)
3427 #define V_FW_RDEV_WR_RETRY(x)	((x) << S_FW_RDEV_WR_RETRY)
3428 #define G_FW_RDEV_WR_RETRY(x)	\
3429     (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY)
3430 #define F_FW_RDEV_WR_RETRY	V_FW_RDEV_WR_RETRY(1U)
3434 #define V_FW_RDEV_WR_CONF_CMPL(x)	((x) << S_FW_RDEV_WR_CONF_CMPL)
3435 #define G_FW_RDEV_WR_CONF_CMPL(x)	\
3436     (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL)
3437 #define F_FW_RDEV_WR_CONF_CMPL	V_FW_RDEV_WR_CONF_CMPL(1U)
3441 #define V_FW_RDEV_WR_DATA_OVLY(x)	((x) << S_FW_RDEV_WR_DATA_OVLY)
3442 #define G_FW_RDEV_WR_DATA_OVLY(x)	\
3443     (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY)
3444 #define F_FW_RDEV_WR_DATA_OVLY	V_FW_RDEV_WR_DATA_OVLY(1U)
3446 #define S_FW_RDEV_WR_INI	1
3448 #define V_FW_RDEV_WR_INI(x)	((x) << S_FW_RDEV_WR_INI)
3449 #define G_FW_RDEV_WR_INI(x)	(((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI)
3450 #define F_FW_RDEV_WR_INI	V_FW_RDEV_WR_INI(1U)
3454 #define V_FW_RDEV_WR_TGT(x)	((x) << S_FW_RDEV_WR_TGT)
3455 #define G_FW_RDEV_WR_TGT(x)	(((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT)
3456 #define F_FW_RDEV_WR_TGT	V_FW_RDEV_WR_TGT(1U)
3478 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x)	((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN)
3479 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x)	\
3480     (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN)
3484 #define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x)	\
3485     ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV)
3486 #define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x)	\
3487     (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \
3490     V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U)
3494 #define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x)	\
3495     ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL)
3496 #define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x)	\
3497     (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL)
3501 #define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x)	\
3502     ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL)
3503 #define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x)	\
3504     (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL)
3508 #define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x)	\
3509     ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL)
3510 #define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x)	\
3511     (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL)
3515 #define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x)	\
3516     ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL)
3517 #define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x)	\
3518     (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL)
3563 #define S_FW_FOISCSI_CTRL_WR_PORTID	1
3565 #define V_FW_FOISCSI_CTRL_WR_PORTID(x)	((x) << S_FW_FOISCSI_CTRL_WR_PORTID)
3566 #define G_FW_FOISCSI_CTRL_WR_PORTID(x)	\
3567     (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID)
3571 #define V_FW_FOISCSI_CTRL_WR_NO_FIN(x)	((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN)
3572 #define G_FW_FOISCSI_CTRL_WR_NO_FIN(x)	\
3573     (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN)
3574 #define F_FW_FOISCSI_CTRL_WR_NO_FIN	V_FW_FOISCSI_CTRL_WR_NO_FIN(1U)
3578 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
3579     ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE)
3580 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x)	\
3581     (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE)
3585 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
3586     ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER)
3587 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x)	\
3588     (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \
3591     V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U)
3595 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
3596     ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER)
3597 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x)	\
3598     (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \
3601     V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U)
3605 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
3606     ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN)
3607 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x)	\
3608     (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \
3611     V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U)
3615 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
3616     ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN)
3617 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x)	\
3618     (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \
3621     V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U)
3625 #define V_FW_FOISCSI_CTRL_WR_ERL(x)	((x) << S_FW_FOISCSI_CTRL_WR_ERL)
3626 #define G_FW_FOISCSI_CTRL_WR_ERL(x)	\
3627     (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL)
3631 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST)
3632 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x)	\
3633     (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST)
3637 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x)	((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST)
3638 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x)	\
3639     (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST)
3643 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
3644     ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD)
3645 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x)	\
3646     (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \
3651 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
3652     ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY)
3653 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x)	\
3654     (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \
3659 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
3660     ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
3661 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x)	\
3662     (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ)
3666 #define V_FW_FOISCSI_CTRL_WR_IPV6(x)	((x) << S_FW_FOISCSI_CTRL_WR_IPV6)
3667 #define G_FW_FOISCSI_CTRL_WR_IPV6(x)	\
3668     (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6)
3669 #define F_FW_FOISCSI_CTRL_WR_IPV6	V_FW_FOISCSI_CTRL_WR_IPV6(1U)
3673 #define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x)	\
3674     ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX)
3675 #define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x)	\
3676     (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX)
3680 #define V_FW_FOISCSI_CTRL_WR_TCP_WS(x)	((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS)
3681 #define G_FW_FOISCSI_CTRL_WR_TCP_WS(x)	\
3682     (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS)
3686 #define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x)	\
3687     ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN)
3688 #define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x)	\
3689     (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN)
3690 #define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN	V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U)
3724 #define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x)	((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG)
3725 #define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x)	\
3726     (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG)
3727 #define F_FW_FOISCSI_CHAP_WR_KV_FLAG	V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U)
3773 #define V_FW_COISCSI_TGT_WR_PORTID(x)	((x) << S_FW_COISCSI_TGT_WR_PORTID)
3774 #define G_FW_COISCSI_TGT_WR_PORTID(x)	\
3775     (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID)
3826 #define V_FW_COISCSI_TGT_CONN_WR_PORTID(x)	\
3827     ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID)
3828 #define G_FW_COISCSI_TGT_CONN_WR_PORTID(x)	\
3829     (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \
3834 #define V_FW_COISCSI_TGT_CONN_WR_FIN(x)	((x) << S_FW_COISCSI_TGT_CONN_WR_FIN)
3835 #define G_FW_COISCSI_TGT_CONN_WR_FIN(x)	\
3836     (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN)
3837 #define F_FW_COISCSI_TGT_CONN_WR_FIN	V_FW_COISCSI_TGT_CONN_WR_FIN(1U)
3839 #define S_FW_COISCSI_TGT_CONN_WR_WSCALE		1
3841 #define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x)	\
3842     ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE)
3843 #define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x)	\
3844     (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \
3849 #define V_FW_COISCSI_TGT_CONN_WR_WSEN(x)	\
3850     ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN)
3851 #define G_FW_COISCSI_TGT_CONN_WR_WSEN(x)	\
3852     (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN)
3853 #define F_FW_COISCSI_TGT_CONN_WR_WSEN	V_FW_COISCSI_TGT_CONN_WR_WSEN(1U)
3879 #define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x)	\
3880     ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST)
3881 #define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x)	\
3882     (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST)
3883 #define F_FW_COISCSI_TGT_XMIT_WR_DDGST	V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U)
3887 #define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x)	\
3888     ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST)
3889 #define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x)	\
3890     (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST)
3891 #define F_FW_COISCSI_TGT_XMIT_WR_HDGST	V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U)
3895 #define V_FW_COISCSI_TGT_XMIT_WR_DDP(x)	((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP)
3896 #define G_FW_COISCSI_TGT_XMIT_WR_DDP(x)	\
3897     (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP)
3898 #define F_FW_COISCSI_TGT_XMIT_WR_DDP	V_FW_COISCSI_TGT_XMIT_WR_DDP(1U)
3902 #define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x)	\
3903     ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT)
3904 #define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x)	\
3905     (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT)
3906 #define F_FW_COISCSI_TGT_XMIT_WR_ABORT	V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U)
3910 #define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x)	\
3911     ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL)
3912 #define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x)	\
3913     (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL)
3914 #define F_FW_COISCSI_TGT_XMIT_WR_FINAL	V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U)
3918 #define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x)	\
3919     ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN)
3920 #define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x)	\
3921     (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \
3926 #define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x)	\
3927     ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN)
3928 #define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x)	\
3929     (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \
3932     V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U)
3936 #define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x)	\
3937     ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN)
3938 #define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x)	\
3939     (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \
3944 #define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x)	\
3945     ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS)
3946 #define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x)	\
3947     (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \
3972 #define V_FW_COISCSI_STATS_WR_PORTID(x)	((x) << S_FW_COISCSI_STATS_WR_PORTID)
3973 #define G_FW_COISCSI_STATS_WR_PORTID(x)	\
3974     (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID)
4005 #define V_FW_ISNS_WR_PORTID(x)	((x) << S_FW_ISNS_WR_PORTID)
4006 #define G_FW_ISNS_WR_PORTID(x)	\
4007     (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID)
4021 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x)	((x) << S_FW_ISNS_XMIT_WR_IMMDLEN)
4022 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x)	\
4023     (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN)
4050 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x)	((x) << S_FW_FCOE_ELS_CT_WR_OPCODE)
4051 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x)	\
4052     (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE)
4056 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN)
4057 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x)	\
4058     (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN)
4062 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x)	((x) << S_FW_FCOE_ELS_CT_WR_FLOWID)
4063 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x)	\
4064     (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID)
4068 #define V_FW_FCOE_ELS_CT_WR_LEN16(x)	((x) << S_FW_FCOE_ELS_CT_WR_LEN16)
4069 #define G_FW_FCOE_ELS_CT_WR_LEN16(x)	\
4070     (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16)
4074 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x)	((x) << S_FW_FCOE_ELS_CT_WR_CP_EN)
4075 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x)	\
4076     (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN)
4080 #define V_FW_FCOE_ELS_CT_WR_CLASS(x)	((x) << S_FW_FCOE_ELS_CT_WR_CLASS)
4081 #define G_FW_FCOE_ELS_CT_WR_CLASS(x)	\
4082     (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS)
4086 #define V_FW_FCOE_ELS_CT_WR_FL(x)	((x) << S_FW_FCOE_ELS_CT_WR_FL)
4087 #define G_FW_FCOE_ELS_CT_WR_FL(x)	\
4088     (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL)
4089 #define F_FW_FCOE_ELS_CT_WR_FL	V_FW_FCOE_ELS_CT_WR_FL(1U)
4091 #define S_FW_FCOE_ELS_CT_WR_NPIV	1
4093 #define V_FW_FCOE_ELS_CT_WR_NPIV(x)	((x) << S_FW_FCOE_ELS_CT_WR_NPIV)
4094 #define G_FW_FCOE_ELS_CT_WR_NPIV(x)	\
4095     (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV)
4096 #define F_FW_FCOE_ELS_CT_WR_NPIV	V_FW_FCOE_ELS_CT_WR_NPIV(1U)
4100 #define V_FW_FCOE_ELS_CT_WR_SP(x)	((x) << S_FW_FCOE_ELS_CT_WR_SP)
4101 #define G_FW_FCOE_ELS_CT_WR_SP(x)	\
4102     (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP)
4103 #define F_FW_FCOE_ELS_CT_WR_SP	V_FW_FCOE_ELS_CT_WR_SP(1U)
4135 #define V_FW_SCSI_WRITE_WR_OPCODE(x)	((x) << S_FW_SCSI_WRITE_WR_OPCODE)
4136 #define G_FW_SCSI_WRITE_WR_OPCODE(x)	\
4137     (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE)
4141 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x)	((x) << S_FW_SCSI_WRITE_WR_IMMDLEN)
4142 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x)	\
4143     (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN)
4147 #define V_FW_SCSI_WRITE_WR_FLOWID(x)	((x) << S_FW_SCSI_WRITE_WR_FLOWID)
4148 #define G_FW_SCSI_WRITE_WR_FLOWID(x)	\
4149     (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID)
4153 #define V_FW_SCSI_WRITE_WR_LEN16(x)	((x) << S_FW_SCSI_WRITE_WR_LEN16)
4154 #define G_FW_SCSI_WRITE_WR_LEN16(x)	\
4155     (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16)
4159 #define V_FW_SCSI_WRITE_WR_CP_EN(x)	((x) << S_FW_SCSI_WRITE_WR_CP_EN)
4160 #define G_FW_SCSI_WRITE_WR_CP_EN(x)	\
4161     (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN)
4165 #define V_FW_SCSI_WRITE_WR_CLASS(x)	((x) << S_FW_SCSI_WRITE_WR_CLASS)
4166 #define G_FW_SCSI_WRITE_WR_CLASS(x)	\
4167     (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS)
4195 #define V_FW_SCSI_READ_WR_OPCODE(x)	((x) << S_FW_SCSI_READ_WR_OPCODE)
4196 #define G_FW_SCSI_READ_WR_OPCODE(x)	\
4197     (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE)
4201 #define V_FW_SCSI_READ_WR_IMMDLEN(x)	((x) << S_FW_SCSI_READ_WR_IMMDLEN)
4202 #define G_FW_SCSI_READ_WR_IMMDLEN(x)	\
4203     (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN)
4207 #define V_FW_SCSI_READ_WR_FLOWID(x)	((x) << S_FW_SCSI_READ_WR_FLOWID)
4208 #define G_FW_SCSI_READ_WR_FLOWID(x)	\
4209     (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID)
4213 #define V_FW_SCSI_READ_WR_LEN16(x)	((x) << S_FW_SCSI_READ_WR_LEN16)
4214 #define G_FW_SCSI_READ_WR_LEN16(x)	\
4215     (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16)
4219 #define V_FW_SCSI_READ_WR_CP_EN(x)	((x) << S_FW_SCSI_READ_WR_CP_EN)
4220 #define G_FW_SCSI_READ_WR_CP_EN(x)	\
4221     (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN)
4225 #define V_FW_SCSI_READ_WR_CLASS(x)	((x) << S_FW_SCSI_READ_WR_CLASS)
4226 #define G_FW_SCSI_READ_WR_CLASS(x)	\
4227     (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS)
4254 #define V_FW_SCSI_CMD_WR_OPCODE(x)	((x) << S_FW_SCSI_CMD_WR_OPCODE)
4255 #define G_FW_SCSI_CMD_WR_OPCODE(x)	\
4256     (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE)
4260 #define V_FW_SCSI_CMD_WR_IMMDLEN(x)	((x) << S_FW_SCSI_CMD_WR_IMMDLEN)
4261 #define G_FW_SCSI_CMD_WR_IMMDLEN(x)	\
4262     (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN)
4266 #define V_FW_SCSI_CMD_WR_FLOWID(x)	((x) << S_FW_SCSI_CMD_WR_FLOWID)
4267 #define G_FW_SCSI_CMD_WR_FLOWID(x)	\
4268     (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID)
4272 #define V_FW_SCSI_CMD_WR_LEN16(x)	((x) << S_FW_SCSI_CMD_WR_LEN16)
4273 #define G_FW_SCSI_CMD_WR_LEN16(x)	\
4274     (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16)
4278 #define V_FW_SCSI_CMD_WR_CP_EN(x)	((x) << S_FW_SCSI_CMD_WR_CP_EN)
4279 #define G_FW_SCSI_CMD_WR_CP_EN(x)	\
4280     (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN)
4284 #define V_FW_SCSI_CMD_WR_CLASS(x)	((x) << S_FW_SCSI_CMD_WR_CLASS)
4285 #define G_FW_SCSI_CMD_WR_CLASS(x)	\
4286     (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS)
4301 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE)
4302 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x)	\
4303     (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE)
4307 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
4308     ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
4309 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x)	\
4310     (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN)
4314 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID)
4315 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x)	\
4316     (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID)
4320 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16)
4321 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x)	\
4322     (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16)
4326 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
4327     ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE)
4328 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x)	\
4329     (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \
4332 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL	1
4334 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL)
4335 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x)	\
4336     (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL)
4337 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL	V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U)
4341 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
4342     ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO)
4343 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x)	\
4344     (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \
4347     V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U)
4375 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE)
4376 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x)	\
4377     (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE)
4381 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN)
4382 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x)	\
4383     (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN)
4387 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID)
4388 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x)	\
4389     (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID)
4393 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_ACC_WR_LEN16)
4394 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x)	\
4395     (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16)
4399 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN)
4400 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x)	\
4401     (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN)
4405 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_ACC_WR_CLASS)
4406 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x)	\
4407     (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS)
4435 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE)
4436 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x)	\
4437     (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE)
4441 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
4442     ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
4443 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x)	\
4444     (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN)
4448 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID)
4449 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x)	\
4450     (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID)
4454 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16)
4455 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x)	\
4456     (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16)
4460 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN)
4461 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x)	\
4462     (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN)
4466 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS)
4467 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x)	\
4468     (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS)
4491 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x)	((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE)
4492 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x)	\
4493     (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE)
4497 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN)
4498 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x)	\
4499     (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN)
4503 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x)	((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID)
4504 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x)	\
4505     (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID)
4509 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x)	((x) << S_FW_SCSI_TGT_RSP_WR_LEN16)
4510 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x)	\
4511     (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16)
4515 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN)
4516 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x)	\
4517     (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN)
4521 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x)	((x) << S_FW_SCSI_TGT_RSP_WR_CLASS)
4522 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x)	\
4523     (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS)
4543 #define V_FW_POFCOE_TCB_WR_TID(x)	((x) << S_FW_POFCOE_TCB_WR_TID)
4544 #define G_FW_POFCOE_TCB_WR_TID(x)	\
4545     (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID)
4549 #define V_FW_POFCOE_TCB_WR_ALLOC(x)	((x) << S_FW_POFCOE_TCB_WR_ALLOC)
4550 #define G_FW_POFCOE_TCB_WR_ALLOC(x)	\
4551     (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC)
4552 #define F_FW_POFCOE_TCB_WR_ALLOC	V_FW_POFCOE_TCB_WR_ALLOC(1U)
4556 #define V_FW_POFCOE_TCB_WR_FREE(x)	((x) << S_FW_POFCOE_TCB_WR_FREE)
4557 #define G_FW_POFCOE_TCB_WR_FREE(x)	\
4558     (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE)
4559 #define F_FW_POFCOE_TCB_WR_FREE	V_FW_POFCOE_TCB_WR_FREE(1U)
4563 #define V_FW_POFCOE_TCB_WR_PORT(x)	((x) << S_FW_POFCOE_TCB_WR_PORT)
4564 #define G_FW_POFCOE_TCB_WR_PORT(x)	\
4565     (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT)
4589 #define V_FW_TX_PI_HEADER_OP(x)	((x) << S_FW_TX_PI_HEADER_OP)
4590 #define G_FW_TX_PI_HEADER_OP(x)	\
4591     (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP)
4595 #define V_FW_TX_PI_HEADER_ULPTXMORE(x)	((x) << S_FW_TX_PI_HEADER_ULPTXMORE)
4596 #define G_FW_TX_PI_HEADER_ULPTXMORE(x)	\
4597     (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE)
4598 #define F_FW_TX_PI_HEADER_ULPTXMORE	V_FW_TX_PI_HEADER_ULPTXMORE(1U)
4602 #define V_FW_TX_PI_HEADER_PI_CONTROL(x)	((x) << S_FW_TX_PI_HEADER_PI_CONTROL)
4603 #define G_FW_TX_PI_HEADER_PI_CONTROL(x)	\
4604     (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL)
4608 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x)	((x) << S_FW_TX_PI_HEADER_GUARD_TYPE)
4609 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x)	\
4610     (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE)
4611 #define F_FW_TX_PI_HEADER_GUARD_TYPE	V_FW_TX_PI_HEADER_GUARD_TYPE(1U)
4613 #define S_FW_TX_PI_HEADER_VALIDATE	1
4615 #define V_FW_TX_PI_HEADER_VALIDATE(x)	((x) << S_FW_TX_PI_HEADER_VALIDATE)
4616 #define G_FW_TX_PI_HEADER_VALIDATE(x)	\
4617     (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE)
4618 #define F_FW_TX_PI_HEADER_VALIDATE	V_FW_TX_PI_HEADER_VALIDATE(1U)
4622 #define V_FW_TX_PI_HEADER_INLINE(x)	((x) << S_FW_TX_PI_HEADER_INLINE)
4623 #define G_FW_TX_PI_HEADER_INLINE(x)	\
4624     (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE)
4625 #define F_FW_TX_PI_HEADER_INLINE	V_FW_TX_PI_HEADER_INLINE(1U)
4629 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x)	\
4630     ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL)
4631 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x)	\
4632     (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL)
4633 #define F_FW_TX_PI_HEADER_PI_INTERVAL	V_FW_TX_PI_HEADER_PI_INTERVAL(1U)
4637 #define V_FW_TX_PI_HEADER_TAG_TYPE(x)	((x) << S_FW_TX_PI_HEADER_TAG_TYPE)
4638 #define G_FW_TX_PI_HEADER_TAG_TYPE(x)	\
4639     (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE)
4643 #define V_FW_TX_PI_HEADER_PI_START4(x)	((x) << S_FW_TX_PI_HEADER_PI_START4)
4644 #define G_FW_TX_PI_HEADER_PI_START4(x)	\
4645     (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4)
4649 #define V_FW_TX_PI_HEADER_PI_END4(x)	((x) << S_FW_TX_PI_HEADER_PI_END4)
4650 #define G_FW_TX_PI_HEADER_PI_END4(x)	\
4651     (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4)
4655 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x)	\
4656     ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED)
4657 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x)	\
4658     (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \
4676 #define V_FW_PI_ERROR_ERR_TYPE(x)	((x) << S_FW_PI_ERROR_ERR_TYPE)
4677 #define G_FW_PI_ERROR_ERR_TYPE(x)	\
4678     (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE)
4696 #define V_FW_TLSTX_DATA_WR_OPCODE(x)    ((x) << S_FW_TLSTX_DATA_WR_OPCODE)
4697 #define G_FW_TLSTX_DATA_WR_OPCODE(x)    \
4698     (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE)
4702 #define V_FW_TLSTX_DATA_WR_COMPL(x)     ((x) << S_FW_TLSTX_DATA_WR_COMPL)
4703 #define G_FW_TLSTX_DATA_WR_COMPL(x)     \
4704     (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL)
4705 #define F_FW_TLSTX_DATA_WR_COMPL        V_FW_TLSTX_DATA_WR_COMPL(1U)
4709 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x)   ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN)
4710 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x)   \
4711     (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN)
4715 #define V_FW_TLSTX_DATA_WR_FLOWID(x)    ((x) << S_FW_TLSTX_DATA_WR_FLOWID)
4716 #define G_FW_TLSTX_DATA_WR_FLOWID(x)    \
4717     (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID)
4721 #define V_FW_TLSTX_DATA_WR_LEN16(x)     ((x) << S_FW_TLSTX_DATA_WR_LEN16)
4722 #define G_FW_TLSTX_DATA_WR_LEN16(x)     \
4723     (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16)
4727 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \
4728     ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE)
4729 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \
4730     (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE)
4731 #define F_FW_TLSTX_DATA_WR_LSODISABLE   V_FW_TLSTX_DATA_WR_LSODISABLE(1U)
4735 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x)  ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD)
4736 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x)  \
4737     (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD)
4738 #define F_FW_TLSTX_DATA_WR_ALIGNPLD     V_FW_TLSTX_DATA_WR_ALIGNPLD(1U)
4742 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
4743     ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE)
4744 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \
4745     (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \
4747 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U)
4751 #define V_FW_TLSTX_DATA_WR_FLAGS(x)     ((x) << S_FW_TLSTX_DATA_WR_FLAGS)
4752 #define G_FW_TLSTX_DATA_WR_FLAGS(x)     \
4753     (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS)
4757 #define V_FW_TLSTX_DATA_WR_CTXLOC(x)    ((x) << S_FW_TLSTX_DATA_WR_CTXLOC)
4758 #define G_FW_TLSTX_DATA_WR_CTXLOC(x)    \
4759     (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC)
4763 #define V_FW_TLSTX_DATA_WR_IVDSGL(x)    ((x) << S_FW_TLSTX_DATA_WR_IVDSGL)
4764 #define G_FW_TLSTX_DATA_WR_IVDSGL(x)    \
4765     (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL)
4766 #define F_FW_TLSTX_DATA_WR_IVDSGL       V_FW_TLSTX_DATA_WR_IVDSGL(1U)
4770 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x)   ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE)
4771 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x)   \
4772     (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE)
4776 #define V_FW_TLSTX_DATA_WR_NUMIVS(x)    ((x) << S_FW_TLSTX_DATA_WR_NUMIVS)
4777 #define G_FW_TLSTX_DATA_WR_NUMIVS(x)    \
4778     (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS)
4782 #define V_FW_TLSTX_DATA_WR_EXP(x)       ((x) << S_FW_TLSTX_DATA_WR_EXP)
4783 #define G_FW_TLSTX_DATA_WR_EXP(x)       \
4784     (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP)
4786 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1
4788 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
4789     ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN)
4790 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \
4791     (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \
4796 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
4797     ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX)
4798 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \
4799     (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \
4804 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
4805     ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX)
4806 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \
4807     (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \
4822 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
4823     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE)
4824 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \
4825     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \
4830 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
4831     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL)
4832 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \
4833     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \
4835 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U)
4839 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
4840     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN)
4841 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \
4842     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \
4847 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
4848     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC)
4849 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \
4850     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \
4855 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
4856     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE)
4857 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \
4858     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \
4863 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
4864     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16)
4865 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \
4866     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \
4871 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
4872     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID)
4873 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \
4874     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \
4879 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
4880     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB)
4881 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \
4882     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB)
4886 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
4887     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH)
4888 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \
4889     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \
4894 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
4895     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV)
4896 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \
4897     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV)
4901 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4902 	((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX)
4903 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \
4904 	(((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\
4909 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4910     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH)
4911 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \
4912     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \
4917 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4918     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID)
4919 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \
4920     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \
4925 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4926     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE)
4927 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \
4928     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \
4933 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4934     ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE)
4935 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \
4936     (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \
4995 #define V_FW_CRYPTO_UPDATE_SA_WR_SAOP(x)	\
4996     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SAOP)
4997 #define G_FW_CRYPTO_UPDATE_SA_WR_SAOP(x)	\
4998     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SAOP) & M_FW_CRYPTO_UPDATE_SA_WR_SAOP)
4999 #define F_FW_CRYPTO_UPDATE_SA_WR_SAOP	V_FW_CRYPTO_UPDATE_SA_WR_SAOP(1U)
5001 #define S_FW_CRYPTO_UPDATE_SA_WR_MODE		1
5003 #define V_FW_CRYPTO_UPDATE_SA_WR_MODE(x)	\
5004     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_MODE)
5005 #define G_FW_CRYPTO_UPDATE_SA_WR_MODE(x)	\
5006     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_MODE) & M_FW_CRYPTO_UPDATE_SA_WR_MODE)
5007 #define F_FW_CRYPTO_UPDATE_SA_WR_MODE	V_FW_CRYPTO_UPDATE_SA_WR_MODE(1U)
5011 #define V_FW_CRYPTO_UPDATE_SA_WR_TXRX(x)	\
5012     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_TXRX)
5013 #define G_FW_CRYPTO_UPDATE_SA_WR_TXRX(x)	\
5014     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_TXRX) & M_FW_CRYPTO_UPDATE_SA_WR_TXRX)
5015 #define F_FW_CRYPTO_UPDATE_SA_WR_TXRX	V_FW_CRYPTO_UPDATE_SA_WR_TXRX(1U)
5019 #define V_FW_CRYPTO_UPDATE_SA_WR_VALID(x)	\
5020     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_VALID)
5021 #define G_FW_CRYPTO_UPDATE_SA_WR_VALID(x)	\
5022     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_VALID) & M_FW_CRYPTO_UPDATE_SA_WR_VALID)
5023 #define F_FW_CRYPTO_UPDATE_SA_WR_VALID	V_FW_CRYPTO_UPDATE_SA_WR_VALID(1U)
5027 #define V_FW_CRYPTO_UPDATE_SA_WR_SPI_HI(x)	\
5028     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI)
5029 #define G_FW_CRYPTO_UPDATE_SA_WR_SPI_HI(x)	\
5030     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI) & \
5035 #define V_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(x)	\
5036     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO)
5037 #define G_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(x)	\
5038     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO) & \
5040 #define F_FW_CRYPTO_UPDATE_SA_WR_SPI_LO	V_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(1U)
5044 #define V_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI(x)	\
5045     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI)
5046 #define G_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI(x)	\
5047     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI) & \
5052 #define V_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO(x)	\
5053     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO)
5054 #define G_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO(x)	\
5055     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO) & \
5060 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x)	\
5061     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI)
5062 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x)	\
5063     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) & \
5068 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x)	\
5069     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO)
5070 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x)	\
5071     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) & \
5076 #define V_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x)	\
5077     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN)
5078 #define G_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x)	\
5079     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) & \
5084 #define V_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(x)	\
5085     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE)
5086 #define G_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(x)	\
5087     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE) & \
5090     V_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(1U)
5094 #define V_FW_CRYPTO_UPDATE_SA_WR_KEYID(x)	\
5095     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYID)
5096 #define G_FW_CRYPTO_UPDATE_SA_WR_KEYID(x)	\
5097     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYID) & M_FW_CRYPTO_UPDATE_SA_WR_KEYID)
5101 #define V_FW_CRYPTO_UPDATE_SA_WR_VALID(x)	\
5102     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_VALID)
5103 #define G_FW_CRYPTO_UPDATE_SA_WR_VALID(x)	\
5104     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_VALID) & M_FW_CRYPTO_UPDATE_SA_WR_VALID)
5105 #define F_FW_CRYPTO_UPDATE_SA_WR_VALID	V_FW_CRYPTO_UPDATE_SA_WR_VALID(1U)
5109 #define V_FW_CRYPTO_UPDATE_SA_WR_EGKEYID(x)	\
5110     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID)
5111 #define G_FW_CRYPTO_UPDATE_SA_WR_EGKEYID(x)	\
5112     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID) & \
5117 #define V_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(x)	\
5118     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN)
5119 #define G_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(x)	\
5120     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN) & \
5123     V_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(1U)
5127 #define V_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW(x)	\
5128     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW)
5129 #define G_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW(x)	\
5130     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW) & \
5135 #define V_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI(x)	\
5136     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI)
5137 #define G_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI(x)	\
5138     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI) & \
5143 #define V_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO(x)	\
5144     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO)
5145 #define G_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO(x)	\
5146     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO) & \
5151 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x)	\
5152     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI)
5153 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x)	\
5154     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) & \
5159 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x)	\
5160     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO)
5161 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x)	\
5162     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) & \
5167 #define V_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x)	\
5168     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN)
5169 #define G_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x)	\
5170     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) & \
5175 #define V_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH(x)	\
5176     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH)
5177 #define G_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH(x)	\
5178     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH) & \
5183 #define V_FW_CRYPTO_UPDATE_SA_WR_ESNEN(x)	\
5184     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESNEN)
5185 #define G_FW_CRYPTO_UPDATE_SA_WR_ESNEN(x)	\
5186     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESNEN) & M_FW_CRYPTO_UPDATE_SA_WR_ESNEN)
5187 #define F_FW_CRYPTO_UPDATE_SA_WR_ESNEN	V_FW_CRYPTO_UPDATE_SA_WR_ESNEN(1U)
5189 #define S_FW_CRYPTO_UPDATE_SA_WR_MODE		1
5191 #define V_FW_CRYPTO_UPDATE_SA_WR_MODE(x)	\
5192     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_MODE)
5193 #define G_FW_CRYPTO_UPDATE_SA_WR_MODE(x)	\
5194     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_MODE) & M_FW_CRYPTO_UPDATE_SA_WR_MODE)
5195 #define F_FW_CRYPTO_UPDATE_SA_WR_MODE	V_FW_CRYPTO_UPDATE_SA_WR_MODE(1U)
5199 #define V_FW_CRYPTO_UPDATE_SA_WR_IPVER(x)	\
5200     ((x) << S_FW_CRYPTO_UPDATE_SA_WR_IPVER)
5201 #define G_FW_CRYPTO_UPDATE_SA_WR_IPVER(x)	\
5202     (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_IPVER) & M_FW_CRYPTO_UPDATE_SA_WR_IPVER)
5203 #define F_FW_CRYPTO_UPDATE_SA_WR_IPVER	V_FW_CRYPTO_UPDATE_SA_WR_IPVER(1U)
5299 #define V_FW_CMD_OP(x)		((x) << S_FW_CMD_OP)
5300 #define G_FW_CMD_OP(x)		(((x) >> S_FW_CMD_OP) & M_FW_CMD_OP)
5304 #define V_FW_CMD_REQUEST(x)	((x) << S_FW_CMD_REQUEST)
5305 #define G_FW_CMD_REQUEST(x)	(((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST)
5306 #define F_FW_CMD_REQUEST	V_FW_CMD_REQUEST(1U)
5310 #define V_FW_CMD_READ(x)	((x) << S_FW_CMD_READ)
5311 #define G_FW_CMD_READ(x)	(((x) >> S_FW_CMD_READ) & M_FW_CMD_READ)
5312 #define F_FW_CMD_READ		V_FW_CMD_READ(1U)
5316 #define V_FW_CMD_WRITE(x)	((x) << S_FW_CMD_WRITE)
5317 #define G_FW_CMD_WRITE(x)	(((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE)
5318 #define F_FW_CMD_WRITE		V_FW_CMD_WRITE(1U)
5322 #define V_FW_CMD_EXEC(x)	((x) << S_FW_CMD_EXEC)
5323 #define G_FW_CMD_EXEC(x)	(((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC)
5324 #define F_FW_CMD_EXEC		V_FW_CMD_EXEC(1U)
5328 #define V_FW_CMD_RAMASK(x)	((x) << S_FW_CMD_RAMASK)
5329 #define G_FW_CMD_RAMASK(x)	(((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK)
5333 #define V_FW_CMD_RETVAL(x)	((x) << S_FW_CMD_RETVAL)
5334 #define G_FW_CMD_RETVAL(x)	(((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL)
5338 #define V_FW_CMD_LEN16(x)	((x) << S_FW_CMD_LEN16)
5339 #define G_FW_CMD_LEN16(x)	(((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16)
5490 #define V_FW_LDST_CMD_ADDRSPACE(x)	((x) << S_FW_LDST_CMD_ADDRSPACE)
5491 #define G_FW_LDST_CMD_ADDRSPACE(x)	\
5492     (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE)
5496 #define V_FW_LDST_CMD_CYCLES(x)		((x) << S_FW_LDST_CMD_CYCLES)
5497 #define G_FW_LDST_CMD_CYCLES(x)		\
5498     (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES)
5502 #define V_FW_LDST_CMD_MSG(x)		((x) << S_FW_LDST_CMD_MSG)
5503 #define G_FW_LDST_CMD_MSG(x)		\
5504     (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG)
5505 #define F_FW_LDST_CMD_MSG		V_FW_LDST_CMD_MSG(1U)
5509 #define V_FW_LDST_CMD_CTXTFLUSH(x)	((x) << S_FW_LDST_CMD_CTXTFLUSH)
5510 #define G_FW_LDST_CMD_CTXTFLUSH(x)	\
5511     (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH)
5512 #define F_FW_LDST_CMD_CTXTFLUSH		V_FW_LDST_CMD_CTXTFLUSH(1U)
5516 #define V_FW_LDST_CMD_PADDR(x)		((x) << S_FW_LDST_CMD_PADDR)
5517 #define G_FW_LDST_CMD_PADDR(x)		\
5518     (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR)
5522 #define V_FW_LDST_CMD_MMD(x)		((x) << S_FW_LDST_CMD_MMD)
5523 #define G_FW_LDST_CMD_MMD(x)		\
5524     (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD)
5528 #define V_FW_LDST_CMD_FID(x)		((x) << S_FW_LDST_CMD_FID)
5529 #define G_FW_LDST_CMD_FID(x)		\
5530     (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID)
5531 #define F_FW_LDST_CMD_FID		V_FW_LDST_CMD_FID(1U)
5535 #define V_FW_LDST_CMD_IDX(x)		((x) << S_FW_LDST_CMD_IDX)
5536 #define G_FW_LDST_CMD_IDX(x)		\
5537     (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX)
5541 #define V_FW_LDST_CMD_RPLCPF(x)		((x) << S_FW_LDST_CMD_RPLCPF)
5542 #define G_FW_LDST_CMD_RPLCPF(x)		\
5543     (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF)
5547 #define V_FW_LDST_CMD_MPSID(x)		((x) << S_FW_LDST_CMD_MPSID)
5548 #define G_FW_LDST_CMD_MPSID(x)		\
5549     (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID)
5553 #define V_FW_LDST_CMD_CTRL(x)		((x) << S_FW_LDST_CMD_CTRL)
5554 #define G_FW_LDST_CMD_CTRL(x)		\
5555     (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL)
5556 #define F_FW_LDST_CMD_CTRL		V_FW_LDST_CMD_CTRL(1U)
5560 #define V_FW_LDST_CMD_LC(x)		((x) << S_FW_LDST_CMD_LC)
5561 #define G_FW_LDST_CMD_LC(x)		\
5562     (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC)
5563 #define F_FW_LDST_CMD_LC		V_FW_LDST_CMD_LC(1U)
5567 #define V_FW_LDST_CMD_AI(x)		((x) << S_FW_LDST_CMD_AI)
5568 #define G_FW_LDST_CMD_AI(x)		\
5569     (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI)
5570 #define F_FW_LDST_CMD_AI		V_FW_LDST_CMD_AI(1U)
5574 #define V_FW_LDST_CMD_FN(x)		((x) << S_FW_LDST_CMD_FN)
5575 #define G_FW_LDST_CMD_FN(x)		\
5576     (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN)
5580 #define V_FW_LDST_CMD_SELECT(x)		((x) << S_FW_LDST_CMD_SELECT)
5581 #define G_FW_LDST_CMD_SELECT(x)		\
5582     (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT)
5586 #define V_FW_LDST_CMD_NACCESS(x)	((x) << S_FW_LDST_CMD_NACCESS)
5587 #define G_FW_LDST_CMD_NACCESS(x)	\
5588     (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS)
5592 #define V_FW_LDST_CMD_NSET(x)		((x) << S_FW_LDST_CMD_NSET)
5593 #define G_FW_LDST_CMD_NSET(x)		\
5594     (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET)
5598 #define V_FW_LDST_CMD_PID(x)		((x) << S_FW_LDST_CMD_PID)
5599 #define G_FW_LDST_CMD_PID(x)		\
5600     (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID)
5611 #define V_FW_RESET_CMD_HALT(x)		((x) << S_FW_RESET_CMD_HALT)
5612 #define G_FW_RESET_CMD_HALT(x)		\
5613     (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT)
5614 #define F_FW_RESET_CMD_HALT		V_FW_RESET_CMD_HALT(1U)
5618 	FW_HELLO_CMD_STAGE_PREOS0	= 1,
5632 #define V_FW_HELLO_CMD_ERR(x)		((x) << S_FW_HELLO_CMD_ERR)
5633 #define G_FW_HELLO_CMD_ERR(x)		\
5634     (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR)
5635 #define F_FW_HELLO_CMD_ERR		V_FW_HELLO_CMD_ERR(1U)
5639 #define V_FW_HELLO_CMD_INIT(x)		((x) << S_FW_HELLO_CMD_INIT)
5640 #define G_FW_HELLO_CMD_INIT(x)		\
5641     (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT)
5642 #define F_FW_HELLO_CMD_INIT		V_FW_HELLO_CMD_INIT(1U)
5646 #define V_FW_HELLO_CMD_MASTERDIS(x)	((x) << S_FW_HELLO_CMD_MASTERDIS)
5647 #define G_FW_HELLO_CMD_MASTERDIS(x)	\
5648     (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS)
5649 #define F_FW_HELLO_CMD_MASTERDIS	V_FW_HELLO_CMD_MASTERDIS(1U)
5653 #define V_FW_HELLO_CMD_MASTERFORCE(x)	((x) << S_FW_HELLO_CMD_MASTERFORCE)
5654 #define G_FW_HELLO_CMD_MASTERFORCE(x)	\
5655     (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE)
5656 #define F_FW_HELLO_CMD_MASTERFORCE	V_FW_HELLO_CMD_MASTERFORCE(1U)
5660 #define V_FW_HELLO_CMD_MBMASTER(x)	((x) << S_FW_HELLO_CMD_MBMASTER)
5661 #define G_FW_HELLO_CMD_MBMASTER(x)	\
5662     (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER)
5666 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOTINT)
5667 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x)	\
5668     (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT)
5669 #define F_FW_HELLO_CMD_MBASYNCNOTINT	V_FW_HELLO_CMD_MBASYNCNOTINT(1U)
5673 #define V_FW_HELLO_CMD_MBASYNCNOT(x)	((x) << S_FW_HELLO_CMD_MBASYNCNOT)
5674 #define G_FW_HELLO_CMD_MBASYNCNOT(x)	\
5675     (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT)
5679 #define V_FW_HELLO_CMD_STAGE(x)		((x) << S_FW_HELLO_CMD_STAGE)
5680 #define G_FW_HELLO_CMD_STAGE(x)		\
5681     (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE)
5685 #define V_FW_HELLO_CMD_CLEARINIT(x)	((x) << S_FW_HELLO_CMD_CLEARINIT)
5686 #define G_FW_HELLO_CMD_CLEARINIT(x)	\
5687     (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT)
5688 #define F_FW_HELLO_CMD_CLEARINIT	V_FW_HELLO_CMD_CLEARINIT(1U)
5851 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x)	((x) << S_FW_CAPS_CONFIG_CMD_CFVALID)
5852 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x)	\
5853     (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID)
5854 #define F_FW_CAPS_CONFIG_CMD_CFVALID	V_FW_CAPS_CONFIG_CMD_CFVALID(1U)
5858 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
5859     ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF)
5860 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \
5861     (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \
5866 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
5867     ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF)
5868 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \
5869     (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \
5876 	FW_PARAMS_MNEM_DEV		= 1,	/* device params */
5889 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \
5890     ((x) << S_FW_PARAMS_PARAM_FILTER_MODE)
5891 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \
5892     (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \
5897 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \
5898     ((x) << S_FW_PARAMS_PARAM_FILTER_MASK)
5899 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \
5900     (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \
6001 	FW_VNIC_MODE_OUTER_VLAN = 1,
6118 #define V_T7_DMAQ_CONM_CTXT_CNGTPMODE(x)  ((x) << S_T7_DMAQ_CONM_CTXT_CNGTPMODE)
6119 #define G_T7_DMAQ_CONM_CTXT_CNGTPMODE(x)  \
6120 	(((x) >> S_T7_DMAQ_CONM_CTXT_CNGTPMODE) & M_T7_DMAQ_CONM_CTXT_CNGTPMODE)
6124 #define V_T7_DMAQ_CONM_CTXT_CH_VEC(x)  ((x) << S_T7_DMAQ_CONM_CTXT_CH_VEC)
6125 #define G_T7_DMAQ_CONM_CTXT_CH_VEC(x)  \
6126 	(((x) >> S_T7_DMAQ_CONM_CTXT_CH_VEC) & M_T7_DMAQ_CONM_CTXT_CH_VEC)
6145 #define V_FW_PARAMS_MNEM(x)	((x) << S_FW_PARAMS_MNEM)
6146 #define G_FW_PARAMS_MNEM(x)	\
6147     (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM)
6151 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X)
6152 #define G_FW_PARAMS_PARAM_X(x) \
6153     (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X)
6157 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y)
6158 #define G_FW_PARAMS_PARAM_Y(x) \
6159     (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y)
6163 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z)
6164 #define G_FW_PARAMS_PARAM_Z(x) \
6165     (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z)
6169 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ)
6170 #define G_FW_PARAMS_PARAM_XYZ(x) \
6171     (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ)
6175 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ)
6176 #define G_FW_PARAMS_PARAM_YZ(x) \
6177     (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ)
6181 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
6182     ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN)
6183 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \
6184     (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \
6189 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
6190     ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT)
6191 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \
6192     (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \
6197 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
6198     ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST)
6199 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \
6200     (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST)
6204 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x)	\
6205     ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE)
6206 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x)	\
6207     (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \
6212 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x)	\
6213     ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX)
6214 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x)	\
6215     (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \
6229 #define V_FW_PARAMS_CMD_PFN(x)		((x) << S_FW_PARAMS_CMD_PFN)
6230 #define G_FW_PARAMS_CMD_PFN(x)		\
6231     (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN)
6235 #define V_FW_PARAMS_CMD_VFN(x)		((x) << S_FW_PARAMS_CMD_VFN)
6236 #define G_FW_PARAMS_CMD_VFN(x)		\
6237     (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN)
6253 #define V_FW_PFVF_CMD_PFN(x)		((x) << S_FW_PFVF_CMD_PFN)
6254 #define G_FW_PFVF_CMD_PFN(x)		\
6255     (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN)
6259 #define V_FW_PFVF_CMD_VFN(x)		((x) << S_FW_PFVF_CMD_VFN)
6260 #define G_FW_PFVF_CMD_VFN(x)		\
6261     (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN)
6265 #define V_FW_PFVF_CMD_NIQFLINT(x)	((x) << S_FW_PFVF_CMD_NIQFLINT)
6266 #define G_FW_PFVF_CMD_NIQFLINT(x)	\
6267     (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT)
6271 #define V_FW_PFVF_CMD_NIQ(x)		((x) << S_FW_PFVF_CMD_NIQ)
6272 #define G_FW_PFVF_CMD_NIQ(x)		\
6273     (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ)
6277 #define V_FW_PFVF_CMD_TYPE(x)		((x) << S_FW_PFVF_CMD_TYPE)
6278 #define G_FW_PFVF_CMD_TYPE(x)		\
6279     (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE)
6280 #define F_FW_PFVF_CMD_TYPE		V_FW_PFVF_CMD_TYPE(1U)
6284 #define V_FW_PFVF_CMD_CMASK(x)		((x) << S_FW_PFVF_CMD_CMASK)
6285 #define G_FW_PFVF_CMD_CMASK(x)		\
6286     (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK)
6290 #define V_FW_PFVF_CMD_PMASK(x)		((x) << S_FW_PFVF_CMD_PMASK)
6291 #define G_FW_PFVF_CMD_PMASK(x)		\
6292     (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK)
6296 #define V_FW_PFVF_CMD_NEQ(x)		((x) << S_FW_PFVF_CMD_NEQ)
6297 #define G_FW_PFVF_CMD_NEQ(x)		\
6298     (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ)
6302 #define V_FW_PFVF_CMD_TC(x)		((x) << S_FW_PFVF_CMD_TC)
6303 #define G_FW_PFVF_CMD_TC(x)		\
6304     (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC)
6308 #define V_FW_PFVF_CMD_NVI(x)		((x) << S_FW_PFVF_CMD_NVI)
6309 #define G_FW_PFVF_CMD_NVI(x)		\
6310     (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI)
6314 #define V_FW_PFVF_CMD_NEXACTF(x)	((x) << S_FW_PFVF_CMD_NEXACTF)
6315 #define G_FW_PFVF_CMD_NEXACTF(x)	\
6316     (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF)
6320 #define V_FW_PFVF_CMD_R_CAPS(x)		((x) << S_FW_PFVF_CMD_R_CAPS)
6321 #define G_FW_PFVF_CMD_R_CAPS(x)		\
6322     (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS)
6326 #define V_FW_PFVF_CMD_WX_CAPS(x)	((x) << S_FW_PFVF_CMD_WX_CAPS)
6327 #define G_FW_PFVF_CMD_WX_CAPS(x)	\
6328     (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS)
6332 #define V_FW_PFVF_CMD_NETHCTRL(x)	((x) << S_FW_PFVF_CMD_NETHCTRL)
6333 #define G_FW_PFVF_CMD_NETHCTRL(x)	\
6334     (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL)
6337  *	ingress queue type; the first 1K ingress queues can have associated 0,
6338  *	1 or 2 free lists and an interrupt, all other ingress queues lack these
6377 #define V_FW_IQ_CMD_PFN(x)		((x) << S_FW_IQ_CMD_PFN)
6378 #define G_FW_IQ_CMD_PFN(x)		\
6379     (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN)
6383 #define V_FW_IQ_CMD_VFN(x)		((x) << S_FW_IQ_CMD_VFN)
6384 #define G_FW_IQ_CMD_VFN(x)		\
6385     (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN)
6389 #define V_FW_IQ_CMD_ALLOC(x)		((x) << S_FW_IQ_CMD_ALLOC)
6390 #define G_FW_IQ_CMD_ALLOC(x)		\
6391     (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC)
6392 #define F_FW_IQ_CMD_ALLOC		V_FW_IQ_CMD_ALLOC(1U)
6396 #define V_FW_IQ_CMD_FREE(x)		((x) << S_FW_IQ_CMD_FREE)
6397 #define G_FW_IQ_CMD_FREE(x)		\
6398     (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE)
6399 #define F_FW_IQ_CMD_FREE		V_FW_IQ_CMD_FREE(1U)
6403 #define V_FW_IQ_CMD_MODIFY(x)		((x) << S_FW_IQ_CMD_MODIFY)
6404 #define G_FW_IQ_CMD_MODIFY(x)		\
6405     (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY)
6406 #define F_FW_IQ_CMD_MODIFY		V_FW_IQ_CMD_MODIFY(1U)
6410 #define V_FW_IQ_CMD_IQSTART(x)		((x) << S_FW_IQ_CMD_IQSTART)
6411 #define G_FW_IQ_CMD_IQSTART(x)		\
6412     (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART)
6413 #define F_FW_IQ_CMD_IQSTART		V_FW_IQ_CMD_IQSTART(1U)
6417 #define V_FW_IQ_CMD_IQSTOP(x)		((x) << S_FW_IQ_CMD_IQSTOP)
6418 #define G_FW_IQ_CMD_IQSTOP(x)		\
6419     (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP)
6420 #define F_FW_IQ_CMD_IQSTOP		V_FW_IQ_CMD_IQSTOP(1U)
6424 #define V_FW_IQ_CMD_TYPE(x)		((x) << S_FW_IQ_CMD_TYPE)
6425 #define G_FW_IQ_CMD_TYPE(x)		\
6426     (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE)
6430 #define V_FW_IQ_CMD_IQASYNCH(x)		((x) << S_FW_IQ_CMD_IQASYNCH)
6431 #define G_FW_IQ_CMD_IQASYNCH(x)		\
6432     (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH)
6433 #define F_FW_IQ_CMD_IQASYNCH		V_FW_IQ_CMD_IQASYNCH(1U)
6437 #define V_FW_IQ_CMD_VIID(x)		((x) << S_FW_IQ_CMD_VIID)
6438 #define G_FW_IQ_CMD_VIID(x)		\
6439     (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID)
6443 #define V_FW_IQ_CMD_IQANDST(x)		((x) << S_FW_IQ_CMD_IQANDST)
6444 #define G_FW_IQ_CMD_IQANDST(x)		\
6445     (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST)
6446 #define F_FW_IQ_CMD_IQANDST		V_FW_IQ_CMD_IQANDST(1U)
6450 #define V_FW_IQ_CMD_IQANUS(x)		((x) << S_FW_IQ_CMD_IQANUS)
6451 #define G_FW_IQ_CMD_IQANUS(x)		\
6452     (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS)
6453 #define F_FW_IQ_CMD_IQANUS		V_FW_IQ_CMD_IQANUS(1U)
6457 #define V_FW_IQ_CMD_IQANUD(x)		((x) << S_FW_IQ_CMD_IQANUD)
6458 #define G_FW_IQ_CMD_IQANUD(x)		\
6459     (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD)
6463 #define V_FW_IQ_CMD_IQANDSTINDEX(x)	((x) << S_FW_IQ_CMD_IQANDSTINDEX)
6464 #define G_FW_IQ_CMD_IQANDSTINDEX(x)	\
6465     (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX)
6469 #define V_FW_IQ_CMD_IQDROPRSS(x)	((x) << S_FW_IQ_CMD_IQDROPRSS)
6470 #define G_FW_IQ_CMD_IQDROPRSS(x)	\
6471     (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS)
6472 #define F_FW_IQ_CMD_IQDROPRSS		V_FW_IQ_CMD_IQDROPRSS(1U)
6476 #define V_FW_IQ_CMD_IQGTSMODE(x)	((x) << S_FW_IQ_CMD_IQGTSMODE)
6477 #define G_FW_IQ_CMD_IQGTSMODE(x)	\
6478     (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE)
6479 #define F_FW_IQ_CMD_IQGTSMODE		V_FW_IQ_CMD_IQGTSMODE(1U)
6483 #define V_FW_IQ_CMD_IQPCIECH(x)		((x) << S_FW_IQ_CMD_IQPCIECH)
6484 #define G_FW_IQ_CMD_IQPCIECH(x)		\
6485     (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH)
6489 #define V_FW_IQ_CMD_IQDCAEN(x)		((x) << S_FW_IQ_CMD_IQDCAEN)
6490 #define G_FW_IQ_CMD_IQDCAEN(x)		\
6491     (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN)
6492 #define F_FW_IQ_CMD_IQDCAEN		V_FW_IQ_CMD_IQDCAEN(1U)
6496 #define V_FW_IQ_CMD_IQDCACPU(x)		((x) << S_FW_IQ_CMD_IQDCACPU)
6497 #define G_FW_IQ_CMD_IQDCACPU(x)		\
6498     (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU)
6502 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x)	((x) << S_FW_IQ_CMD_IQINTCNTTHRESH)
6503 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x)	\
6504     (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH)
6508 #define V_FW_IQ_CMD_IQO(x)		((x) << S_FW_IQ_CMD_IQO)
6509 #define G_FW_IQ_CMD_IQO(x)		\
6510     (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO)
6511 #define F_FW_IQ_CMD_IQO			V_FW_IQ_CMD_IQO(1U)
6515 #define V_FW_IQ_CMD_IQCPRIO(x)		((x) << S_FW_IQ_CMD_IQCPRIO)
6516 #define G_FW_IQ_CMD_IQCPRIO(x)		\
6517     (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO)
6518 #define F_FW_IQ_CMD_IQCPRIO		V_FW_IQ_CMD_IQCPRIO(1U)
6522 #define V_FW_IQ_CMD_IQESIZE(x)		((x) << S_FW_IQ_CMD_IQESIZE)
6523 #define G_FW_IQ_CMD_IQESIZE(x)		\
6524     (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE)
6528 #define V_FW_IQ_CMD_IQNS(x)		((x) << S_FW_IQ_CMD_IQNS)
6529 #define G_FW_IQ_CMD_IQNS(x)		\
6530     (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS)
6531 #define F_FW_IQ_CMD_IQNS		V_FW_IQ_CMD_IQNS(1U)
6535 #define V_FW_IQ_CMD_IQRO(x)		((x) << S_FW_IQ_CMD_IQRO)
6536 #define G_FW_IQ_CMD_IQRO(x)		\
6537     (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO)
6538 #define F_FW_IQ_CMD_IQRO		V_FW_IQ_CMD_IQRO(1U)
6542 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x)	((x) << S_FW_IQ_CMD_IQFLINTIQHSEN)
6543 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x)	\
6544     (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN)
6548 #define V_FW_IQ_CMD_IQFLINTCONGEN(x)	((x) << S_FW_IQ_CMD_IQFLINTCONGEN)
6549 #define G_FW_IQ_CMD_IQFLINTCONGEN(x)	\
6550     (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN)
6551 #define F_FW_IQ_CMD_IQFLINTCONGEN	V_FW_IQ_CMD_IQFLINTCONGEN(1U)
6555 #define V_FW_IQ_CMD_IQFLINTISCSIC(x)	((x) << S_FW_IQ_CMD_IQFLINTISCSIC)
6556 #define G_FW_IQ_CMD_IQFLINTISCSIC(x)	\
6557     (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC)
6558 #define F_FW_IQ_CMD_IQFLINTISCSIC	V_FW_IQ_CMD_IQFLINTISCSIC(1U)
6562 #define V_FW_IQ_CMD_IQTYPE(x)	((x) << S_FW_IQ_CMD_IQTYPE)
6563 #define G_FW_IQ_CMD_IQTYPE(x)	\
6564     (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE)
6568 #define V_FW_IQ_CMD_FL0CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL0CNGCHMAP)
6569 #define G_FW_IQ_CMD_FL0CNGCHMAP(x)	\
6570     (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP)
6574 #define V_FW_IQ_CMD_FL0CONGDROP(x)	((x) << S_FW_IQ_CMD_FL0CONGDROP)
6575 #define G_FW_IQ_CMD_FL0CONGDROP(x)	\
6576     (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP)
6577 #define F_FW_IQ_CMD_FL0CONGDROP		V_FW_IQ_CMD_FL0CONGDROP(1U)
6581 #define V_FW_IQ_CMD_FL0CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL0CACHELOCK)
6582 #define G_FW_IQ_CMD_FL0CACHELOCK(x)	\
6583     (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK)
6584 #define F_FW_IQ_CMD_FL0CACHELOCK	V_FW_IQ_CMD_FL0CACHELOCK(1U)
6588 #define V_FW_IQ_CMD_FL0DBP(x)		((x) << S_FW_IQ_CMD_FL0DBP)
6589 #define G_FW_IQ_CMD_FL0DBP(x)		\
6590     (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP)
6591 #define F_FW_IQ_CMD_FL0DBP		V_FW_IQ_CMD_FL0DBP(1U)
6595 #define V_FW_IQ_CMD_FL0DATANS(x)	((x) << S_FW_IQ_CMD_FL0DATANS)
6596 #define G_FW_IQ_CMD_FL0DATANS(x)	\
6597     (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS)
6598 #define F_FW_IQ_CMD_FL0DATANS		V_FW_IQ_CMD_FL0DATANS(1U)
6602 #define V_FW_IQ_CMD_FL0DATARO(x)	((x) << S_FW_IQ_CMD_FL0DATARO)
6603 #define G_FW_IQ_CMD_FL0DATARO(x)	\
6604     (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO)
6605 #define F_FW_IQ_CMD_FL0DATARO		V_FW_IQ_CMD_FL0DATARO(1U)
6609 #define V_FW_IQ_CMD_FL0CONGCIF(x)	((x) << S_FW_IQ_CMD_FL0CONGCIF)
6610 #define G_FW_IQ_CMD_FL0CONGCIF(x)	\
6611     (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF)
6612 #define F_FW_IQ_CMD_FL0CONGCIF		V_FW_IQ_CMD_FL0CONGCIF(1U)
6616 #define V_FW_IQ_CMD_FL0ONCHIP(x)	((x) << S_FW_IQ_CMD_FL0ONCHIP)
6617 #define G_FW_IQ_CMD_FL0ONCHIP(x)	\
6618     (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP)
6619 #define F_FW_IQ_CMD_FL0ONCHIP		V_FW_IQ_CMD_FL0ONCHIP(1U)
6623 #define V_FW_IQ_CMD_FL0STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGNS)
6624 #define G_FW_IQ_CMD_FL0STATUSPGNS(x)	\
6625     (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS)
6626 #define F_FW_IQ_CMD_FL0STATUSPGNS	V_FW_IQ_CMD_FL0STATUSPGNS(1U)
6630 #define V_FW_IQ_CMD_FL0STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL0STATUSPGRO)
6631 #define G_FW_IQ_CMD_FL0STATUSPGRO(x)	\
6632     (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO)
6633 #define F_FW_IQ_CMD_FL0STATUSPGRO	V_FW_IQ_CMD_FL0STATUSPGRO(1U)
6637 #define V_FW_IQ_CMD_FL0FETCHNS(x)	((x) << S_FW_IQ_CMD_FL0FETCHNS)
6638 #define G_FW_IQ_CMD_FL0FETCHNS(x)	\
6639     (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS)
6640 #define F_FW_IQ_CMD_FL0FETCHNS		V_FW_IQ_CMD_FL0FETCHNS(1U)
6644 #define V_FW_IQ_CMD_FL0FETCHRO(x)	((x) << S_FW_IQ_CMD_FL0FETCHRO)
6645 #define G_FW_IQ_CMD_FL0FETCHRO(x)	\
6646     (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO)
6647 #define F_FW_IQ_CMD_FL0FETCHRO		V_FW_IQ_CMD_FL0FETCHRO(1U)
6651 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL0HOSTFCMODE)
6652 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x)	\
6653     (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE)
6657 #define V_FW_IQ_CMD_FL0CPRIO(x)		((x) << S_FW_IQ_CMD_FL0CPRIO)
6658 #define G_FW_IQ_CMD_FL0CPRIO(x)		\
6659     (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO)
6660 #define F_FW_IQ_CMD_FL0CPRIO		V_FW_IQ_CMD_FL0CPRIO(1U)
6664 #define V_FW_IQ_CMD_FL0PADEN(x)		((x) << S_FW_IQ_CMD_FL0PADEN)
6665 #define G_FW_IQ_CMD_FL0PADEN(x)		\
6666     (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN)
6667 #define F_FW_IQ_CMD_FL0PADEN		V_FW_IQ_CMD_FL0PADEN(1U)
6669 #define S_FW_IQ_CMD_FL0PACKEN		1
6671 #define V_FW_IQ_CMD_FL0PACKEN(x)	((x) << S_FW_IQ_CMD_FL0PACKEN)
6672 #define G_FW_IQ_CMD_FL0PACKEN(x)	\
6673     (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN)
6674 #define F_FW_IQ_CMD_FL0PACKEN		V_FW_IQ_CMD_FL0PACKEN(1U)
6678 #define V_FW_IQ_CMD_FL0CONGEN(x)	((x) << S_FW_IQ_CMD_FL0CONGEN)
6679 #define G_FW_IQ_CMD_FL0CONGEN(x)	\
6680     (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN)
6681 #define F_FW_IQ_CMD_FL0CONGEN		V_FW_IQ_CMD_FL0CONGEN(1U)
6685 #define V_FW_IQ_CMD_FL0DCAEN(x)		((x) << S_FW_IQ_CMD_FL0DCAEN)
6686 #define G_FW_IQ_CMD_FL0DCAEN(x)		\
6687     (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN)
6688 #define F_FW_IQ_CMD_FL0DCAEN		V_FW_IQ_CMD_FL0DCAEN(1U)
6692 #define V_FW_IQ_CMD_FL0DCACPU(x)	((x) << S_FW_IQ_CMD_FL0DCACPU)
6693 #define G_FW_IQ_CMD_FL0DCACPU(x)	\
6694     (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU)
6698 #define V_FW_IQ_CMD_FL0FBMIN(x)		((x) << S_FW_IQ_CMD_FL0FBMIN)
6699 #define G_FW_IQ_CMD_FL0FBMIN(x)		\
6700     (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN)
6704 #define V_FW_IQ_CMD_FL0FBMAX(x)		((x) << S_FW_IQ_CMD_FL0FBMAX)
6705 #define G_FW_IQ_CMD_FL0FBMAX(x)		\
6706     (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX)
6710 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO)
6711 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x)	\
6712     (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO)
6713 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO	V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U)
6717 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH)
6718 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x)	\
6719     (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH)
6723 #define V_FW_IQ_CMD_FL1CNGCHMAP(x)	((x) << S_FW_IQ_CMD_FL1CNGCHMAP)
6724 #define G_FW_IQ_CMD_FL1CNGCHMAP(x)	\
6725     (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP)
6729 #define V_FW_IQ_CMD_FL1CONGDROP(x)	((x) << S_FW_IQ_CMD_FL1CONGDROP)
6730 #define G_FW_IQ_CMD_FL1CONGDROP(x)	\
6731     (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP)
6732 #define F_FW_IQ_CMD_FL1CONGDROP		V_FW_IQ_CMD_FL1CONGDROP(1U)
6736 #define V_FW_IQ_CMD_FL1CACHELOCK(x)	((x) << S_FW_IQ_CMD_FL1CACHELOCK)
6737 #define G_FW_IQ_CMD_FL1CACHELOCK(x)	\
6738     (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK)
6739 #define F_FW_IQ_CMD_FL1CACHELOCK	V_FW_IQ_CMD_FL1CACHELOCK(1U)
6743 #define V_FW_IQ_CMD_FL1DBP(x)		((x) << S_FW_IQ_CMD_FL1DBP)
6744 #define G_FW_IQ_CMD_FL1DBP(x)		\
6745     (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP)
6746 #define F_FW_IQ_CMD_FL1DBP		V_FW_IQ_CMD_FL1DBP(1U)
6750 #define V_FW_IQ_CMD_FL1DATANS(x)	((x) << S_FW_IQ_CMD_FL1DATANS)
6751 #define G_FW_IQ_CMD_FL1DATANS(x)	\
6752     (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS)
6753 #define F_FW_IQ_CMD_FL1DATANS		V_FW_IQ_CMD_FL1DATANS(1U)
6757 #define V_FW_IQ_CMD_FL1DATARO(x)	((x) << S_FW_IQ_CMD_FL1DATARO)
6758 #define G_FW_IQ_CMD_FL1DATARO(x)	\
6759     (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO)
6760 #define F_FW_IQ_CMD_FL1DATARO		V_FW_IQ_CMD_FL1DATARO(1U)
6764 #define V_FW_IQ_CMD_FL1CONGCIF(x)	((x) << S_FW_IQ_CMD_FL1CONGCIF)
6765 #define G_FW_IQ_CMD_FL1CONGCIF(x)	\
6766     (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF)
6767 #define F_FW_IQ_CMD_FL1CONGCIF		V_FW_IQ_CMD_FL1CONGCIF(1U)
6771 #define V_FW_IQ_CMD_FL1ONCHIP(x)	((x) << S_FW_IQ_CMD_FL1ONCHIP)
6772 #define G_FW_IQ_CMD_FL1ONCHIP(x)	\
6773     (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP)
6774 #define F_FW_IQ_CMD_FL1ONCHIP		V_FW_IQ_CMD_FL1ONCHIP(1U)
6778 #define V_FW_IQ_CMD_FL1STATUSPGNS(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGNS)
6779 #define G_FW_IQ_CMD_FL1STATUSPGNS(x)	\
6780     (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS)
6781 #define F_FW_IQ_CMD_FL1STATUSPGNS	V_FW_IQ_CMD_FL1STATUSPGNS(1U)
6785 #define V_FW_IQ_CMD_FL1STATUSPGRO(x)	((x) << S_FW_IQ_CMD_FL1STATUSPGRO)
6786 #define G_FW_IQ_CMD_FL1STATUSPGRO(x)	\
6787     (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO)
6788 #define F_FW_IQ_CMD_FL1STATUSPGRO	V_FW_IQ_CMD_FL1STATUSPGRO(1U)
6792 #define V_FW_IQ_CMD_FL1FETCHNS(x)	((x) << S_FW_IQ_CMD_FL1FETCHNS)
6793 #define G_FW_IQ_CMD_FL1FETCHNS(x)	\
6794     (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS)
6795 #define F_FW_IQ_CMD_FL1FETCHNS		V_FW_IQ_CMD_FL1FETCHNS(1U)
6799 #define V_FW_IQ_CMD_FL1FETCHRO(x)	((x) << S_FW_IQ_CMD_FL1FETCHRO)
6800 #define G_FW_IQ_CMD_FL1FETCHRO(x)	\
6801     (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO)
6802 #define F_FW_IQ_CMD_FL1FETCHRO		V_FW_IQ_CMD_FL1FETCHRO(1U)
6806 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x)	((x) << S_FW_IQ_CMD_FL1HOSTFCMODE)
6807 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x)	\
6808     (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE)
6812 #define V_FW_IQ_CMD_FL1CPRIO(x)		((x) << S_FW_IQ_CMD_FL1CPRIO)
6813 #define G_FW_IQ_CMD_FL1CPRIO(x)		\
6814     (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO)
6815 #define F_FW_IQ_CMD_FL1CPRIO		V_FW_IQ_CMD_FL1CPRIO(1U)
6819 #define V_FW_IQ_CMD_FL1PADEN(x)		((x) << S_FW_IQ_CMD_FL1PADEN)
6820 #define G_FW_IQ_CMD_FL1PADEN(x)		\
6821     (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN)
6822 #define F_FW_IQ_CMD_FL1PADEN		V_FW_IQ_CMD_FL1PADEN(1U)
6824 #define S_FW_IQ_CMD_FL1PACKEN		1
6826 #define V_FW_IQ_CMD_FL1PACKEN(x)	((x) << S_FW_IQ_CMD_FL1PACKEN)
6827 #define G_FW_IQ_CMD_FL1PACKEN(x)	\
6828     (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN)
6829 #define F_FW_IQ_CMD_FL1PACKEN		V_FW_IQ_CMD_FL1PACKEN(1U)
6833 #define V_FW_IQ_CMD_FL1CONGEN(x)	((x) << S_FW_IQ_CMD_FL1CONGEN)
6834 #define G_FW_IQ_CMD_FL1CONGEN(x)	\
6835     (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN)
6836 #define F_FW_IQ_CMD_FL1CONGEN		V_FW_IQ_CMD_FL1CONGEN(1U)
6840 #define V_FW_IQ_CMD_FL1DCAEN(x)		((x) << S_FW_IQ_CMD_FL1DCAEN)
6841 #define G_FW_IQ_CMD_FL1DCAEN(x)		\
6842     (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN)
6843 #define F_FW_IQ_CMD_FL1DCAEN		V_FW_IQ_CMD_FL1DCAEN(1U)
6847 #define V_FW_IQ_CMD_FL1DCACPU(x)	((x) << S_FW_IQ_CMD_FL1DCACPU)
6848 #define G_FW_IQ_CMD_FL1DCACPU(x)	\
6849     (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU)
6853 #define V_FW_IQ_CMD_FL1FBMIN(x)		((x) << S_FW_IQ_CMD_FL1FBMIN)
6854 #define G_FW_IQ_CMD_FL1FBMIN(x)		\
6855     (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN)
6859 #define V_FW_IQ_CMD_FL1FBMAX(x)		((x) << S_FW_IQ_CMD_FL1FBMAX)
6860 #define G_FW_IQ_CMD_FL1FBMAX(x)		\
6861     (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX)
6865 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO)
6866 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x)	\
6867     (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO)
6868 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO	V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U)
6872 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x)	((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH)
6873 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x)	\
6874     (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH)
6888 #define V_FW_EQ_MNGT_CMD_PFN(x)		((x) << S_FW_EQ_MNGT_CMD_PFN)
6889 #define G_FW_EQ_MNGT_CMD_PFN(x)		\
6890     (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN)
6894 #define V_FW_EQ_MNGT_CMD_VFN(x)		((x) << S_FW_EQ_MNGT_CMD_VFN)
6895 #define G_FW_EQ_MNGT_CMD_VFN(x)		\
6896     (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN)
6900 #define V_FW_EQ_MNGT_CMD_ALLOC(x)	((x) << S_FW_EQ_MNGT_CMD_ALLOC)
6901 #define G_FW_EQ_MNGT_CMD_ALLOC(x)	\
6902     (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC)
6903 #define F_FW_EQ_MNGT_CMD_ALLOC		V_FW_EQ_MNGT_CMD_ALLOC(1U)
6907 #define V_FW_EQ_MNGT_CMD_FREE(x)	((x) << S_FW_EQ_MNGT_CMD_FREE)
6908 #define G_FW_EQ_MNGT_CMD_FREE(x)	\
6909     (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE)
6910 #define F_FW_EQ_MNGT_CMD_FREE		V_FW_EQ_MNGT_CMD_FREE(1U)
6914 #define V_FW_EQ_MNGT_CMD_MODIFY(x)	((x) << S_FW_EQ_MNGT_CMD_MODIFY)
6915 #define G_FW_EQ_MNGT_CMD_MODIFY(x)	\
6916     (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY)
6917 #define F_FW_EQ_MNGT_CMD_MODIFY		V_FW_EQ_MNGT_CMD_MODIFY(1U)
6921 #define V_FW_EQ_MNGT_CMD_EQSTART(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTART)
6922 #define G_FW_EQ_MNGT_CMD_EQSTART(x)	\
6923     (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART)
6924 #define F_FW_EQ_MNGT_CMD_EQSTART	V_FW_EQ_MNGT_CMD_EQSTART(1U)
6928 #define V_FW_EQ_MNGT_CMD_EQSTOP(x)	((x) << S_FW_EQ_MNGT_CMD_EQSTOP)
6929 #define G_FW_EQ_MNGT_CMD_EQSTOP(x)	\
6930     (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP)
6931 #define F_FW_EQ_MNGT_CMD_EQSTOP		V_FW_EQ_MNGT_CMD_EQSTOP(1U)
6935 #define V_FW_EQ_MNGT_CMD_COREGROUP(x)	((x) << S_FW_EQ_MNGT_CMD_COREGROUP)
6936 #define G_FW_EQ_MNGT_CMD_COREGROUP(x)	\
6937     (((x) >> S_FW_EQ_MNGT_CMD_COREGROUP) & M_FW_EQ_MNGT_CMD_COREGROUP)
6941 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x)	((x) << S_FW_EQ_MNGT_CMD_CMPLIQID)
6942 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x)	\
6943     (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID)
6947 #define V_FW_EQ_MNGT_CMD_EQID(x)	((x) << S_FW_EQ_MNGT_CMD_EQID)
6948 #define G_FW_EQ_MNGT_CMD_EQID(x)	\
6949     (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID)
6953 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x)	((x) << S_FW_EQ_MNGT_CMD_PHYSEQID)
6954 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x)	\
6955     (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID)
6959 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHSZM)
6960 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x)	\
6961     (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM)
6962 #define F_FW_EQ_MNGT_CMD_FETCHSZM	V_FW_EQ_MNGT_CMD_FETCHSZM(1U)
6966 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS)
6967 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x)	\
6968     (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS)
6969 #define F_FW_EQ_MNGT_CMD_STATUSPGNS	V_FW_EQ_MNGT_CMD_STATUSPGNS(1U)
6973 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO)
6974 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x)	\
6975     (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO)
6976 #define F_FW_EQ_MNGT_CMD_STATUSPGRO	V_FW_EQ_MNGT_CMD_STATUSPGRO(1U)
6980 #define V_FW_EQ_MNGT_CMD_FETCHNS(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHNS)
6981 #define G_FW_EQ_MNGT_CMD_FETCHNS(x)	\
6982     (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS)
6983 #define F_FW_EQ_MNGT_CMD_FETCHNS	V_FW_EQ_MNGT_CMD_FETCHNS(1U)
6987 #define V_FW_EQ_MNGT_CMD_FETCHRO(x)	((x) << S_FW_EQ_MNGT_CMD_FETCHRO)
6988 #define G_FW_EQ_MNGT_CMD_FETCHRO(x)	\
6989     (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO)
6990 #define F_FW_EQ_MNGT_CMD_FETCHRO	V_FW_EQ_MNGT_CMD_FETCHRO(1U)
6994 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE)
6995 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x)	\
6996     (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE)
7000 #define V_FW_EQ_MNGT_CMD_CPRIO(x)	((x) << S_FW_EQ_MNGT_CMD_CPRIO)
7001 #define G_FW_EQ_MNGT_CMD_CPRIO(x)	\
7002     (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO)
7003 #define F_FW_EQ_MNGT_CMD_CPRIO		V_FW_EQ_MNGT_CMD_CPRIO(1U)
7007 #define V_FW_EQ_MNGT_CMD_ONCHIP(x)	((x) << S_FW_EQ_MNGT_CMD_ONCHIP)
7008 #define G_FW_EQ_MNGT_CMD_ONCHIP(x)	\
7009     (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP)
7010 #define F_FW_EQ_MNGT_CMD_ONCHIP		V_FW_EQ_MNGT_CMD_ONCHIP(1U)
7014 #define V_FW_EQ_MNGT_CMD_PCIECHN(x)	((x) << S_FW_EQ_MNGT_CMD_PCIECHN)
7015 #define G_FW_EQ_MNGT_CMD_PCIECHN(x)	\
7016     (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN)
7020 #define V_FW_EQ_MNGT_CMD_IQID(x)	((x) << S_FW_EQ_MNGT_CMD_IQID)
7021 #define G_FW_EQ_MNGT_CMD_IQID(x)	\
7022     (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID)
7026 #define V_FW_EQ_MNGT_CMD_DCAEN(x)	((x) << S_FW_EQ_MNGT_CMD_DCAEN)
7027 #define G_FW_EQ_MNGT_CMD_DCAEN(x)	\
7028     (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN)
7029 #define F_FW_EQ_MNGT_CMD_DCAEN		V_FW_EQ_MNGT_CMD_DCAEN(1U)
7033 #define V_FW_EQ_MNGT_CMD_DCACPU(x)	((x) << S_FW_EQ_MNGT_CMD_DCACPU)
7034 #define G_FW_EQ_MNGT_CMD_DCACPU(x)	\
7035     (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU)
7039 #define V_FW_EQ_MNGT_CMD_FBMIN(x)	((x) << S_FW_EQ_MNGT_CMD_FBMIN)
7040 #define G_FW_EQ_MNGT_CMD_FBMIN(x)	\
7041     (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN)
7045 #define V_FW_EQ_MNGT_CMD_FBMAX(x)	((x) << S_FW_EQ_MNGT_CMD_FBMAX)
7046 #define G_FW_EQ_MNGT_CMD_FBMAX(x)	\
7047     (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX)
7051 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
7052     ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
7053 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \
7054     (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO)
7055 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO	V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U)
7059 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH)
7060 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x)	\
7061     (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH)
7065 #define V_FW_EQ_MNGT_CMD_EQSIZE(x)	((x) << S_FW_EQ_MNGT_CMD_EQSIZE)
7066 #define G_FW_EQ_MNGT_CMD_EQSIZE(x)	\
7067     (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE)
7084 #define V_FW_EQ_ETH_CMD_PFN(x)		((x) << S_FW_EQ_ETH_CMD_PFN)
7085 #define G_FW_EQ_ETH_CMD_PFN(x)		\
7086     (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN)
7090 #define V_FW_EQ_ETH_CMD_VFN(x)		((x) << S_FW_EQ_ETH_CMD_VFN)
7091 #define G_FW_EQ_ETH_CMD_VFN(x)		\
7092     (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN)
7096 #define V_FW_EQ_ETH_CMD_ALLOC(x)	((x) << S_FW_EQ_ETH_CMD_ALLOC)
7097 #define G_FW_EQ_ETH_CMD_ALLOC(x)	\
7098     (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC)
7099 #define F_FW_EQ_ETH_CMD_ALLOC		V_FW_EQ_ETH_CMD_ALLOC(1U)
7103 #define V_FW_EQ_ETH_CMD_FREE(x)		((x) << S_FW_EQ_ETH_CMD_FREE)
7104 #define G_FW_EQ_ETH_CMD_FREE(x)		\
7105     (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE)
7106 #define F_FW_EQ_ETH_CMD_FREE		V_FW_EQ_ETH_CMD_FREE(1U)
7110 #define V_FW_EQ_ETH_CMD_MODIFY(x)	((x) << S_FW_EQ_ETH_CMD_MODIFY)
7111 #define G_FW_EQ_ETH_CMD_MODIFY(x)	\
7112     (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY)
7113 #define F_FW_EQ_ETH_CMD_MODIFY		V_FW_EQ_ETH_CMD_MODIFY(1U)
7117 #define V_FW_EQ_ETH_CMD_EQSTART(x)	((x) << S_FW_EQ_ETH_CMD_EQSTART)
7118 #define G_FW_EQ_ETH_CMD_EQSTART(x)	\
7119     (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART)
7120 #define F_FW_EQ_ETH_CMD_EQSTART		V_FW_EQ_ETH_CMD_EQSTART(1U)
7124 #define V_FW_EQ_ETH_CMD_EQSTOP(x)	((x) << S_FW_EQ_ETH_CMD_EQSTOP)
7125 #define G_FW_EQ_ETH_CMD_EQSTOP(x)	\
7126     (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP)
7127 #define F_FW_EQ_ETH_CMD_EQSTOP		V_FW_EQ_ETH_CMD_EQSTOP(1U)
7131 #define V_FW_EQ_ETH_CMD_COREGROUP(x)	((x) << S_FW_EQ_ETH_CMD_COREGROUP)
7132 #define G_FW_EQ_ETH_CMD_COREGROUP(x)	\
7133     (((x) >> S_FW_EQ_ETH_CMD_COREGROUP) & M_FW_EQ_ETH_CMD_COREGROUP)
7137 #define V_FW_EQ_ETH_CMD_EQID(x)		((x) << S_FW_EQ_ETH_CMD_EQID)
7138 #define G_FW_EQ_ETH_CMD_EQID(x)		\
7139     (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID)
7143 #define V_FW_EQ_ETH_CMD_PHYSEQID(x)	((x) << S_FW_EQ_ETH_CMD_PHYSEQID)
7144 #define G_FW_EQ_ETH_CMD_PHYSEQID(x)	\
7145     (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID)
7149 #define V_FW_EQ_ETH_CMD_FETCHSZM(x)	((x) << S_FW_EQ_ETH_CMD_FETCHSZM)
7150 #define G_FW_EQ_ETH_CMD_FETCHSZM(x)	\
7151     (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM)
7152 #define F_FW_EQ_ETH_CMD_FETCHSZM	V_FW_EQ_ETH_CMD_FETCHSZM(1U)
7156 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGNS)
7157 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x)	\
7158     (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS)
7159 #define F_FW_EQ_ETH_CMD_STATUSPGNS	V_FW_EQ_ETH_CMD_STATUSPGNS(1U)
7163 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_ETH_CMD_STATUSPGRO)
7164 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x)	\
7165     (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO)
7166 #define F_FW_EQ_ETH_CMD_STATUSPGRO	V_FW_EQ_ETH_CMD_STATUSPGRO(1U)
7170 #define V_FW_EQ_ETH_CMD_FETCHNS(x)	((x) << S_FW_EQ_ETH_CMD_FETCHNS)
7171 #define G_FW_EQ_ETH_CMD_FETCHNS(x)	\
7172     (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS)
7173 #define F_FW_EQ_ETH_CMD_FETCHNS		V_FW_EQ_ETH_CMD_FETCHNS(1U)
7177 #define V_FW_EQ_ETH_CMD_FETCHRO(x)	((x) << S_FW_EQ_ETH_CMD_FETCHRO)
7178 #define G_FW_EQ_ETH_CMD_FETCHRO(x)	\
7179     (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO)
7180 #define F_FW_EQ_ETH_CMD_FETCHRO		V_FW_EQ_ETH_CMD_FETCHRO(1U)
7184 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE)
7185 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x)	\
7186     (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE)
7190 #define V_FW_EQ_ETH_CMD_CPRIO(x)	((x) << S_FW_EQ_ETH_CMD_CPRIO)
7191 #define G_FW_EQ_ETH_CMD_CPRIO(x)	\
7192     (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO)
7193 #define F_FW_EQ_ETH_CMD_CPRIO		V_FW_EQ_ETH_CMD_CPRIO(1U)
7197 #define V_FW_EQ_ETH_CMD_ONCHIP(x)	((x) << S_FW_EQ_ETH_CMD_ONCHIP)
7198 #define G_FW_EQ_ETH_CMD_ONCHIP(x)	\
7199     (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP)
7200 #define F_FW_EQ_ETH_CMD_ONCHIP		V_FW_EQ_ETH_CMD_ONCHIP(1U)
7204 #define V_FW_EQ_ETH_CMD_PCIECHN(x)	((x) << S_FW_EQ_ETH_CMD_PCIECHN)
7205 #define G_FW_EQ_ETH_CMD_PCIECHN(x)	\
7206     (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN)
7210 #define V_FW_EQ_ETH_CMD_IQID(x)		((x) << S_FW_EQ_ETH_CMD_IQID)
7211 #define G_FW_EQ_ETH_CMD_IQID(x)		\
7212     (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID)
7216 #define V_FW_EQ_ETH_CMD_DCAEN(x)	((x) << S_FW_EQ_ETH_CMD_DCAEN)
7217 #define G_FW_EQ_ETH_CMD_DCAEN(x)	\
7218     (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN)
7219 #define F_FW_EQ_ETH_CMD_DCAEN		V_FW_EQ_ETH_CMD_DCAEN(1U)
7223 #define V_FW_EQ_ETH_CMD_DCACPU(x)	((x) << S_FW_EQ_ETH_CMD_DCACPU)
7224 #define G_FW_EQ_ETH_CMD_DCACPU(x)	\
7225     (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU)
7229 #define V_FW_EQ_ETH_CMD_FBMIN(x)	((x) << S_FW_EQ_ETH_CMD_FBMIN)
7230 #define G_FW_EQ_ETH_CMD_FBMIN(x)	\
7231     (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN)
7235 #define V_FW_EQ_ETH_CMD_FBMAX(x)	((x) << S_FW_EQ_ETH_CMD_FBMAX)
7236 #define G_FW_EQ_ETH_CMD_FBMAX(x)	\
7237     (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX)
7241 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO)
7242 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x)	\
7243     (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO)
7244 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO	V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U)
7248 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH)
7249 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x)	\
7250     (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH)
7254 #define V_FW_EQ_ETH_CMD_EQSIZE(x)	((x) << S_FW_EQ_ETH_CMD_EQSIZE)
7255 #define G_FW_EQ_ETH_CMD_EQSIZE(x)	\
7256     (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
7260 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x)	((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)
7261 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x)	\
7262     (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)
7263 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE	V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)
7267 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x)	((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
7268 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x)	\
7269     (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
7270 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE	V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
7274 #define V_FW_EQ_ETH_CMD_VIID(x)		((x) << S_FW_EQ_ETH_CMD_VIID)
7275 #define G_FW_EQ_ETH_CMD_VIID(x)		\
7276     (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID)
7280 #define V_FW_EQ_ETH_CMD_TIMEREN(x)	((x) << S_FW_EQ_ETH_CMD_TIMEREN)
7281 #define G_FW_EQ_ETH_CMD_TIMEREN(x)	\
7282     (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN)
7283 #define F_FW_EQ_ETH_CMD_TIMEREN	V_FW_EQ_ETH_CMD_TIMEREN(1U)
7287 #define V_FW_EQ_ETH_CMD_TIMERIX(x)	((x) << S_FW_EQ_ETH_CMD_TIMERIX)
7288 #define G_FW_EQ_ETH_CMD_TIMERIX(x)	\
7289     (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX)
7303 #define V_FW_EQ_CTRL_CMD_PFN(x)		((x) << S_FW_EQ_CTRL_CMD_PFN)
7304 #define G_FW_EQ_CTRL_CMD_PFN(x)		\
7305     (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN)
7309 #define V_FW_EQ_CTRL_CMD_VFN(x)		((x) << S_FW_EQ_CTRL_CMD_VFN)
7310 #define G_FW_EQ_CTRL_CMD_VFN(x)		\
7311     (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN)
7315 #define V_FW_EQ_CTRL_CMD_ALLOC(x)	((x) << S_FW_EQ_CTRL_CMD_ALLOC)
7316 #define G_FW_EQ_CTRL_CMD_ALLOC(x)	\
7317     (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC)
7318 #define F_FW_EQ_CTRL_CMD_ALLOC		V_FW_EQ_CTRL_CMD_ALLOC(1U)
7322 #define V_FW_EQ_CTRL_CMD_FREE(x)	((x) << S_FW_EQ_CTRL_CMD_FREE)
7323 #define G_FW_EQ_CTRL_CMD_FREE(x)	\
7324     (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE)
7325 #define F_FW_EQ_CTRL_CMD_FREE		V_FW_EQ_CTRL_CMD_FREE(1U)
7329 #define V_FW_EQ_CTRL_CMD_MODIFY(x)	((x) << S_FW_EQ_CTRL_CMD_MODIFY)
7330 #define G_FW_EQ_CTRL_CMD_MODIFY(x)	\
7331     (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY)
7332 #define F_FW_EQ_CTRL_CMD_MODIFY		V_FW_EQ_CTRL_CMD_MODIFY(1U)
7336 #define V_FW_EQ_CTRL_CMD_EQSTART(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTART)
7337 #define G_FW_EQ_CTRL_CMD_EQSTART(x)	\
7338     (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART)
7339 #define F_FW_EQ_CTRL_CMD_EQSTART	V_FW_EQ_CTRL_CMD_EQSTART(1U)
7343 #define V_FW_EQ_CTRL_CMD_EQSTOP(x)	((x) << S_FW_EQ_CTRL_CMD_EQSTOP)
7344 #define G_FW_EQ_CTRL_CMD_EQSTOP(x)	\
7345     (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP)
7346 #define F_FW_EQ_CTRL_CMD_EQSTOP		V_FW_EQ_CTRL_CMD_EQSTOP(1U)
7350 #define V_FW_EQ_CTRL_CMD_COREGROUP(x)	((x) << S_FW_EQ_CTRL_CMD_COREGROUP)
7351 #define G_FW_EQ_CTRL_CMD_COREGROUP(x)	\
7352     (((x) >> S_FW_EQ_CTRL_CMD_COREGROUP) & M_FW_EQ_CTRL_CMD_COREGROUP)
7356 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x)	((x) << S_FW_EQ_CTRL_CMD_CMPLIQID)
7357 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x)	\
7358     (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID)
7362 #define V_FW_EQ_CTRL_CMD_EQID(x)	((x) << S_FW_EQ_CTRL_CMD_EQID)
7363 #define G_FW_EQ_CTRL_CMD_EQID(x)	\
7364     (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID)
7368 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x)	((x) << S_FW_EQ_CTRL_CMD_PHYSEQID)
7369 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x)	\
7370     (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID)
7374 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHSZM)
7375 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x)	\
7376     (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM)
7377 #define F_FW_EQ_CTRL_CMD_FETCHSZM	V_FW_EQ_CTRL_CMD_FETCHSZM(1U)
7381 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS)
7382 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x)	\
7383     (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS)
7384 #define F_FW_EQ_CTRL_CMD_STATUSPGNS	V_FW_EQ_CTRL_CMD_STATUSPGNS(1U)
7388 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO)
7389 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x)	\
7390     (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO)
7391 #define F_FW_EQ_CTRL_CMD_STATUSPGRO	V_FW_EQ_CTRL_CMD_STATUSPGRO(1U)
7395 #define V_FW_EQ_CTRL_CMD_FETCHNS(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHNS)
7396 #define G_FW_EQ_CTRL_CMD_FETCHNS(x)	\
7397     (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS)
7398 #define F_FW_EQ_CTRL_CMD_FETCHNS	V_FW_EQ_CTRL_CMD_FETCHNS(1U)
7402 #define V_FW_EQ_CTRL_CMD_FETCHRO(x)	((x) << S_FW_EQ_CTRL_CMD_FETCHRO)
7403 #define G_FW_EQ_CTRL_CMD_FETCHRO(x)	\
7404     (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO)
7405 #define F_FW_EQ_CTRL_CMD_FETCHRO	V_FW_EQ_CTRL_CMD_FETCHRO(1U)
7409 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE)
7410 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x)	\
7411     (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE)
7415 #define V_FW_EQ_CTRL_CMD_CPRIO(x)	((x) << S_FW_EQ_CTRL_CMD_CPRIO)
7416 #define G_FW_EQ_CTRL_CMD_CPRIO(x)	\
7417     (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO)
7418 #define F_FW_EQ_CTRL_CMD_CPRIO		V_FW_EQ_CTRL_CMD_CPRIO(1U)
7422 #define V_FW_EQ_CTRL_CMD_ONCHIP(x)	((x) << S_FW_EQ_CTRL_CMD_ONCHIP)
7423 #define G_FW_EQ_CTRL_CMD_ONCHIP(x)	\
7424     (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP)
7425 #define F_FW_EQ_CTRL_CMD_ONCHIP		V_FW_EQ_CTRL_CMD_ONCHIP(1U)
7429 #define V_FW_EQ_CTRL_CMD_PCIECHN(x)	((x) << S_FW_EQ_CTRL_CMD_PCIECHN)
7430 #define G_FW_EQ_CTRL_CMD_PCIECHN(x)	\
7431     (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN)
7435 #define V_FW_EQ_CTRL_CMD_IQID(x)	((x) << S_FW_EQ_CTRL_CMD_IQID)
7436 #define G_FW_EQ_CTRL_CMD_IQID(x)	\
7437     (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID)
7441 #define V_FW_EQ_CTRL_CMD_DCAEN(x)	((x) << S_FW_EQ_CTRL_CMD_DCAEN)
7442 #define G_FW_EQ_CTRL_CMD_DCAEN(x)	\
7443     (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN)
7444 #define F_FW_EQ_CTRL_CMD_DCAEN		V_FW_EQ_CTRL_CMD_DCAEN(1U)
7448 #define V_FW_EQ_CTRL_CMD_DCACPU(x)	((x) << S_FW_EQ_CTRL_CMD_DCACPU)
7449 #define G_FW_EQ_CTRL_CMD_DCACPU(x)	\
7450     (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU)
7454 #define V_FW_EQ_CTRL_CMD_FBMIN(x)	((x) << S_FW_EQ_CTRL_CMD_FBMIN)
7455 #define G_FW_EQ_CTRL_CMD_FBMIN(x)	\
7456     (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN)
7460 #define V_FW_EQ_CTRL_CMD_FBMAX(x)	((x) << S_FW_EQ_CTRL_CMD_FBMAX)
7461 #define G_FW_EQ_CTRL_CMD_FBMAX(x)	\
7462     (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX)
7466 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
7467     ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
7468 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \
7469     (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO)
7470 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO	V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U)
7474 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH)
7475 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x)	\
7476     (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH)
7480 #define V_FW_EQ_CTRL_CMD_EQSIZE(x)	((x) << S_FW_EQ_CTRL_CMD_EQSIZE)
7481 #define G_FW_EQ_CTRL_CMD_EQSIZE(x)	\
7482     (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE)
7496 #define V_FW_EQ_OFLD_CMD_PFN(x)		((x) << S_FW_EQ_OFLD_CMD_PFN)
7497 #define G_FW_EQ_OFLD_CMD_PFN(x)		\
7498     (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN)
7502 #define V_FW_EQ_OFLD_CMD_VFN(x)		((x) << S_FW_EQ_OFLD_CMD_VFN)
7503 #define G_FW_EQ_OFLD_CMD_VFN(x)		\
7504     (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN)
7508 #define V_FW_EQ_OFLD_CMD_ALLOC(x)	((x) << S_FW_EQ_OFLD_CMD_ALLOC)
7509 #define G_FW_EQ_OFLD_CMD_ALLOC(x)	\
7510     (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC)
7511 #define F_FW_EQ_OFLD_CMD_ALLOC		V_FW_EQ_OFLD_CMD_ALLOC(1U)
7515 #define V_FW_EQ_OFLD_CMD_FREE(x)	((x) << S_FW_EQ_OFLD_CMD_FREE)
7516 #define G_FW_EQ_OFLD_CMD_FREE(x)	\
7517     (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE)
7518 #define F_FW_EQ_OFLD_CMD_FREE		V_FW_EQ_OFLD_CMD_FREE(1U)
7522 #define V_FW_EQ_OFLD_CMD_MODIFY(x)	((x) << S_FW_EQ_OFLD_CMD_MODIFY)
7523 #define G_FW_EQ_OFLD_CMD_MODIFY(x)	\
7524     (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY)
7525 #define F_FW_EQ_OFLD_CMD_MODIFY		V_FW_EQ_OFLD_CMD_MODIFY(1U)
7529 #define V_FW_EQ_OFLD_CMD_EQSTART(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTART)
7530 #define G_FW_EQ_OFLD_CMD_EQSTART(x)	\
7531     (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART)
7532 #define F_FW_EQ_OFLD_CMD_EQSTART	V_FW_EQ_OFLD_CMD_EQSTART(1U)
7536 #define V_FW_EQ_OFLD_CMD_EQSTOP(x)	((x) << S_FW_EQ_OFLD_CMD_EQSTOP)
7537 #define G_FW_EQ_OFLD_CMD_EQSTOP(x)	\
7538     (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP)
7539 #define F_FW_EQ_OFLD_CMD_EQSTOP		V_FW_EQ_OFLD_CMD_EQSTOP(1U)
7543 #define V_FW_EQ_OFLD_CMD_COREGROUP(x)	((x) << S_FW_EQ_OFLD_CMD_COREGROUP)
7544 #define G_FW_EQ_OFLD_CMD_COREGROUP(x)	\
7545     (((x) >> S_FW_EQ_OFLD_CMD_COREGROUP) & M_FW_EQ_OFLD_CMD_COREGROUP)
7549 #define V_FW_EQ_OFLD_CMD_EQID(x)	((x) << S_FW_EQ_OFLD_CMD_EQID)
7550 #define G_FW_EQ_OFLD_CMD_EQID(x)	\
7551     (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID)
7555 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x)	((x) << S_FW_EQ_OFLD_CMD_PHYSEQID)
7556 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x)	\
7557     (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID)
7561 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHSZM)
7562 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x)	\
7563     (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM)
7564 #define F_FW_EQ_OFLD_CMD_FETCHSZM	V_FW_EQ_OFLD_CMD_FETCHSZM(1U)
7568 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS)
7569 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x)	\
7570     (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS)
7571 #define F_FW_EQ_OFLD_CMD_STATUSPGNS	V_FW_EQ_OFLD_CMD_STATUSPGNS(1U)
7575 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x)	((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO)
7576 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x)	\
7577     (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO)
7578 #define F_FW_EQ_OFLD_CMD_STATUSPGRO	V_FW_EQ_OFLD_CMD_STATUSPGRO(1U)
7582 #define V_FW_EQ_OFLD_CMD_FETCHNS(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHNS)
7583 #define G_FW_EQ_OFLD_CMD_FETCHNS(x)	\
7584     (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS)
7585 #define F_FW_EQ_OFLD_CMD_FETCHNS	V_FW_EQ_OFLD_CMD_FETCHNS(1U)
7589 #define V_FW_EQ_OFLD_CMD_FETCHRO(x)	((x) << S_FW_EQ_OFLD_CMD_FETCHRO)
7590 #define G_FW_EQ_OFLD_CMD_FETCHRO(x)	\
7591     (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO)
7592 #define F_FW_EQ_OFLD_CMD_FETCHRO	V_FW_EQ_OFLD_CMD_FETCHRO(1U)
7596 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE)
7597 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x)	\
7598     (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE)
7602 #define V_FW_EQ_OFLD_CMD_CPRIO(x)	((x) << S_FW_EQ_OFLD_CMD_CPRIO)
7603 #define G_FW_EQ_OFLD_CMD_CPRIO(x)	\
7604     (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO)
7605 #define F_FW_EQ_OFLD_CMD_CPRIO		V_FW_EQ_OFLD_CMD_CPRIO(1U)
7609 #define V_FW_EQ_OFLD_CMD_ONCHIP(x)	((x) << S_FW_EQ_OFLD_CMD_ONCHIP)
7610 #define G_FW_EQ_OFLD_CMD_ONCHIP(x)	\
7611     (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP)
7612 #define F_FW_EQ_OFLD_CMD_ONCHIP		V_FW_EQ_OFLD_CMD_ONCHIP(1U)
7616 #define V_FW_EQ_OFLD_CMD_PCIECHN(x)	((x) << S_FW_EQ_OFLD_CMD_PCIECHN)
7617 #define G_FW_EQ_OFLD_CMD_PCIECHN(x)	\
7618     (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN)
7622 #define V_FW_EQ_OFLD_CMD_IQID(x)	((x) << S_FW_EQ_OFLD_CMD_IQID)
7623 #define G_FW_EQ_OFLD_CMD_IQID(x)	\
7624     (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID)
7628 #define V_FW_EQ_OFLD_CMD_DCAEN(x)	((x) << S_FW_EQ_OFLD_CMD_DCAEN)
7629 #define G_FW_EQ_OFLD_CMD_DCAEN(x)	\
7630     (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN)
7631 #define F_FW_EQ_OFLD_CMD_DCAEN		V_FW_EQ_OFLD_CMD_DCAEN(1U)
7635 #define V_FW_EQ_OFLD_CMD_DCACPU(x)	((x) << S_FW_EQ_OFLD_CMD_DCACPU)
7636 #define G_FW_EQ_OFLD_CMD_DCACPU(x)	\
7637     (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU)
7641 #define V_FW_EQ_OFLD_CMD_FBMIN(x)	((x) << S_FW_EQ_OFLD_CMD_FBMIN)
7642 #define G_FW_EQ_OFLD_CMD_FBMIN(x)	\
7643     (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN)
7647 #define V_FW_EQ_OFLD_CMD_FBMAX(x)	((x) << S_FW_EQ_OFLD_CMD_FBMAX)
7648 #define G_FW_EQ_OFLD_CMD_FBMAX(x)	\
7649     (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX)
7653 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
7654     ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
7655 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \
7656     (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO)
7657 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO	V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U)
7661 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH)
7662 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x)	\
7663     (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH)
7667 #define V_FW_EQ_OFLD_CMD_EQSIZE(x)	((x) << S_FW_EQ_OFLD_CMD_EQSIZE)
7668 #define G_FW_EQ_OFLD_CMD_EQSIZE(x)	\
7669     (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE)
7677 #define V_FW_VIID_PFN(x)	((x) << S_FW_VIID_PFN)
7678 #define G_FW_VIID_PFN(x)	(((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN)
7682 #define V_FW_VIID_VIVLD(x)	((x) << S_FW_VIID_VIVLD)
7683 #define G_FW_VIID_VIVLD(x)	(((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD)
7687 #define V_FW_VIID_VIN(x)	((x) << S_FW_VIID_VIN)
7688 #define G_FW_VIID_VIN(x)	(((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN)
7694 #define V_FW_256VIID_PFN(x)		((x) << S_FW_256VIID_PFN)
7695 #define G_FW_256VIID_PFN(x)		(((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN)
7699 #define V_FW_256VIID_VIVLD(x)		((x) << S_FW_256VIID_VIVLD)
7700 #define G_FW_256VIID_VIVLD(x)		(((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD)
7704 #define V_FW_256VIID_VIN(x)		((x) << S_FW_256VIID_VIN)
7705 #define G_FW_256VIID_VIN(x)		(((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN)
7738 #define V_FW_VI_CMD_PFN(x)		((x) << S_FW_VI_CMD_PFN)
7739 #define G_FW_VI_CMD_PFN(x)		\
7740     (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN)
7744 #define V_FW_VI_CMD_VFN(x)		((x) << S_FW_VI_CMD_VFN)
7745 #define G_FW_VI_CMD_VFN(x)		\
7746     (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN)
7750 #define V_FW_VI_CMD_ALLOC(x)		((x) << S_FW_VI_CMD_ALLOC)
7751 #define G_FW_VI_CMD_ALLOC(x)		\
7752     (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC)
7753 #define F_FW_VI_CMD_ALLOC		V_FW_VI_CMD_ALLOC(1U)
7757 #define V_FW_VI_CMD_FREE(x)		((x) << S_FW_VI_CMD_FREE)
7758 #define G_FW_VI_CMD_FREE(x)		\
7759     (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE)
7760 #define F_FW_VI_CMD_FREE		V_FW_VI_CMD_FREE(1U)
7764 #define V_FW_VI_CMD_VFVLD(x)		((x) << S_FW_VI_CMD_VFVLD)
7765 #define G_FW_VI_CMD_VFVLD(x)		\
7766     (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD)
7767 #define F_FW_VI_CMD_VFVLD		V_FW_VI_CMD_VFVLD(1U)
7771 #define V_FW_VI_CMD_VIN(x)		((x) << S_FW_VI_CMD_VIN)
7772 #define G_FW_VI_CMD_VIN(x)		\
7773     (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN)
7777 #define V_FW_VI_CMD_TYPE(x)		((x) << S_FW_VI_CMD_TYPE)
7778 #define G_FW_VI_CMD_TYPE(x)		\
7779     (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE)
7780 #define F_FW_VI_CMD_TYPE		V_FW_VI_CMD_TYPE(1U)
7784 #define V_FW_VI_CMD_FUNC(x)		((x) << S_FW_VI_CMD_FUNC)
7785 #define G_FW_VI_CMD_FUNC(x)		\
7786     (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC)
7790 #define V_FW_VI_CMD_VIID(x)		((x) << S_FW_VI_CMD_VIID)
7791 #define G_FW_VI_CMD_VIID(x)		\
7792     (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID)
7796 #define V_FW_VI_CMD_PORTID(x)		((x) << S_FW_VI_CMD_PORTID)
7797 #define G_FW_VI_CMD_PORTID(x)		\
7798     (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID)
7802 #define V_FW_VI_CMD_NORSS(x)		((x) << S_FW_VI_CMD_NORSS)
7803 #define G_FW_VI_CMD_NORSS(x)		\
7804     (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS)
7805 #define F_FW_VI_CMD_NORSS		V_FW_VI_CMD_NORSS(1U)
7809 #define V_FW_VI_CMD_RSSSIZE(x)		((x) << S_FW_VI_CMD_RSSSIZE)
7810 #define G_FW_VI_CMD_RSSSIZE(x)		\
7811     (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE)
7815 #define V_FW_VI_CMD_IDSIIQ(x)		((x) << S_FW_VI_CMD_IDSIIQ)
7816 #define G_FW_VI_CMD_IDSIIQ(x)		\
7817     (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ)
7821 #define V_FW_VI_CMD_IDSEIQ(x)		((x) << S_FW_VI_CMD_IDSEIQ)
7822 #define G_FW_VI_CMD_IDSEIQ(x)		\
7823     (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ)
7883 #define V_FW_VI_MAC_CMD_SMTID(x)	((x) << S_FW_VI_MAC_CMD_SMTID)
7884 #define G_FW_VI_MAC_CMD_SMTID(x)	\
7885     (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID)
7889 #define V_FW_VI_MAC_CMD_VIID(x)		((x) << S_FW_VI_MAC_CMD_VIID)
7890 #define G_FW_VI_MAC_CMD_VIID(x)		\
7891     (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID)
7895 #define V_FW_VI_MAC_CMD_FREEMACS(x)	((x) << S_FW_VI_MAC_CMD_FREEMACS)
7896 #define G_FW_VI_MAC_CMD_FREEMACS(x)	\
7897     (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS)
7898 #define F_FW_VI_MAC_CMD_FREEMACS	V_FW_VI_MAC_CMD_FREEMACS(1U)
7902 #define V_FW_VI_MAC_CMD_IS_SMAC(x)	((x) << S_FW_VI_MAC_CMD_IS_SMAC)
7903 #define G_FW_VI_MAC_CMD_IS_SMAC(x)	\
7904     (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC)
7905 #define F_FW_VI_MAC_CMD_IS_SMAC	V_FW_VI_MAC_CMD_IS_SMAC(1U)
7909 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x)	((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE)
7910 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x)	\
7911     (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE)
7915 #define V_FW_VI_MAC_CMD_HASHUNIEN(x)	((x) << S_FW_VI_MAC_CMD_HASHUNIEN)
7916 #define G_FW_VI_MAC_CMD_HASHUNIEN(x)	\
7917     (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN)
7918 #define F_FW_VI_MAC_CMD_HASHUNIEN	V_FW_VI_MAC_CMD_HASHUNIEN(1U)
7922 #define V_FW_VI_MAC_CMD_VALID(x)	((x) << S_FW_VI_MAC_CMD_VALID)
7923 #define G_FW_VI_MAC_CMD_VALID(x)	\
7924     (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID)
7925 #define F_FW_VI_MAC_CMD_VALID		V_FW_VI_MAC_CMD_VALID(1U)
7929 #define V_FW_VI_MAC_CMD_PRIO(x)		((x) << S_FW_VI_MAC_CMD_PRIO)
7930 #define G_FW_VI_MAC_CMD_PRIO(x)		\
7931     (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO)
7935 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x)	((x) << S_FW_VI_MAC_CMD_SMAC_RESULT)
7936 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x)	\
7937     (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT)
7941 #define V_FW_VI_MAC_CMD_IDX(x)		((x) << S_FW_VI_MAC_CMD_IDX)
7942 #define G_FW_VI_MAC_CMD_IDX(x)		\
7943     (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX)
7947 #define V_FW_VI_MAC_CMD_RAW_IDX(x)	((x) << S_FW_VI_MAC_CMD_RAW_IDX)
7948 #define G_FW_VI_MAC_CMD_RAW_IDX(x)	\
7949     (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX)
7953 #define V_FW_VI_MAC_CMD_DATA0(x)	((x) << S_FW_VI_MAC_CMD_DATA0)
7954 #define G_FW_VI_MAC_CMD_DATA0(x)	\
7955     (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0)
7959 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x)	((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE)
7960 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x)	\
7961     (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE)
7962 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE	V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U)
7966 #define V_FW_VI_MAC_CMD_DIP_HIT(x)	((x) << S_FW_VI_MAC_CMD_DIP_HIT)
7967 #define G_FW_VI_MAC_CMD_DIP_HIT(x)	\
7968     (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT)
7969 #define F_FW_VI_MAC_CMD_DIP_HIT	V_FW_VI_MAC_CMD_DIP_HIT(1U)
7973 #define V_FW_VI_MAC_CMD_VNI(x)	((x) << S_FW_VI_MAC_CMD_VNI)
7974 #define G_FW_VI_MAC_CMD_VNI(x)	\
7975     (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI)
7986 #define V_FW_VI_MAC_CMD_PORT(x)         ((x) << S_FW_VI_MAC_CMD_PORT)
7987 #define G_FW_VI_MAC_CMD_PORT(x)         \
7988     (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT)
7992 #define V_FW_VI_MAC_CMD_VNI_MASK(x)	((x) << S_FW_VI_MAC_CMD_VNI_MASK)
7993 #define G_FW_VI_MAC_CMD_VNI_MASK(x)	\
7994     (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK)
8009 #define V_FW_VI_RXMODE_CMD_VIID(x)	((x) << S_FW_VI_RXMODE_CMD_VIID)
8010 #define G_FW_VI_RXMODE_CMD_VIID(x)	\
8011     (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID)
8015 #define V_FW_VI_RXMODE_CMD_MTU(x)	((x) << S_FW_VI_RXMODE_CMD_MTU)
8016 #define G_FW_VI_RXMODE_CMD_MTU(x)	\
8017     (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU)
8021 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x)	((x) << S_FW_VI_RXMODE_CMD_PROMISCEN)
8022 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x)	\
8023     (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN)
8027 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
8028     ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN)
8029 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \
8030     (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN)
8034 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
8035     ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN)
8036 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \
8037     (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN)
8041 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x)	((x) << S_FW_VI_RXMODE_CMD_VLANEXEN)
8042 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x)	\
8043     (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN)
8055 #define V_FW_VI_ENABLE_CMD_VIID(x)	((x) << S_FW_VI_ENABLE_CMD_VIID)
8056 #define G_FW_VI_ENABLE_CMD_VIID(x)	\
8057     (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID)
8061 #define V_FW_VI_ENABLE_CMD_IEN(x)	((x) << S_FW_VI_ENABLE_CMD_IEN)
8062 #define G_FW_VI_ENABLE_CMD_IEN(x)	\
8063     (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN)
8064 #define F_FW_VI_ENABLE_CMD_IEN		V_FW_VI_ENABLE_CMD_IEN(1U)
8068 #define V_FW_VI_ENABLE_CMD_EEN(x)	((x) << S_FW_VI_ENABLE_CMD_EEN)
8069 #define G_FW_VI_ENABLE_CMD_EEN(x)	\
8070     (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN)
8071 #define F_FW_VI_ENABLE_CMD_EEN		V_FW_VI_ENABLE_CMD_EEN(1U)
8075 #define V_FW_VI_ENABLE_CMD_LED(x)	((x) << S_FW_VI_ENABLE_CMD_LED)
8076 #define G_FW_VI_ENABLE_CMD_LED(x)	\
8077     (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED)
8078 #define F_FW_VI_ENABLE_CMD_LED		V_FW_VI_ENABLE_CMD_LED(1U)
8082 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x)	((x) << S_FW_VI_ENABLE_CMD_DCB_INFO)
8083 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x)	\
8084     (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO)
8085 #define F_FW_VI_ENABLE_CMD_DCB_INFO	V_FW_VI_ENABLE_CMD_DCB_INFO(1U)
8187 #define V_FW_VI_STATS_CMD_VIID(x)	((x) << S_FW_VI_STATS_CMD_VIID)
8188 #define G_FW_VI_STATS_CMD_VIID(x)	\
8189     (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID)
8193 #define V_FW_VI_STATS_CMD_NSTATS(x)	((x) << S_FW_VI_STATS_CMD_NSTATS)
8194 #define G_FW_VI_STATS_CMD_NSTATS(x)	\
8195     (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS)
8199 #define V_FW_VI_STATS_CMD_IX(x)		((x) << S_FW_VI_STATS_CMD_IX)
8200 #define G_FW_VI_STATS_CMD_IX(x)		\
8201     (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX)
8220 #define V_FW_ACL_MAC_CMD_PFN(x)		((x) << S_FW_ACL_MAC_CMD_PFN)
8221 #define G_FW_ACL_MAC_CMD_PFN(x)		\
8222     (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN)
8226 #define V_FW_ACL_MAC_CMD_VFN(x)		((x) << S_FW_ACL_MAC_CMD_VFN)
8227 #define G_FW_ACL_MAC_CMD_VFN(x)		\
8228     (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN)
8232 #define V_FW_ACL_MAC_CMD_EN(x)		((x) << S_FW_ACL_MAC_CMD_EN)
8233 #define G_FW_ACL_MAC_CMD_EN(x)		\
8234     (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN)
8235 #define F_FW_ACL_MAC_CMD_EN		V_FW_ACL_MAC_CMD_EN(1U)
8248 #define V_FW_ACL_VLAN_CMD_PFN(x)	((x) << S_FW_ACL_VLAN_CMD_PFN)
8249 #define G_FW_ACL_VLAN_CMD_PFN(x)	\
8250     (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN)
8254 #define V_FW_ACL_VLAN_CMD_VFN(x)	((x) << S_FW_ACL_VLAN_CMD_VFN)
8255 #define G_FW_ACL_VLAN_CMD_VFN(x)	\
8256     (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN)
8260 #define V_FW_ACL_VLAN_CMD_EN(x)		((x) << S_FW_ACL_VLAN_CMD_EN)
8261 #define G_FW_ACL_VLAN_CMD_EN(x)		\
8262     (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN)
8263 #define F_FW_ACL_VLAN_CMD_EN		V_FW_ACL_VLAN_CMD_EN(1U)
8267 #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
8268     ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT)
8269 #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \
8270     (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT)
8271 #define F_FW_ACL_VLAN_CMD_TRANSPARENT	V_FW_ACL_VLAN_CMD_TRANSPARENT(1U)
8275 #define V_FW_ACL_VLAN_CMD_PMASK(x)	((x) << S_FW_ACL_VLAN_CMD_PMASK)
8276 #define G_FW_ACL_VLAN_CMD_PMASK(x)	\
8277     (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK)
8281 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN)
8282 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x)	\
8283     (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN)
8284 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN	V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U)
8288 #define V_FW_ACL_VLAN_CMD_FM(x)		((x) << S_FW_ACL_VLAN_CMD_FM)
8289 #define G_FW_ACL_VLAN_CMD_FM(x)		\
8290     (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM)
8291 #define F_FW_ACL_VLAN_CMD_FM		V_FW_ACL_VLAN_CMD_FM(1U)
8315 #define V_FW_PORT_CAP_SPEED(x)	((x) << S_FW_PORT_CAP_SPEED)
8316 #define G_FW_PORT_CAP_SPEED(x) \
8317     (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED)
8321 #define V_FW_PORT_CAP_FC(x)	((x) << S_FW_PORT_CAP_FC)
8322 #define G_FW_PORT_CAP_FC(x) \
8323     (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC)
8327 #define V_FW_PORT_CAP_ANEG(x)	((x) << S_FW_PORT_CAP_ANEG)
8328 #define G_FW_PORT_CAP_ANEG(x) \
8329     (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG)
8333 #define V_FW_PORT_CAP_FEC(x)	((x) << S_FW_PORT_CAP_FEC)
8334 #define G_FW_PORT_CAP_FEC(x) \
8335     (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC)
8339 #define V_FW_PORT_CAP_FORCE_PAUSE(x)	((x) << S_FW_PORT_CAP_FORCE_PAUSE)
8340 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \
8341     (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE)
8345 #define V_FW_PORT_CAP_802_3(x)	((x) << S_FW_PORT_CAP_802_3)
8346 #define G_FW_PORT_CAP_802_3(x) \
8347     (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3)
8358 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI)
8359 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI)
8393 #define V_FW_PORT_CAP32_SPEED(x)	((x) << S_FW_PORT_CAP32_SPEED)
8394 #define G_FW_PORT_CAP32_SPEED(x) \
8395     (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED)
8399 #define V_FW_PORT_CAP32_FC(x)	((x) << S_FW_PORT_CAP32_FC)
8400 #define G_FW_PORT_CAP32_FC(x) \
8401     (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC)
8405 #define V_FW_PORT_CAP32_802_3(x)	((x) << S_FW_PORT_CAP32_802_3)
8406 #define G_FW_PORT_CAP32_802_3(x) \
8407     (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3)
8411 #define V_FW_PORT_CAP32_ANEG(x)	((x) << S_FW_PORT_CAP32_ANEG)
8412 #define G_FW_PORT_CAP32_ANEG(x) \
8413     (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG)
8417 #define V_FW_PORT_CAP32_FORCE_PAUSE(x)	((x) << S_FW_PORT_CAP32_FORCE_PAUSE)
8418 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \
8419     (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE)
8430 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI)
8431 #define G_FW_PORT_CAP32_MDI(x) \
8432     (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI)
8436 #define V_FW_PORT_CAP32_FEC(x)	((x) << S_FW_PORT_CAP32_FEC)
8437 #define G_FW_PORT_CAP32_FEC(x) \
8438     (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC)
8653 #define V_FW_PORT_CMD_READ(x)		((x) << S_FW_PORT_CMD_READ)
8654 #define G_FW_PORT_CMD_READ(x)		\
8655     (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ)
8656 #define F_FW_PORT_CMD_READ		V_FW_PORT_CMD_READ(1U)
8660 #define V_FW_PORT_CMD_PORTID(x)		((x) << S_FW_PORT_CMD_PORTID)
8661 #define G_FW_PORT_CMD_PORTID(x)		\
8662     (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID)
8666 #define V_FW_PORT_CMD_ACTION(x)		((x) << S_FW_PORT_CMD_ACTION)
8667 #define G_FW_PORT_CMD_ACTION(x)		\
8668     (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION)
8672 #define V_FW_PORT_CMD_OVLAN3(x)		((x) << S_FW_PORT_CMD_OVLAN3)
8673 #define G_FW_PORT_CMD_OVLAN3(x)		\
8674     (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3)
8675 #define F_FW_PORT_CMD_OVLAN3		V_FW_PORT_CMD_OVLAN3(1U)
8679 #define V_FW_PORT_CMD_OVLAN2(x)		((x) << S_FW_PORT_CMD_OVLAN2)
8680 #define G_FW_PORT_CMD_OVLAN2(x)		\
8681     (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2)
8682 #define F_FW_PORT_CMD_OVLAN2		V_FW_PORT_CMD_OVLAN2(1U)
8686 #define V_FW_PORT_CMD_OVLAN1(x)		((x) << S_FW_PORT_CMD_OVLAN1)
8687 #define G_FW_PORT_CMD_OVLAN1(x)		\
8688     (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1)
8689 #define F_FW_PORT_CMD_OVLAN1		V_FW_PORT_CMD_OVLAN1(1U)
8693 #define V_FW_PORT_CMD_OVLAN0(x)		((x) << S_FW_PORT_CMD_OVLAN0)
8694 #define G_FW_PORT_CMD_OVLAN0(x)		\
8695     (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0)
8696 #define F_FW_PORT_CMD_OVLAN0		V_FW_PORT_CMD_OVLAN0(1U)
8700 #define V_FW_PORT_CMD_IVLAN0(x)		((x) << S_FW_PORT_CMD_IVLAN0)
8701 #define G_FW_PORT_CMD_IVLAN0(x)		\
8702     (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0)
8703 #define F_FW_PORT_CMD_IVLAN0		V_FW_PORT_CMD_IVLAN0(1U)
8707 #define V_FW_PORT_CMD_OVLAN_FILT(x)	((x) << S_FW_PORT_CMD_OVLAN_FILT)
8708 #define G_FW_PORT_CMD_OVLAN_FILT(x)	\
8709     (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT)
8710 #define F_FW_PORT_CMD_OVLAN_FILT	V_FW_PORT_CMD_OVLAN_FILT(1U)
8714 #define V_FW_PORT_CMD_TXIPG(x)		((x) << S_FW_PORT_CMD_TXIPG)
8715 #define G_FW_PORT_CMD_TXIPG(x)		\
8716     (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG)
8720 #define V_FW_PORT_CMD_FORCE_PINFO(x)	((x) << S_FW_PORT_CMD_FORCE_PINFO)
8721 #define G_FW_PORT_CMD_FORCE_PINFO(x)	\
8722     (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO)
8723 #define F_FW_PORT_CMD_FORCE_PINFO	V_FW_PORT_CMD_FORCE_PINFO(1U)
8727 #define V_FW_PORT_CMD_LSTATUS(x)	((x) << S_FW_PORT_CMD_LSTATUS)
8728 #define G_FW_PORT_CMD_LSTATUS(x)	\
8729     (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS)
8730 #define F_FW_PORT_CMD_LSTATUS		V_FW_PORT_CMD_LSTATUS(1U)
8734 #define V_FW_PORT_CMD_LSPEED(x)		((x) << S_FW_PORT_CMD_LSPEED)
8735 #define G_FW_PORT_CMD_LSPEED(x)		\
8736     (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED)
8740 #define V_FW_PORT_CMD_TXPAUSE(x)	((x) << S_FW_PORT_CMD_TXPAUSE)
8741 #define G_FW_PORT_CMD_TXPAUSE(x)	\
8742     (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE)
8743 #define F_FW_PORT_CMD_TXPAUSE		V_FW_PORT_CMD_TXPAUSE(1U)
8747 #define V_FW_PORT_CMD_RXPAUSE(x)	((x) << S_FW_PORT_CMD_RXPAUSE)
8748 #define G_FW_PORT_CMD_RXPAUSE(x)	\
8749     (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE)
8750 #define F_FW_PORT_CMD_RXPAUSE		V_FW_PORT_CMD_RXPAUSE(1U)
8754 #define V_FW_PORT_CMD_MDIOCAP(x)	((x) << S_FW_PORT_CMD_MDIOCAP)
8755 #define G_FW_PORT_CMD_MDIOCAP(x)	\
8756     (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP)
8757 #define F_FW_PORT_CMD_MDIOCAP		V_FW_PORT_CMD_MDIOCAP(1U)
8761 #define V_FW_PORT_CMD_MDIOADDR(x)	((x) << S_FW_PORT_CMD_MDIOADDR)
8762 #define G_FW_PORT_CMD_MDIOADDR(x)	\
8763     (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR)
8767 #define V_FW_PORT_CMD_LPTXPAUSE(x)	((x) << S_FW_PORT_CMD_LPTXPAUSE)
8768 #define G_FW_PORT_CMD_LPTXPAUSE(x)	\
8769     (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE)
8770 #define F_FW_PORT_CMD_LPTXPAUSE		V_FW_PORT_CMD_LPTXPAUSE(1U)
8774 #define V_FW_PORT_CMD_LPRXPAUSE(x)	((x) << S_FW_PORT_CMD_LPRXPAUSE)
8775 #define G_FW_PORT_CMD_LPRXPAUSE(x)	\
8776     (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE)
8777 #define F_FW_PORT_CMD_LPRXPAUSE		V_FW_PORT_CMD_LPRXPAUSE(1U)
8781 #define V_FW_PORT_CMD_PTYPE(x)		((x) << S_FW_PORT_CMD_PTYPE)
8782 #define G_FW_PORT_CMD_PTYPE(x)		\
8783     (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE)
8787 #define V_FW_PORT_CMD_LINKDNRC(x)	((x) << S_FW_PORT_CMD_LINKDNRC)
8788 #define G_FW_PORT_CMD_LINKDNRC(x)	\
8789     (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC)
8793 #define V_FW_PORT_CMD_MODTYPE(x)	((x) << S_FW_PORT_CMD_MODTYPE)
8794 #define G_FW_PORT_CMD_MODTYPE(x)	\
8795     (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
8799 #define V_FW_PORT_AUXLINFO_KX4(x) \
8800     ((x) << S_FW_PORT_AUXLINFO_KX4)
8801 #define G_FW_PORT_AUXLINFO_KX4(x) \
8802     (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4)
8803 #define F_FW_PORT_AUXLINFO_KX4	V_FW_PORT_AUXLINFO_KX4(1U)
8805 #define S_FW_PORT_AUXLINFO_KR	1
8807 #define V_FW_PORT_AUXLINFO_KR(x) \
8808     ((x) << S_FW_PORT_AUXLINFO_KR)
8809 #define G_FW_PORT_AUXLINFO_KR(x) \
8810     (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR)
8811 #define F_FW_PORT_AUXLINFO_KR	V_FW_PORT_AUXLINFO_KR(1U)
8815 #define V_FW_PORT_CMD_DCBXDIS(x)	((x) << S_FW_PORT_CMD_DCBXDIS)
8816 #define G_FW_PORT_CMD_DCBXDIS(x)	\
8817     (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
8818 #define F_FW_PORT_CMD_DCBXDIS		V_FW_PORT_CMD_DCBXDIS(1U)
8822 #define V_FW_PORT_CMD_APPLY(x)		((x) << S_FW_PORT_CMD_APPLY)
8823 #define G_FW_PORT_CMD_APPLY(x)		\
8824     (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY)
8825 #define F_FW_PORT_CMD_APPLY		V_FW_PORT_CMD_APPLY(1U)
8829 #define V_FW_PORT_CMD_ALL_SYNCD(x)	((x) << S_FW_PORT_CMD_ALL_SYNCD)
8830 #define G_FW_PORT_CMD_ALL_SYNCD(x)	\
8831     (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
8832 #define F_FW_PORT_CMD_ALL_SYNCD		V_FW_PORT_CMD_ALL_SYNCD(1U)
8836 #define V_FW_PORT_CMD_DCB_VERSION(x)	((x) << S_FW_PORT_CMD_DCB_VERSION)
8837 #define G_FW_PORT_CMD_DCB_VERSION(x)	\
8838     (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION)
8842 #define V_FW_PORT_CMD_PFC_STATE(x)	((x) << S_FW_PORT_CMD_PFC_STATE)
8843 #define G_FW_PORT_CMD_PFC_STATE(x)	\
8844     (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
8848 #define V_FW_PORT_CMD_ETS_STATE(x)	((x) << S_FW_PORT_CMD_ETS_STATE)
8849 #define G_FW_PORT_CMD_ETS_STATE(x)	\
8850     (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
8854 #define V_FW_PORT_CMD_APP_STATE(x)	((x) << S_FW_PORT_CMD_APP_STATE)
8855 #define G_FW_PORT_CMD_APP_STATE(x)	\
8856     (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
8860 #define V_FW_PORT_CMD_LSTATUS32(x)	((x) << S_FW_PORT_CMD_LSTATUS32)
8861 #define G_FW_PORT_CMD_LSTATUS32(x)	\
8862     (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32)
8863 #define F_FW_PORT_CMD_LSTATUS32	V_FW_PORT_CMD_LSTATUS32(1U)
8867 #define V_FW_PORT_CMD_LINKDNRC32(x)	((x) << S_FW_PORT_CMD_LINKDNRC32)
8868 #define G_FW_PORT_CMD_LINKDNRC32(x)	\
8869     (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32)
8873 #define V_FW_PORT_CMD_DCBXDIS32(x)	((x) << S_FW_PORT_CMD_DCBXDIS32)
8874 #define G_FW_PORT_CMD_DCBXDIS32(x)	\
8875     (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32)
8876 #define F_FW_PORT_CMD_DCBXDIS32	V_FW_PORT_CMD_DCBXDIS32(1U)
8880 #define V_FW_PORT_CMD_MDIOCAP32(x)	((x) << S_FW_PORT_CMD_MDIOCAP32)
8881 #define G_FW_PORT_CMD_MDIOCAP32(x)	\
8882     (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32)
8883 #define F_FW_PORT_CMD_MDIOCAP32	V_FW_PORT_CMD_MDIOCAP32(1U)
8887 #define V_FW_PORT_CMD_MDIOADDR32(x)	((x) << S_FW_PORT_CMD_MDIOADDR32)
8888 #define G_FW_PORT_CMD_MDIOADDR32(x)	\
8889     (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32)
8893 #define V_FW_PORT_CMD_PORTTYPE32(x)	((x) << S_FW_PORT_CMD_PORTTYPE32)
8894 #define G_FW_PORT_CMD_PORTTYPE32(x)	\
8895     (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32)
8899 #define V_FW_PORT_CMD_MODTYPE32(x)	((x) << S_FW_PORT_CMD_MODTYPE32)
8900 #define G_FW_PORT_CMD_MODTYPE32(x)	\
8901     (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32)
8905 #define V_FW_PORT_CMD_CBLLEN32(x)	((x) << S_FW_PORT_CMD_CBLLEN32)
8906 #define G_FW_PORT_CMD_CBLLEN32(x)	\
8907     (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32)
8911 #define V_FW_PORT_CMD_AUXLINFO32(x)	((x) << S_FW_PORT_CMD_AUXLINFO32)
8912 #define G_FW_PORT_CMD_AUXLINFO32(x)	\
8913     (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32)
8917 #define V_FW_PORT_AUXLINFO32_KX4(x) \
8918     ((x) << S_FW_PORT_AUXLINFO32_KX4)
8919 #define G_FW_PORT_AUXLINFO32_KX4(x) \
8920     (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4)
8921 #define F_FW_PORT_AUXLINFO32_KX4	V_FW_PORT_AUXLINFO32_KX4(1U)
8923 #define S_FW_PORT_AUXLINFO32_KR	1
8925 #define V_FW_PORT_AUXLINFO32_KR(x) \
8926     ((x) << S_FW_PORT_AUXLINFO32_KR)
8927 #define G_FW_PORT_AUXLINFO32_KR(x) \
8928     (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR)
8929 #define F_FW_PORT_AUXLINFO32_KR	V_FW_PORT_AUXLINFO32_KR(1U)
8933 #define V_FW_PORT_CMD_MTU32(x)	((x) << S_FW_PORT_CMD_MTU32)
8934 #define G_FW_PORT_CMD_MTU32(x)	\
8935     (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32)
8947 	FW_PORT_TYPE_FIBER_XFI	=  0,	/* Y, 1, N, Y, N, N, 10G */
8948 	FW_PORT_TYPE_FIBER_XAUI	=  1,	/* Y, 4, N, Y, N, N, 10G */
8949 	FW_PORT_TYPE_BT_SGMII	=  2,	/* Y, 1, No, No, No, No, 1G/100M */
8950 	FW_PORT_TYPE_BT_XFI	=  3,	/* Y, 1, No, No, No, No, 10G/1G/100M */
8951 	FW_PORT_TYPE_BT_XAUI	=  4,	/* Y, 4, No, No, No, No, 10G/1G/100M */
8954 	FW_PORT_TYPE_KX		=  7,	/* No, 1, No, No, Yes, No, 1G */
8955 	FW_PORT_TYPE_KR		=  8,	/* No, 1, No, No, Yes, Yes, 10G */
8956 	FW_PORT_TYPE_SFP	=  9,	/* No, 1, Yes, No, No, No, 10G */
8957 	FW_PORT_TYPE_BP_AP	= 10,	/* No, 1, No, No, Yes, Yes, 10G, BP ANGE */
8959 	FW_PORT_TYPE_QSFP_10G	= 12,	/* No, 1, Yes, No, No, No, 10G */
8960 	FW_PORT_TYPE_QSA	= 13,	/* No, 1, Yes, No, No, No, 10G */
8962 	FW_PORT_TYPE_BP40_BA	= 15,	/* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */
8965 	FW_PORT_TYPE_CR_QSFP	= 18,	/* No, 1, 25G Spider cable */
8967 	FW_PORT_TYPE_SFP28	= 20,	/* No, 1, 25G/10G/1G */
8968 	FW_PORT_TYPE_KR_SFP28	= 21,	/* No, 1, 25G/10G/1G using Backplane */
8969 	FW_PORT_TYPE_KR_XLAUI	= 22,	/* No, 4, 40G/10G/1G, No AN*/
8997 	FW_PORT_MOD_TYPE_NOTSUPPORTED	= M_FW_PORT_CMD_MODTYPE - 1,
9173 #define V_FW_PORT_STATS_CMD_NSTATS(x)	((x) << S_FW_PORT_STATS_CMD_NSTATS)
9174 #define G_FW_PORT_STATS_CMD_NSTATS(x)	\
9175     (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS)
9179 #define V_FW_PORT_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_STATS_CMD_BG_BM)
9180 #define G_FW_PORT_STATS_CMD_BG_BM(x)	\
9181     (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM)
9185 #define V_FW_PORT_STATS_CMD_TX(x)	((x) << S_FW_PORT_STATS_CMD_TX)
9186 #define G_FW_PORT_STATS_CMD_TX(x)	\
9187     (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX)
9188 #define F_FW_PORT_STATS_CMD_TX		V_FW_PORT_STATS_CMD_TX(1U)
9192 #define V_FW_PORT_STATS_CMD_IX(x)	((x) << S_FW_PORT_STATS_CMD_IX)
9193 #define G_FW_PORT_STATS_CMD_IX(x)	\
9194     (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX)
9253 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \
9254     ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT)
9255 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \
9256     (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT)
9260 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \
9261     ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS)
9262 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \
9263     (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS)
9267 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x)	((x) << S_FW_PORT_LB_STATS_CMD_BG_BM)
9268 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x)	\
9269     (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM)
9273 #define V_FW_PORT_LB_STATS_CMD_IX(x)	((x) << S_FW_PORT_LB_STATS_CMD_IX)
9274 #define G_FW_PORT_LB_STATS_CMD_IX(x)	\
9275     (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX)
9291 #define V_FW_PORT_TRACE_CMD_PORTID(x)	((x) << S_FW_PORT_TRACE_CMD_PORTID)
9292 #define G_FW_PORT_TRACE_CMD_PORTID(x)	\
9293     (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID)
9297 #define V_FW_PORT_TRACE_CMD_TRACEEN(x)	((x) << S_FW_PORT_TRACE_CMD_TRACEEN)
9298 #define G_FW_PORT_TRACE_CMD_TRACEEN(x)	\
9299     (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN)
9300 #define F_FW_PORT_TRACE_CMD_TRACEEN	V_FW_PORT_TRACE_CMD_TRACEEN(1U)
9304 #define V_FW_PORT_TRACE_CMD_FLTMODE(x)	((x) << S_FW_PORT_TRACE_CMD_FLTMODE)
9305 #define G_FW_PORT_TRACE_CMD_FLTMODE(x)	\
9306     (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE)
9307 #define F_FW_PORT_TRACE_CMD_FLTMODE	V_FW_PORT_TRACE_CMD_FLTMODE(1U)
9311 #define V_FW_PORT_TRACE_CMD_DUPLEN(x)	((x) << S_FW_PORT_TRACE_CMD_DUPLEN)
9312 #define G_FW_PORT_TRACE_CMD_DUPLEN(x)	\
9313     (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN)
9314 #define F_FW_PORT_TRACE_CMD_DUPLEN	V_FW_PORT_TRACE_CMD_DUPLEN(1U)
9318 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
9319     ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE)
9320 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \
9321     (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \
9326 #define V_FW_PORT_TRACE_CMD_PCIECH(x)	((x) << S_FW_PORT_TRACE_CMD_PCIECH)
9327 #define G_FW_PORT_TRACE_CMD_PCIECH(x)	\
9328     (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH)
9340 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
9341     ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID)
9342 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \
9343     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \
9348 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x)	((x) << S_FW_PORT_TRACE_MMAP_CMD_FID)
9349 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x)	\
9350     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID)
9354 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
9355     ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN)
9356 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \
9357     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \
9359 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN	V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U)
9363 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
9364     ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN)
9365 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \
9366     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \
9368 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U)
9372 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
9373     ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH)
9374 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \
9375     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \
9380 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
9381     ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET)
9382 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \
9383     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \
9388 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
9389     ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE)
9390 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \
9391     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \
9396 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
9397     ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX)
9398 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \
9399     (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \
9449 #define V_FW_PTP_CMD_PORTID(x)		((x) << S_FW_PTP_CMD_PORTID)
9450 #define G_FW_PTP_CMD_PORTID(x)		\
9451     (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID)
9455 #define V_FW_PTP_CMD_PTP_RX_CTRL(x)	((x) << S_FW_PTP_CMD_PTP_RX_CTRL)
9456 #define G_FW_PTP_CMD_PTP_RX_CTRL(x)	\
9457     (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL)
9458 #define F_FW_PTP_CMD_PTP_RX_CTRL	V_FW_PTP_CMD_PTP_RX_CTRL(1U)
9483 #define V_FW_RSS_IND_TBL_CMD_VIID(x)	((x) << S_FW_RSS_IND_TBL_CMD_VIID)
9484 #define G_FW_RSS_IND_TBL_CMD_VIID(x)	\
9485     (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID)
9489 #define V_FW_RSS_IND_TBL_CMD_IQ0(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ0)
9490 #define G_FW_RSS_IND_TBL_CMD_IQ0(x)	\
9491     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0)
9495 #define V_FW_RSS_IND_TBL_CMD_IQ1(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ1)
9496 #define G_FW_RSS_IND_TBL_CMD_IQ1(x)	\
9497     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1)
9501 #define V_FW_RSS_IND_TBL_CMD_IQ2(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ2)
9502 #define G_FW_RSS_IND_TBL_CMD_IQ2(x)	\
9503     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2)
9507 #define V_FW_RSS_IND_TBL_CMD_IQ3(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ3)
9508 #define G_FW_RSS_IND_TBL_CMD_IQ3(x)	\
9509     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3)
9513 #define V_FW_RSS_IND_TBL_CMD_IQ4(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ4)
9514 #define G_FW_RSS_IND_TBL_CMD_IQ4(x)	\
9515     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4)
9519 #define V_FW_RSS_IND_TBL_CMD_IQ5(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ5)
9520 #define G_FW_RSS_IND_TBL_CMD_IQ5(x)	\
9521     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5)
9525 #define V_FW_RSS_IND_TBL_CMD_IQ6(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ6)
9526 #define G_FW_RSS_IND_TBL_CMD_IQ6(x)	\
9527     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6)
9531 #define V_FW_RSS_IND_TBL_CMD_IQ7(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ7)
9532 #define G_FW_RSS_IND_TBL_CMD_IQ7(x)	\
9533     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7)
9537 #define V_FW_RSS_IND_TBL_CMD_IQ8(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ8)
9538 #define G_FW_RSS_IND_TBL_CMD_IQ8(x)	\
9539     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8)
9543 #define V_FW_RSS_IND_TBL_CMD_IQ9(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ9)
9544 #define G_FW_RSS_IND_TBL_CMD_IQ9(x)	\
9545     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9)
9549 #define V_FW_RSS_IND_TBL_CMD_IQ10(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ10)
9550 #define G_FW_RSS_IND_TBL_CMD_IQ10(x)	\
9551     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10)
9555 #define V_FW_RSS_IND_TBL_CMD_IQ11(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ11)
9556 #define G_FW_RSS_IND_TBL_CMD_IQ11(x)	\
9557     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11)
9561 #define V_FW_RSS_IND_TBL_CMD_IQ12(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ12)
9562 #define G_FW_RSS_IND_TBL_CMD_IQ12(x)	\
9563     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12)
9567 #define V_FW_RSS_IND_TBL_CMD_IQ13(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ13)
9568 #define G_FW_RSS_IND_TBL_CMD_IQ13(x)	\
9569     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13)
9573 #define V_FW_RSS_IND_TBL_CMD_IQ14(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ14)
9574 #define G_FW_RSS_IND_TBL_CMD_IQ14(x)	\
9575     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14)
9579 #define V_FW_RSS_IND_TBL_CMD_IQ15(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ15)
9580 #define G_FW_RSS_IND_TBL_CMD_IQ15(x)	\
9581     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15)
9585 #define V_FW_RSS_IND_TBL_CMD_IQ16(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ16)
9586 #define G_FW_RSS_IND_TBL_CMD_IQ16(x)	\
9587     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16)
9591 #define V_FW_RSS_IND_TBL_CMD_IQ17(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ17)
9592 #define G_FW_RSS_IND_TBL_CMD_IQ17(x)	\
9593     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17)
9597 #define V_FW_RSS_IND_TBL_CMD_IQ18(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ18)
9598 #define G_FW_RSS_IND_TBL_CMD_IQ18(x)	\
9599     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18)
9603 #define V_FW_RSS_IND_TBL_CMD_IQ19(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ19)
9604 #define G_FW_RSS_IND_TBL_CMD_IQ19(x)	\
9605     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19)
9609 #define V_FW_RSS_IND_TBL_CMD_IQ20(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ20)
9610 #define G_FW_RSS_IND_TBL_CMD_IQ20(x)	\
9611     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20)
9615 #define V_FW_RSS_IND_TBL_CMD_IQ21(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ21)
9616 #define G_FW_RSS_IND_TBL_CMD_IQ21(x)	\
9617     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21)
9621 #define V_FW_RSS_IND_TBL_CMD_IQ22(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ22)
9622 #define G_FW_RSS_IND_TBL_CMD_IQ22(x)	\
9623     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22)
9627 #define V_FW_RSS_IND_TBL_CMD_IQ23(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ23)
9628 #define G_FW_RSS_IND_TBL_CMD_IQ23(x)	\
9629     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23)
9633 #define V_FW_RSS_IND_TBL_CMD_IQ24(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ24)
9634 #define G_FW_RSS_IND_TBL_CMD_IQ24(x)	\
9635     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24)
9639 #define V_FW_RSS_IND_TBL_CMD_IQ25(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ25)
9640 #define G_FW_RSS_IND_TBL_CMD_IQ25(x)	\
9641     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25)
9645 #define V_FW_RSS_IND_TBL_CMD_IQ26(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ26)
9646 #define G_FW_RSS_IND_TBL_CMD_IQ26(x)	\
9647     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26)
9651 #define V_FW_RSS_IND_TBL_CMD_IQ27(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ27)
9652 #define G_FW_RSS_IND_TBL_CMD_IQ27(x)	\
9653     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27)
9657 #define V_FW_RSS_IND_TBL_CMD_IQ28(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ28)
9658 #define G_FW_RSS_IND_TBL_CMD_IQ28(x)	\
9659     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28)
9663 #define V_FW_RSS_IND_TBL_CMD_IQ29(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ29)
9664 #define G_FW_RSS_IND_TBL_CMD_IQ29(x)	\
9665     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29)
9669 #define V_FW_RSS_IND_TBL_CMD_IQ30(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ30)
9670 #define G_FW_RSS_IND_TBL_CMD_IQ30(x)	\
9671     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30)
9675 #define V_FW_RSS_IND_TBL_CMD_IQ31(x)	((x) << S_FW_RSS_IND_TBL_CMD_IQ31)
9676 #define G_FW_RSS_IND_TBL_CMD_IQ31(x)	\
9677     (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31)
9700 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x)	((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE)
9701 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x)	\
9702     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE)
9705 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL	1
9706 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX		1
9710 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
9711     ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE)
9712 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \
9713     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \
9717 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY	1
9723 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
9724     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN)
9725 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \
9726     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \
9728 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U)
9732 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
9733     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6)
9734 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \
9735     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \
9738     V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U)
9742 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
9743     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6)
9744 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \
9745     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \
9748     V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U)
9752 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
9753     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4)
9754 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \
9755     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \
9758     V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U)
9762 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
9763     ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4)
9764 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \
9765     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \
9768     V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U)
9772 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
9773     ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN)
9774 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \
9775     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \
9777 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U)
9781 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
9782     ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN)
9783 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \
9784     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \
9786 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U)
9788 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1
9790 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
9791     ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP)
9792 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \
9793     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \
9796     V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U)
9800 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
9801     ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ)
9802 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \
9803     (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \
9806     V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U)
9829 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_VIID)
9830 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x)	\
9831     (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID)
9835 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
9836     ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ)
9837 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \
9838     (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \
9843 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
9844     ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
9845 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \
9846     (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \
9849     V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U)
9853 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
9854     ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
9855 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \
9856     (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \
9859     V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U)
9863 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
9864     ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
9865 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \
9866     (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \
9869     V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U)
9871 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1
9873 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
9874     ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
9875 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \
9876     (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \
9879     V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U)
9883 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN)
9884 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x)	\
9885     (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN)
9886 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN	V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U)
9890 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
9891     ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX)
9892 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \
9893     (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \
9898 	FW_SCHED_SC_PARAMS		= 1,
9903 	FW_SCHED_TYPE_STREAMSCHED       = 1,
9908 	FW_SCHED_PARAMS_LEVEL_CL_WRR	= 1,
9914 	FW_SCHED_PARAMS_MODE_FLOW	= 1,
9919 	FW_SCHED_PARAMS_UNIT_PKTRATE	= 1,
9924 	FW_SCHED_PARAMS_RATE_ABS	= 1,
10042 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
10043     ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
10044 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \
10045     (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG)
10049 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
10050     ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG)
10051 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \
10052     (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \
10057 	FW_WATCHDOG_ACTION_FLR = 1,
10076 #define V_FW_WATCHDOG_CMD_PFN(x)	((x) << S_FW_WATCHDOG_CMD_PFN)
10077 #define G_FW_WATCHDOG_CMD_PFN(x)	\
10078     (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN)
10082 #define V_FW_WATCHDOG_CMD_VFN(x)	((x) << S_FW_WATCHDOG_CMD_VFN)
10083 #define G_FW_WATCHDOG_CMD_VFN(x)	\
10084     (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN)
10096 #define V_FW_CLIP_CMD_ALLOC(x)		((x) << S_FW_CLIP_CMD_ALLOC)
10097 #define G_FW_CLIP_CMD_ALLOC(x)		\
10098     (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC)
10099 #define F_FW_CLIP_CMD_ALLOC		V_FW_CLIP_CMD_ALLOC(1U)
10103 #define V_FW_CLIP_CMD_FREE(x)		((x) << S_FW_CLIP_CMD_FREE)
10104 #define G_FW_CLIP_CMD_FREE(x)		\
10105     (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE)
10106 #define F_FW_CLIP_CMD_FREE		V_FW_CLIP_CMD_FREE(1U)
10110 #define V_FW_CLIP_CMD_INDEX(x)	((x) << S_FW_CLIP_CMD_INDEX)
10111 #define G_FW_CLIP_CMD_INDEX(x)	\
10112     (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX)
10158 #define V_FW_CHNET_IFACE_CMD_PORTID(x)	((x) << S_FW_CHNET_IFACE_CMD_PORTID)
10159 #define G_FW_CHNET_IFACE_CMD_PORTID(x)	\
10160     (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID)
10164 #define V_FW_CHNET_IFACE_CMD_RSS_IQID(x)	\
10165     ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID)
10166 #define G_FW_CHNET_IFACE_CMD_RSS_IQID(x)	\
10167     (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID)
10171 #define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x)	\
10172     ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F)
10173 #define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x)	\
10174     (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) &	\
10176 #define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U)
10180 #define V_FW_CHNET_IFACE_CMD_IFID(x)	((x) << S_FW_CHNET_IFACE_CMD_IFID)
10181 #define G_FW_CHNET_IFACE_CMD_IFID(x)	\
10182     (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID)
10186 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x)	((x) << S_FW_CHNET_IFACE_CMD_IFSTATE)
10187 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x)	\
10188     (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE)
10226 #define V_FW_FCOE_LINK_CMD_PORTID(x)	((x) << S_FW_FCOE_LINK_CMD_PORTID)
10227 #define G_FW_FCOE_LINK_CMD_PORTID(x)	\
10228     (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID)
10232 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
10233     ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE)
10234 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \
10235     (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE)
10239 #define V_FW_FCOE_LINK_CMD_FCFI(x)	((x) << S_FW_FCOE_LINK_CMD_FCFI)
10240 #define G_FW_FCOE_LINK_CMD_FCFI(x)	\
10241     (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI)
10245 #define V_FW_FCOE_LINK_CMD_VNPI(x)	((x) << S_FW_FCOE_LINK_CMD_VNPI)
10246 #define G_FW_FCOE_LINK_CMD_VNPI(x)	\
10247     (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI)
10264 #define V_FW_FCOE_VNP_CMD_FCFI(x)	((x) << S_FW_FCOE_VNP_CMD_FCFI)
10265 #define G_FW_FCOE_VNP_CMD_FCFI(x)	\
10266     (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI)
10270 #define V_FW_FCOE_VNP_CMD_ALLOC(x)	((x) << S_FW_FCOE_VNP_CMD_ALLOC)
10271 #define G_FW_FCOE_VNP_CMD_ALLOC(x)	\
10272     (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC)
10273 #define F_FW_FCOE_VNP_CMD_ALLOC		V_FW_FCOE_VNP_CMD_ALLOC(1U)
10277 #define V_FW_FCOE_VNP_CMD_FREE(x)	((x) << S_FW_FCOE_VNP_CMD_FREE)
10278 #define G_FW_FCOE_VNP_CMD_FREE(x)	\
10279     (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE)
10280 #define F_FW_FCOE_VNP_CMD_FREE		V_FW_FCOE_VNP_CMD_FREE(1U)
10284 #define V_FW_FCOE_VNP_CMD_MODIFY(x)	((x) << S_FW_FCOE_VNP_CMD_MODIFY)
10285 #define G_FW_FCOE_VNP_CMD_MODIFY(x)	\
10286     (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY)
10287 #define F_FW_FCOE_VNP_CMD_MODIFY	V_FW_FCOE_VNP_CMD_MODIFY(1U)
10291 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x)	((x) << S_FW_FCOE_VNP_CMD_GEN_WWN)
10292 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x)	\
10293     (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN)
10294 #define F_FW_FCOE_VNP_CMD_GEN_WWN	V_FW_FCOE_VNP_CMD_GEN_WWN(1U)
10298 #define V_FW_FCOE_VNP_CMD_PERSIST(x)	((x) << S_FW_FCOE_VNP_CMD_PERSIST)
10299 #define G_FW_FCOE_VNP_CMD_PERSIST(x)	\
10300     (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST)
10301 #define F_FW_FCOE_VNP_CMD_PERSIST	V_FW_FCOE_VNP_CMD_PERSIST(1U)
10305 #define V_FW_FCOE_VNP_CMD_VFID_EN(x)	((x) << S_FW_FCOE_VNP_CMD_VFID_EN)
10306 #define G_FW_FCOE_VNP_CMD_VFID_EN(x)	\
10307     (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN)
10308 #define F_FW_FCOE_VNP_CMD_VFID_EN	V_FW_FCOE_VNP_CMD_VFID_EN(1U)
10312 #define V_FW_FCOE_VNP_CMD_VNPI(x)	((x) << S_FW_FCOE_VNP_CMD_VNPI)
10313 #define G_FW_FCOE_VNP_CMD_VNPI(x)	\
10314     (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI)
10329 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x)	((x) << S_FW_FCOE_SPARAMS_CMD_PORTID)
10330 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x)	\
10331     (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID)
10453 #define V_FW_FCOE_STATS_CMD_FLOWID(x)	((x) << S_FW_FCOE_STATS_CMD_FLOWID)
10454 #define G_FW_FCOE_STATS_CMD_FLOWID(x)	\
10455     (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID)
10459 #define V_FW_FCOE_STATS_CMD_FREE(x)	((x) << S_FW_FCOE_STATS_CMD_FREE)
10460 #define G_FW_FCOE_STATS_CMD_FREE(x)	\
10461     (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE)
10462 #define F_FW_FCOE_STATS_CMD_FREE	V_FW_FCOE_STATS_CMD_FREE(1U)
10466 #define V_FW_FCOE_STATS_CMD_NSTATS(x)	((x) << S_FW_FCOE_STATS_CMD_NSTATS)
10467 #define G_FW_FCOE_STATS_CMD_NSTATS(x)	\
10468     (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS)
10472 #define V_FW_FCOE_STATS_CMD_PORT(x)	((x) << S_FW_FCOE_STATS_CMD_PORT)
10473 #define G_FW_FCOE_STATS_CMD_PORT(x)	\
10474     (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT)
10478 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \
10479     ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID)
10480 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \
10481     (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID)
10482 #define F_FW_FCOE_STATS_CMD_PORT_VALID	V_FW_FCOE_STATS_CMD_PORT_VALID(1U)
10486 #define V_FW_FCOE_STATS_CMD_IX(x)	((x) << S_FW_FCOE_STATS_CMD_IX)
10487 #define G_FW_FCOE_STATS_CMD_IX(x)	\
10488     (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX)
10511 #define V_FW_FCOE_FCF_CMD_FCFI(x)	((x) << S_FW_FCOE_FCF_CMD_FCFI)
10512 #define G_FW_FCOE_FCF_CMD_FCFI(x)	\
10513     (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI)
10517 #define V_FW_FCOE_FCF_CMD_PRIORITY(x)	((x) << S_FW_FCOE_FCF_CMD_PRIORITY)
10518 #define G_FW_FCOE_FCF_CMD_PRIORITY(x)	\
10519     (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY)
10523 #define V_FW_FCOE_FCF_CMD_FPMA(x)	((x) << S_FW_FCOE_FCF_CMD_FPMA)
10524 #define G_FW_FCOE_FCF_CMD_FPMA(x)	\
10525     (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA)
10526 #define F_FW_FCOE_FCF_CMD_FPMA		V_FW_FCOE_FCF_CMD_FPMA(1U)
10530 #define V_FW_FCOE_FCF_CMD_SPMA(x)	((x) << S_FW_FCOE_FCF_CMD_SPMA)
10531 #define G_FW_FCOE_FCF_CMD_SPMA(x)	\
10532     (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA)
10533 #define F_FW_FCOE_FCF_CMD_SPMA		V_FW_FCOE_FCF_CMD_SPMA(1U)
10537 #define V_FW_FCOE_FCF_CMD_LOGIN(x)	((x) << S_FW_FCOE_FCF_CMD_LOGIN)
10538 #define G_FW_FCOE_FCF_CMD_LOGIN(x)	\
10539     (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN)
10540 #define F_FW_FCOE_FCF_CMD_LOGIN		V_FW_FCOE_FCF_CMD_LOGIN(1U)
10544 #define V_FW_FCOE_FCF_CMD_PORTID(x)	((x) << S_FW_FCOE_FCF_CMD_PORTID)
10545 #define G_FW_FCOE_FCF_CMD_PORTID(x)	\
10546     (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID)
10594 #define V_FW_DCB_IEEE_CMD_PORT(x)	((x) << S_FW_DCB_IEEE_CMD_PORT)
10595 #define G_FW_DCB_IEEE_CMD_PORT(x)	\
10596     (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT)
10600 #define V_FW_DCB_IEEE_CMD_FEATURE(x)	((x) << S_FW_DCB_IEEE_CMD_FEATURE)
10601 #define G_FW_DCB_IEEE_CMD_FEATURE(x)	\
10602     (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE)
10606 #define V_FW_DCB_IEEE_CMD_LOCATION(x)	((x) << S_FW_DCB_IEEE_CMD_LOCATION)
10607 #define G_FW_DCB_IEEE_CMD_LOCATION(x)	\
10608     (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION)
10612 #define V_FW_DCB_IEEE_CMD_CHANGED(x)	((x) << S_FW_DCB_IEEE_CMD_CHANGED)
10613 #define G_FW_DCB_IEEE_CMD_CHANGED(x)	\
10614     (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED)
10615 #define F_FW_DCB_IEEE_CMD_CHANGED	V_FW_DCB_IEEE_CMD_CHANGED(1U)
10619 #define V_FW_DCB_IEEE_CMD_RECEIVED(x)	((x) << S_FW_DCB_IEEE_CMD_RECEIVED)
10620 #define G_FW_DCB_IEEE_CMD_RECEIVED(x)	\
10621     (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED)
10622 #define F_FW_DCB_IEEE_CMD_RECEIVED	V_FW_DCB_IEEE_CMD_RECEIVED(1U)
10626 #define V_FW_DCB_IEEE_CMD_APPLY(x)	((x) << S_FW_DCB_IEEE_CMD_APPLY)
10627 #define G_FW_DCB_IEEE_CMD_APPLY(x)	\
10628     (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY)
10629 #define F_FW_DCB_IEEE_CMD_APPLY	V_FW_DCB_IEEE_CMD_APPLY(1U)
10633 #define V_FW_DCB_IEEE_CMD_DISABLED(x)	((x) << S_FW_DCB_IEEE_CMD_DISABLED)
10634 #define G_FW_DCB_IEEE_CMD_DISABLED(x)	\
10635     (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED)
10636 #define F_FW_DCB_IEEE_CMD_DISABLED	V_FW_DCB_IEEE_CMD_DISABLED(1U)
10640 #define V_FW_DCB_IEEE_CMD_MORE(x)	((x) << S_FW_DCB_IEEE_CMD_MORE)
10641 #define G_FW_DCB_IEEE_CMD_MORE(x)	\
10642     (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE)
10643 #define F_FW_DCB_IEEE_CMD_MORE	V_FW_DCB_IEEE_CMD_MORE(1U)
10647 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x)	((x) << S_FW_DCB_IEEE_CMD_PFC_MBC)
10648 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x)	\
10649     (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC)
10650 #define F_FW_DCB_IEEE_CMD_PFC_MBC	V_FW_DCB_IEEE_CMD_PFC_MBC(1U)
10654 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x)	\
10655     ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING)
10656 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x)	\
10657     (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING)
10658 #define F_FW_DCB_IEEE_CMD_PFC_WILLING	V_FW_DCB_IEEE_CMD_PFC_WILLING(1U)
10662 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x)	((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC)
10663 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x)	\
10664     (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC)
10668 #define V_FW_DCB_IEEE_CMD_PFC_EN(x)	((x) << S_FW_DCB_IEEE_CMD_PFC_EN)
10669 #define G_FW_DCB_IEEE_CMD_PFC_EN(x)	\
10670     (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN)
10674 #define V_FW_DCB_IEEE_CMD_CBS(x)	((x) << S_FW_DCB_IEEE_CMD_CBS)
10675 #define G_FW_DCB_IEEE_CMD_CBS(x)	\
10676     (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS)
10677 #define F_FW_DCB_IEEE_CMD_CBS	V_FW_DCB_IEEE_CMD_CBS(1U)
10681 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x)	\
10682     ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING)
10683 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x)	\
10684     (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING)
10685 #define F_FW_DCB_IEEE_CMD_ETS_WILLING	V_FW_DCB_IEEE_CMD_ETS_WILLING(1U)
10689 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x)	((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC)
10690 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x)	\
10691     (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC)
10695 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x)	((x) << S_FW_DCB_IEEE_CMD_NUM_APPS)
10696 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x)	\
10697     (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS)
10701 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x)	((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER)
10702 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x)	\
10703     (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER)
10704 #define F_FW_DCB_IEEE_CMD_MULTI_PEER	V_FW_DCB_IEEE_CMD_MULTI_PEER(1U)
10708 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x)	\
10709     ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED)
10710 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x)	\
10711     (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED)
10712 #define F_FW_DCB_IEEE_CMD_INVALIDATED	V_FW_DCB_IEEE_CMD_INVALIDATED(1U)
10717 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x)	((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL)
10718 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x)	\
10719     (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL)
10723 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x)	((x) << S_FW_DCB_IEEE_CMD_APP_SELECT)
10724 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x)	\
10725     (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT)
10729 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x)	((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY)
10730 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x)	\
10731     (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY)
10764 #define V_FW_ERROR_CMD_FATAL(x)		((x) << S_FW_ERROR_CMD_FATAL)
10765 #define G_FW_ERROR_CMD_FATAL(x)		\
10766     (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL)
10767 #define F_FW_ERROR_CMD_FATAL		V_FW_ERROR_CMD_FATAL(1U)
10771 #define V_FW_ERROR_CMD_TYPE(x)		((x) << S_FW_ERROR_CMD_TYPE)
10772 #define G_FW_ERROR_CMD_TYPE(x)		\
10773     (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE)
10777 #define V_FW_ERROR_CMD_PFN(x)		((x) << S_FW_ERROR_CMD_PFN)
10778 #define G_FW_ERROR_CMD_PFN(x)		\
10779     (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
10783 #define V_FW_ERROR_CMD_VFN(x)		((x) << S_FW_ERROR_CMD_VFN)
10784 #define G_FW_ERROR_CMD_VFN(x)		\
10785     (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
10789 #define V_FW_ERROR_CMD_PFN(x)		((x) << S_FW_ERROR_CMD_PFN)
10790 #define G_FW_ERROR_CMD_PFN(x)		\
10791     (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN)
10795 #define V_FW_ERROR_CMD_VFN(x)		((x) << S_FW_ERROR_CMD_VFN)
10796 #define G_FW_ERROR_CMD_VFN(x)		\
10797     (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN)
10801 #define V_FW_ERROR_CMD_MV(x)		((x) << S_FW_ERROR_CMD_MV)
10802 #define G_FW_ERROR_CMD_MV(x)		\
10803     (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV)
10804 #define F_FW_ERROR_CMD_MV		V_FW_ERROR_CMD_MV(1U)
10813 			__be32 x;
10832 #define V_FW_DEBUG_CMD_TYPE(x)		((x) << S_FW_DEBUG_CMD_TYPE)
10833 #define G_FW_DEBUG_CMD_TYPE(x)		\
10834     (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE)
10856 	FW_DIAG_CMD_MEMDIAG_TEST_START=1,
10892 #define V_FW_DIAG_CMD_OPCODE(x)     ((x) << S_FW_DIAG_CMD_OPCODE)
10893 #define G_FW_DIAG_CMD_OPCODE(x)     \
10894 	    (((x) >> S_FW_DIAG_CMD_OPCODE) & M_FW_DIAG_CMD_OPCODE)
10898 #define V_FW_DIAG_CMD_TYPE(x)       ((x) << S_FW_DIAG_CMD_TYPE)
10899 #define G_FW_DIAG_CMD_TYPE(x)       \
10900 	    (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE)
10904 #define V_FW_DIAG_CMD_LEN16(x)      ((x) << S_FW_DIAG_CMD_LEN16)
10905 #define G_FW_DIAG_CMD_LEN16(x)      \
10906 	    (((x) >> S_FW_DIAG_CMD_LEN16) & M_FW_DIAG_CMD_LEN16)
10920 #define V_FW_HMA_CMD_MODE(x)	((x) << S_FW_HMA_CMD_MODE)
10921 #define G_FW_HMA_CMD_MODE(x)	\
10922     (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE)
10923 #define F_FW_HMA_CMD_MODE	V_FW_HMA_CMD_MODE(1U)
10927 #define V_FW_HMA_CMD_SOC(x)	((x) << S_FW_HMA_CMD_SOC)
10928 #define G_FW_HMA_CMD_SOC(x)	(((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC)
10929 #define F_FW_HMA_CMD_SOC	V_FW_HMA_CMD_SOC(1U)
10933 #define V_FW_HMA_CMD_EOC(x)	((x) << S_FW_HMA_CMD_EOC)
10934 #define G_FW_HMA_CMD_EOC(x)	(((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC)
10935 #define F_FW_HMA_CMD_EOC	V_FW_HMA_CMD_EOC(1U)
10939 #define V_FW_HMA_CMD_PCIE_PARAMS(x)	((x) << S_FW_HMA_CMD_PCIE_PARAMS)
10940 #define G_FW_HMA_CMD_PCIE_PARAMS(x)	\
10941     (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS)
10945 #define V_FW_HMA_CMD_NADDR(x)	((x) << S_FW_HMA_CMD_NADDR)
10946 #define G_FW_HMA_CMD_NADDR(x)	\
10947     (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR)
10951 #define V_FW_HMA_CMD_SIZE(x)	((x) << S_FW_HMA_CMD_SIZE)
10952 #define G_FW_HMA_CMD_SIZE(x)	\
10953     (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE)
10957 #define V_FW_HMA_CMD_ADDR_SIZE(x)	((x) << S_FW_HMA_CMD_ADDR_SIZE)
10958 #define G_FW_HMA_CMD_ADDR_SIZE(x)	\
10959     (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE)
10972 #define V_FW_JBOF_WIN_REG_CMD_ALLOC(x)	((x) << S_FW_JBOF_WIN_REG_CMD_ALLOC)
10973 #define G_FW_JBOF_WIN_REG_CMD_ALLOC(x)	\
10974     (((x) >> S_FW_JBOF_WIN_REG_CMD_ALLOC) & M_FW_JBOF_WIN_REG_CMD_ALLOC)
10975 #define F_FW_JBOF_WIN_REG_CMD_ALLOC	V_FW_JBOF_WIN_REG_CMD_ALLOC(1U)
10979 #define V_FW_JBOF_WIN_REG_CMD_FREE(x)	((x) << S_FW_JBOF_WIN_REG_CMD_FREE)
10980 #define G_FW_JBOF_WIN_REG_CMD_FREE(x)	\
10981     (((x) >> S_FW_JBOF_WIN_REG_CMD_FREE) & M_FW_JBOF_WIN_REG_CMD_FREE)
10982 #define F_FW_JBOF_WIN_REG_CMD_FREE	V_FW_JBOF_WIN_REG_CMD_FREE(1U)
10986 #define V_FW_JBOF_WIN_REG_CMD_WINDOW_NUM(x)	\
10987     ((x) << S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM)
10988 #define G_FW_JBOF_WIN_REG_CMD_WINDOW_NUM(x)	\
10989     (((x) >> S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM) & \
10994 #define V_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS(x)	\
10995     ((x) << S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS)
10996 #define G_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS(x)	\
10997     (((x) >> S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS) & \
11006 	PCIE_FW_EVAL_PREP		= 1,
11022 #define V_PCIE_FW_ERR(x)	((x) << S_PCIE_FW_ERR)
11023 #define G_PCIE_FW_ERR(x)	(((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR)
11024 #define F_PCIE_FW_ERR		V_PCIE_FW_ERR(1U)
11028 #define V_PCIE_FW_INIT(x)	((x) << S_PCIE_FW_INIT)
11029 #define G_PCIE_FW_INIT(x)	(((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT)
11030 #define F_PCIE_FW_INIT		V_PCIE_FW_INIT(1U)
11034 #define V_PCIE_FW_HALT(x)       ((x) << S_PCIE_FW_HALT)
11035 #define G_PCIE_FW_HALT(x)       (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT)
11036 #define F_PCIE_FW_HALT          V_PCIE_FW_HALT(1U)
11040 #define V_PCIE_FW_EVAL(x)	((x) << S_PCIE_FW_EVAL)
11041 #define G_PCIE_FW_EVAL(x)	(((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL)
11045 #define V_PCIE_FW_STAGE(x)	((x) << S_PCIE_FW_STAGE)
11046 #define G_PCIE_FW_STAGE(x)	(((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE)
11050 #define V_PCIE_FW_ASYNCNOT_VLD(x) \
11051     ((x) << S_PCIE_FW_ASYNCNOT_VLD)
11052 #define G_PCIE_FW_ASYNCNOT_VLD(x) \
11053     (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD)
11054 #define F_PCIE_FW_ASYNCNOT_VLD	V_PCIE_FW_ASYNCNOT_VLD(1U)
11058 #define V_PCIE_FW_ASYNCNOTINT(x) \
11059     ((x) << S_PCIE_FW_ASYNCNOTINT)
11060 #define G_PCIE_FW_ASYNCNOTINT(x) \
11061     (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT)
11062 #define F_PCIE_FW_ASYNCNOTINT	V_PCIE_FW_ASYNCNOTINT(1U)
11066 #define V_PCIE_FW_ASYNCNOT(x)	((x) << S_PCIE_FW_ASYNCNOT)
11067 #define G_PCIE_FW_ASYNCNOT(x)	\
11068     (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT)
11072 #define V_PCIE_FW_MASTER_VLD(x)	((x) << S_PCIE_FW_MASTER_VLD)
11073 #define G_PCIE_FW_MASTER_VLD(x)	\
11074     (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD)
11075 #define F_PCIE_FW_MASTER_VLD	V_PCIE_FW_MASTER_VLD(1U)
11079 #define V_PCIE_FW_MASTER(x)	((x) << S_PCIE_FW_MASTER)
11080 #define G_PCIE_FW_MASTER(x)	(((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER)
11084 #define V_PCIE_FW_RESET_VLD(x)	((x) << S_PCIE_FW_RESET_VLD)
11085 #define G_PCIE_FW_RESET_VLD(x)	\
11086     (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD)
11087 #define F_PCIE_FW_RESET_VLD	V_PCIE_FW_RESET_VLD(1U)
11091 #define V_PCIE_FW_RESET(x)	((x) << S_PCIE_FW_RESET)
11092 #define G_PCIE_FW_RESET(x)	\
11093     (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET)
11097 #define V_PCIE_FW_REGISTERED(x)	((x) << S_PCIE_FW_REGISTERED)
11098 #define G_PCIE_FW_REGISTERED(x)	\
11099     (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
11121  * which is encoded as the number of entries in multiples-1 of 128 here rather
11130 #define V_PCIE_FW_PF_DEVLOG_COUNT_MSB(x) \
11131 	((x) << S_PCIE_FW_PF_DEVLOG_COUNT_MSB)
11132 #define G_PCIE_FW_PF_DEVLOG_COUNT_MSB(x) \
11133 	(((x) >> S_PCIE_FW_PF_DEVLOG_COUNT_MSB) & M_PCIE_FW_PF_DEVLOG_COUNT_MSB)
11137 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
11138 	((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128)
11139 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \
11140 	(((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \
11145 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x)	((x) << S_PCIE_FW_PF_DEVLOG_ADDR16)
11146 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \
11147 	(((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16)
11151 #define V_PCIE_FW_PF_DEVLOG_COUNT_LSB(x) \
11152 	((x) << S_PCIE_FW_PF_DEVLOG_COUNT_LSB)
11153 #define G_PCIE_FW_PF_DEVLOG_COUNT_LSB(x) \
11154 	(((x) >> S_PCIE_FW_PF_DEVLOG_COUNT_LSB) & M_PCIE_FW_PF_DEVLOG_COUNT_LSB)
11158 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x)	((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE)
11159 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \
11160 	(((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE)
11203 #define V_FW_HDR_FW_VER_MAJOR(x) \
11204     ((x) << S_FW_HDR_FW_VER_MAJOR)
11205 #define G_FW_HDR_FW_VER_MAJOR(x) \
11206     (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR)
11210 #define V_FW_HDR_FW_VER_MINOR(x) \
11211     ((x) << S_FW_HDR_FW_VER_MINOR)
11212 #define G_FW_HDR_FW_VER_MINOR(x) \
11213     (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR)
11217 #define V_FW_HDR_FW_VER_MICRO(x) \
11218     ((x) << S_FW_HDR_FW_VER_MICRO)
11219 #define G_FW_HDR_FW_VER_MICRO(x) \
11220     (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO)
11224 #define V_FW_HDR_FW_VER_BUILD(x) \
11225     ((x) << S_FW_HDR_FW_VER_BUILD)
11226 #define G_FW_HDR_FW_VER_BUILD(x) \
11227     (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD)
11230 	T4FW_VERSION_MAJOR	= 1,
11235 	T5FW_VERSION_MAJOR	= 1,
11240 	T6FW_VERSION_MAJOR	= 1,