Lines Matching +full:otp +full:- +full:2
1 /*-
2 * SPDX-License-Identifier: ISC
4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5 * Copyright (c) 1999-2015, Broadcom Corporation
9 * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's
30 * JEDEC JEP-106 Core Vendor IDs
32 * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's
33 * non-standard 4-bit continutation code), as used in ARM's PrimeCell
38 * will need to convert bus-specific vendor IDs to their BHND_MFGID
39 * JEP-106 equivalents.
41 * @par ARM 4-bit Continuation Code
43 * BHND MFGIDs are encoded using ARM's non-standard 4-bit continuation code
51 * The 4-bit continuation code field specifies the number of JEP-106
53 * ARM's JEP-106 ID of `0x7F 0x7F 0x7F 0x7F 0x3B`, the four 0x7F continuations
54 * are encoded as '4' in the 4-bit continuation code field (i.e. 0x43B).
56 #define BHND_MFGID_ARM 0x043b /**< arm JEP-106 vendor id */
57 #define BHND_MFGID_BCM 0x04bf /**< broadcom JEP-106 vendor id */
58 #define BHND_MFGID_MIPS 0x04a7 /**< mips JEP-106 vendor id */
59 #define BHND_MFGID_INVALID 0x0000 /**< invalid JEP-106 vendor id */
64 * OCP-IP assigned vendor codes are used by siba(4)
292 #define BHND_CHIPID_BCM43111 43111 /* 43111 chipcommon chipid (OTP chipid) */
293 #define BHND_CHIPID_BCM43112 43112 /* 43112 chipcommon chipid (OTP chipid) */
296 #define BHND_CHIPID_BCM43131 43131 /* 43131 chip id (OTP chipid) */
302 #define BHND_CHIPID_BCM43217 43217 /* 43217 chip id (OTP chipid) */
304 #define BHND_CHIPID_BCM43221 43221 /* 43221 chipcommon chipid (OTP chipid) */
311 #define BHND_CHIPID_BCM43231 43231 /* 43231 chipcommon chipid (OTP chipid) */
318 #define BHND_CHIPID_BCM43420 43420 /* 43222 chipcommon chipid (OTP, RBBU) */
319 #define BHND_CHIPID_BCM43421 43421 /* 43224 chipcommon chipid (OTP, RBBU) */
320 #define BHND_CHIPID_BCM43428 43428 /* 43228 chipcommon chipid (OTP, RBBU) */
321 #define BHND_CHIPID_BCM43431 43431 /* 4331 chipcommon chipid (OTP, RBBU) */
322 #define BHND_CHIPID_BCM43460 43460 /* 4360 chipcommon chipid (OTP, RBBU) */
349 #define BHND_CHIPID_BCM4342 4342 /* 4342 chipcommon chipid (OTP, RBBU) */
362 #define BHND_CHIPID_BCM4748 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
363 #define BHND_CHIPID_BCM4749 0x4749 /* 5357 chipcommon chipid (OTP, RBBU) */
374 #define BHND_PKGID_BCM4303 2 /* 4303 package id */
378 #define BHND_PKGID_BCM4712MID 2 /* 225pin 4712 package id */
379 #define BHND_PKGID_BCM4328USBD11G 2 /* 4328 802.11g USB package id */
383 #define BHND_PKGID_BCM4329_289PIN 0 /* 4329 289-pin package id */
384 #define BHND_PKGID_BCM4329_182PIN 1 /* 4329N 182-pin package id */
414 #define BHND_PKGID_BCM4314PCIE (8 | 2) /* 4314 QFN PCI (ARM-less) package id */
415 #define BHND_PKGID_BCM4314SDIO_ARM (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */
420 #define BHND_PKGID_BCM4708 2 /* 4708 package id */
464 #define BHND_COREID_NPHY 0x821 /* 802.11n 2x2 phy core */
468 #define BHND_COREID_ARM7S 0x825 /* ARM7tdmi-s core */
471 #define BHND_COREID_SSNPHY 0x828 /* 802.11n single-stream phy core */
477 #define BHND_COREID_DMEMC 0x82e /* DDR1/2 memory controller core */
488 #define BHND_COREID_APB_BRIDGE 0x135 /* BP135 AMBA AXI-APB bridge */
511 #define BHND_COREID_AMEMC 0x52e /* DDR1/2 cadence/denali memory controller core */
514 * PrimeCell-compatible BCM4331 cores, but due to lack of documentation, the
526 #define BHND_CHIPTYPE_UBUS 2 /**< ubus interconnect found in bcm63xx devices */
529 /** Evaluates to true if @p _type is a BCMA or BCMA-compatible interconenct */
540 #define BHND_BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */
548 #define BHND_BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
557 /* Board's BTC 2wire is in the alternate gpios OBSLETE */
574 #define BHND_BFL_TRSW_1BY2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */
584 #define BHND_BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
586 #define BHND_BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
595 #define BHND_BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
596 #define BHND_BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
597 #define BHND_BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */
599 #define BHND_BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
602 #define BHND_BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
609 #define BHND_BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */
611 #define BHND_BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */
627 #define BHND_BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */
630 /* SROM 11 - 11ac boardflag definitions */
636 #define BHND_BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */
637 #define BHND_BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines …
638 #define BHND_BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines …
649 #define BHND_BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */
654 #define BHND_BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */
655 #define BHND_BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */
656 #define BHND_BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */
663 #define BHND_BFL3_EN_NONBRCM_TXBF 0x10000000 /* acphy, enable non-brcm TXBF */
666 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
742 /* 11a-only minipci */
975 #define BHND_BOARD_BCM94331X12_2G 0x00EC /* X12 2G */