Lines Matching +full:0 +full:x1740

30 		#size-cells = <0>;
32 		PowerPC,5125@0 {
34 			reg = <0>;
35 			d-cache-line-size = <0x20>;	// 32 bytes
36 			i-cache-line-size = <0x20>;	// 32 bytes
37 			d-cache-size = <0x8000>;	// L1, 32K
38 			i-cache-size = <0x8000>;	// L1, 32K
47 		reg = <0x00000000 0x10000000>;	// 256MB at 0
52 		reg = <0x30000000 0x08000>;		// 32K at 0x30000000
57 		#size-cells = <0>;
61 			#clock-cells = <0>;
70 		ranges = <0x0 0x80000000 0x400000>;
71 		reg = <0x80000000 0x400000>;
83 			#address-cells = <0>;
85 			reg = <0xc00 0x100>;
90 			reg = <0xa00 0x100>;
91 			interrupts = <79 0x8 80 0x8>;
96 			reg = <0xe00 0x100>;
101 			reg = <0xf00 0x100>;
109 			reg = <0x1000 0x100>;
110 			interrupts = <83 0x2>;
115 			reg = <0x1100 0x080>;
116 			interrupts = <78 0x8>;
121 			reg = <0x1180 0x080>;
122 			interrupts = <86 0x8>;
127 			interrupts = <12 0x8>;
128 			reg = <0x1300 0x80>;
139 			interrupts = <13 0x8>;
140 			reg = <0x1380 0x80>;
151 			interrupts = <8 0x8>;
152 			reg = <0x1500 0x100>;
160 			#size-cells = <0>;
162 			reg = <0x1700 0x20>;
163 			interrupts = <0x9 0x8>;
170 			#size-cells = <0>;
172 			reg = <0x1720 0x20>;
173 			interrupts = <0xa 0x8>;
180 			#size-cells = <0>;
182 			reg = <0x1740 0x20>;
183 			interrupts = <0xb 0x8>;
190 			reg = <0x1760 0x8>;
195 			reg = <0x2100 0x100>;
196 			interrupts = <64 0x8>;
203 			reg = <0x2800 0x800>;
205 			#size-cells = <0>;
206 			phy0: ethernet-phy@0 {
213 			reg = <0x2800 0x800>;
215 			interrupts = <4 0x8>;
225 			reg = <0xA000 0x1000>;
234 			reg = <0x3000 0x400>;
236 			#size-cells = <0>;
237 			interrupts = <43 0x8>;
247 			reg = <0x10100 0x50>;
248 			interrupts = <7 0x8>;
257 			reg = <0x11100 0x100>;
258 			interrupts = <40 0x8>;
269 			reg = <0x11900 0x100>;
270 			interrupts = <40 0x8>;
280 			reg = <0x11f00 0x100>;
281 			interrupts = <40 0x8>;
288 			reg = <0x14000 0x1800>;
289 			interrupts = <65 0x8>;