Lines Matching +full:tshsl +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include "k3-j784s4.dtsi"
15 compatible = "ti,j784s4-evm", "ti,j784s4";
19 stdout-path = "serial2:115200n8";
39 reserved_memory: reserved-memory {
40 #address-cells = <2>;
41 #size-cells = <2>;
46 no-map;
49 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 {
50 compatible = "shared-dma-pool";
52 no-map;
55 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 {
56 compatible = "shared-dma-pool";
58 no-map;
61 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 {
62 compatible = "shared-dma-pool";
64 no-map;
67 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 {
68 compatible = "shared-dma-pool";
70 no-map;
73 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 {
74 compatible = "shared-dma-pool";
76 no-map;
79 main_r5fss0_core0_memory_region: r5f-memory@a2100000 {
80 compatible = "shared-dma-pool";
82 no-map;
85 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 {
86 compatible = "shared-dma-pool";
88 no-map;
91 main_r5fss0_core1_memory_region: r5f-memory@a3100000 {
92 compatible = "shared-dma-pool";
94 no-map;
97 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 {
98 compatible = "shared-dma-pool";
100 no-map;
103 main_r5fss1_core0_memory_region: r5f-memory@a4100000 {
104 compatible = "shared-dma-pool";
106 no-map;
109 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 {
110 compatible = "shared-dma-pool";
112 no-map;
115 main_r5fss1_core1_memory_region: r5f-memory@a5100000 {
116 compatible = "shared-dma-pool";
118 no-map;
121 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 {
122 compatible = "shared-dma-pool";
124 no-map;
127 main_r5fss2_core0_memory_region: r5f-memory@a6100000 {
128 compatible = "shared-dma-pool";
130 no-map;
133 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 {
134 compatible = "shared-dma-pool";
136 no-map;
139 main_r5fss2_core1_memory_region: r5f-memory@a7100000 {
140 compatible = "shared-dma-pool";
142 no-map;
145 c71_0_dma_memory_region: c71-dma-memory@a8000000 {
146 compatible = "shared-dma-pool";
148 no-map;
151 c71_0_memory_region: c71-memory@a8100000 {
152 compatible = "shared-dma-pool";
154 no-map;
157 c71_1_dma_memory_region: c71-dma-memory@a9000000 {
158 compatible = "shared-dma-pool";
160 no-map;
163 c71_1_memory_region: c71-memory@a9100000 {
164 compatible = "shared-dma-pool";
166 no-map;
169 c71_2_dma_memory_region: c71-dma-memory@aa000000 {
170 compatible = "shared-dma-pool";
172 no-map;
175 c71_2_memory_region: c71-memory@aa100000 {
176 compatible = "shared-dma-pool";
178 no-map;
181 c71_3_dma_memory_region: c71-dma-memory@ab000000 {
182 compatible = "shared-dma-pool";
184 no-map;
187 c71_3_memory_region: c71-memory@ab100000 {
188 compatible = "shared-dma-pool";
190 no-map;
194 evm_12v0: regulator-evm12v0 {
196 compatible = "regulator-fixed";
197 regulator-name = "evm_12v0";
198 regulator-min-microvolt = <12000000>;
199 regulator-max-microvolt = <12000000>;
200 regulator-always-on;
201 regulator-boot-on;
204 vsys_3v3: regulator-vsys3v3 {
206 compatible = "regulator-fixed";
207 regulator-name = "vsys_3v3";
208 regulator-min-microvolt = <3300000>;
209 regulator-max-microvolt = <3300000>;
210 vin-supply = <&evm_12v0>;
211 regulator-always-on;
212 regulator-boot-on;
215 vsys_5v0: regulator-vsys5v0 {
217 compatible = "regulator-fixed";
218 regulator-name = "vsys_5v0";
219 regulator-min-microvolt = <5000000>;
220 regulator-max-microvolt = <5000000>;
221 vin-supply = <&evm_12v0>;
222 regulator-always-on;
223 regulator-boot-on;
226 vdd_mmc1: regulator-sd {
228 compatible = "regulator-fixed";
229 regulator-name = "vdd_mmc1";
230 regulator-min-microvolt = <3300000>;
231 regulator-max-microvolt = <3300000>;
232 regulator-boot-on;
233 enable-active-high;
234 vin-supply = <&vsys_3v3>;
238 vdd_sd_dv: regulator-TLV71033 {
240 compatible = "regulator-gpio";
241 regulator-name = "tlv71033";
242 pinctrl-names = "default";
243 pinctrl-0 = <&vdd_sd_dv_pins_default>;
244 regulator-min-microvolt = <1800000>;
245 regulator-max-microvolt = <3300000>;
246 regulator-boot-on;
247 vin-supply = <&vsys_5v0>;
253 dp0_pwr_3v3: regulator-dp0-prw {
254 compatible = "regulator-fixed";
255 regulator-name = "dp0-pwr";
256 regulator-min-microvolt = <3300000>;
257 regulator-max-microvolt = <3300000>;
259 enable-active-high;
262 dp0: connector-dp0 {
263 compatible = "dp-connector";
265 type = "full-size";
266 dp-pwr-supply = <&dp0_pwr_3v3>;
270 remote-endpoint = <&dp0_out>;
281 bootph-all;
282 main_uart8_pins_default: main-uart8-default-pins {
283 bootph-all;
284 pinctrl-single,pins = <
292 main_i2c0_pins_default: main-i2c0-default-pins {
293 pinctrl-single,pins = <
299 main_mmc1_pins_default: main-mmc1-default-pins {
300 bootph-all;
301 pinctrl-single,pins = <
313 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
314 pinctrl-single,pins = <
319 dp0_pins_default: dp0-default-pins {
320 pinctrl-single,pins = <
325 main_i2c4_pins_default: main-i2c4-default-pins {
326 pinctrl-single,pins = <
334 bootph-all;
335 wkup_uart0_pins_default: wkup-uart0-default-pins {
336 bootph-all;
337 pinctrl-single,pins = <
345 wkup_i2c0_pins_default: wkup-i2c0-default-pins {
346 bootph-all;
347 pinctrl-single,pins = <
353 mcu_uart0_pins_default: mcu-uart0-default-pins {
354 bootph-all;
355 pinctrl-single,pins = <
363 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
364 pinctrl-single,pins = <
380 mcu_mdio_pins_default: mcu-mdio-default-pins {
381 pinctrl-single,pins = <
387 mcu_adc0_pins_default: mcu-adc0-default-pins {
388 pinctrl-single,pins = <
400 mcu_adc1_pins_default: mcu-adc1-default-pins {
401 pinctrl-single,pins = <
417 pmic_irq_pins_default: pmic-irq-default-pins {
418 pinctrl-single,pins = <
426 bootph-all;
427 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins {
428 bootph-all;
429 pinctrl-single,pins = <
446 bootph-all;
447 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins {
448 bootph-all;
449 pinctrl-single,pins = <
455 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
456 bootph-all;
457 pinctrl-single,pins = <
473 pinctrl-names = "default";
474 pinctrl-0 = <&wkup_uart0_pins_default>;
478 bootph-all;
480 pinctrl-names = "default";
481 pinctrl-0 = <&wkup_i2c0_pins_default>;
482 clock-frequency = <400000>;
485 /* CAV24C256WE-GT3 */
491 compatible = "ti,tps6594-q1";
493 system-power-controller;
494 pinctrl-names = "default";
495 pinctrl-0 = <&pmic_irq_pins_default>;
496 interrupt-parent = <&wkup_gpio0>;
498 gpio-controller;
499 #gpio-cells = <2>;
500 ti,primary-pmic;
501 buck12-supply = <&vsys_3v3>;
502 buck3-supply = <&vsys_3v3>;
503 buck4-supply = <&vsys_3v3>;
504 buck5-supply = <&vsys_3v3>;
505 ldo1-supply = <&vsys_3v3>;
506 ldo2-supply = <&vsys_3v3>;
507 ldo3-supply = <&vsys_3v3>;
508 ldo4-supply = <&vsys_3v3>;
512 regulator-name = "vdd_ddr_1v1";
513 regulator-min-microvolt = <1100000>;
514 regulator-max-microvolt = <1100000>;
515 regulator-boot-on;
516 regulator-always-on;
520 regulator-name = "vdd_ram_0v85";
521 regulator-min-microvolt = <850000>;
522 regulator-max-microvolt = <850000>;
523 regulator-boot-on;
524 regulator-always-on;
528 regulator-name = "vdd_io_1v8";
529 regulator-min-microvolt = <1800000>;
530 regulator-max-microvolt = <1800000>;
531 regulator-boot-on;
532 regulator-always-on;
536 regulator-name = "vdd_mcu_0v85";
537 regulator-min-microvolt = <850000>;
538 regulator-max-microvolt = <850000>;
539 regulator-boot-on;
540 regulator-always-on;
544 regulator-name = "vdd_mcuio_1v8";
545 regulator-min-microvolt = <1800000>;
546 regulator-max-microvolt = <1800000>;
547 regulator-boot-on;
548 regulator-always-on;
552 regulator-name = "vdd_mcuio_3v3";
553 regulator-min-microvolt = <3300000>;
554 regulator-max-microvolt = <3300000>;
555 regulator-boot-on;
556 regulator-always-on;
560 regulator-name = "vds_dll_0v8";
561 regulator-min-microvolt = <800000>;
562 regulator-max-microvolt = <800000>;
563 regulator-boot-on;
564 regulator-always-on;
568 regulator-name = "vda_mcu_1v8";
569 regulator-min-microvolt = <1800000>;
570 regulator-max-microvolt = <1800000>;
571 regulator-boot-on;
572 regulator-always-on;
579 bootph-all;
581 pinctrl-names = "default";
582 pinctrl-0 = <&mcu_uart0_pins_default>;
586 bootph-all;
588 pinctrl-names = "default";
589 pinctrl-0 = <&main_uart8_pins_default>;
597 bootph-all;
602 bootph-all;
604 pinctrl-names = "default";
605 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>;
608 bootph-all;
609 compatible = "jedec,spi-nor";
611 spi-tx-bus-width = <8>;
612 spi-rx-bus-width = <8>;
613 spi-max-frequency = <25000000>;
614 cdns,tshsl-ns = <60>;
615 cdns,tsd2d-ns = <60>;
616 cdns,tchsh-ns = <60>;
617 cdns,tslch-ns = <60>;
618 cdns,read-delay = <4>;
621 compatible = "fixed-partitions";
622 #address-cells = <1>;
623 #size-cells = <1>;
636 label = "ospi.u-boot";
656 bootph-all;
665 bootph-all;
667 pinctrl-names = "default";
668 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
671 bootph-all;
672 compatible = "jedec,spi-nor";
674 spi-tx-bus-width = <1>;
675 spi-rx-bus-width = <4>;
676 spi-max-frequency = <40000000>;
677 cdns,tshsl-ns = <60>;
678 cdns,tsd2d-ns = <60>;
679 cdns,tchsh-ns = <60>;
680 cdns,tslch-ns = <60>;
681 cdns,read-delay = <2>;
684 compatible = "fixed-partitions";
685 #address-cells = <1>;
686 #size-cells = <1>;
699 label = "qspi.u-boot";
719 bootph-all;
730 pinctrl-names = "default";
731 pinctrl-0 = <&main_i2c0_pins_default>;
733 clock-frequency = <400000>;
738 gpio-controller;
739 #gpio-cells = <2>;
740 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
750 gpio-controller;
751 #gpio-cells = <2>;
752 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
764 bootph-all;
767 non-removable;
768 ti,driver-strength-ohm = <50>;
769 disable-wp;
773 bootph-all;
776 pinctrl-0 = <&main_mmc1_pins_default>;
777 pinctrl-names = "default";
778 disable-wp;
779 vmmc-supply = <&vdd_mmc1>;
780 vqmmc-supply = <&vdd_sd_dv>;
789 pinctrl-names = "default";
790 pinctrl-0 = <&mcu_cpsw_pins_default>;
794 pinctrl-names = "default";
795 pinctrl-0 = <&mcu_mdio_pins_default>;
797 mcu_phy0: ethernet-phy@0 {
799 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
800 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
801 ti,min-output-impedance;
807 phy-mode = "rgmii-rxid";
808 phy-handle = <&mcu_phy0>;
815 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
816 ti,mbox-rx = <0 0 0>;
817 ti,mbox-tx = <1 0 0>;
820 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
821 ti,mbox-rx = <2 0 0>;
822 ti,mbox-tx = <3 0 0>;
830 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
831 ti,mbox-rx = <0 0 0>;
832 ti,mbox-tx = <1 0 0>;
835 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
836 ti,mbox-rx = <2 0 0>;
837 ti,mbox-tx = <3 0 0>;
845 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
846 ti,mbox-rx = <0 0 0>;
847 ti,mbox-tx = <1 0 0>;
850 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
851 ti,mbox-rx = <2 0 0>;
852 ti,mbox-tx = <3 0 0>;
860 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 {
861 ti,mbox-rx = <0 0 0>;
862 ti,mbox-tx = <1 0 0>;
865 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 {
866 ti,mbox-rx = <2 0 0>;
867 ti,mbox-tx = <3 0 0>;
875 mbox_c71_0: mbox-c71-0 {
876 ti,mbox-rx = <0 0 0>;
877 ti,mbox-tx = <1 0 0>;
880 mbox_c71_1: mbox-c71-1 {
881 ti,mbox-rx = <2 0 0>;
882 ti,mbox-tx = <3 0 0>;
890 mbox_c71_2: mbox-c71-2 {
891 ti,mbox-rx = <0 0 0>;
892 ti,mbox-tx = <1 0 0>;
895 mbox_c71_3: mbox-c71-3 {
896 ti,mbox-rx = <2 0 0>;
897 ti,mbox-tx = <3 0 0>;
904 memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
911 memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
918 memory-region = <&main_r5fss0_core0_dma_memory_region>,
925 memory-region = <&main_r5fss0_core1_dma_memory_region>,
932 memory-region = <&main_r5fss1_core0_dma_memory_region>,
939 memory-region = <&main_r5fss1_core1_dma_memory_region>,
946 memory-region = <&main_r5fss2_core0_dma_memory_region>,
953 memory-region = <&main_r5fss2_core1_dma_memory_region>,
960 memory-region = <&c71_0_dma_memory_region>,
967 memory-region = <&c71_1_dma_memory_region>,
974 memory-region = <&c71_2_dma_memory_region>,
981 memory-region = <&c71_3_dma_memory_region>,
986 pinctrl-0 = <&mcu_adc0_pins_default>;
987 pinctrl-names = "default";
990 ti,adc-channels = <0 1 2 3 4 5 6 7>;
995 pinctrl-0 = <&mcu_adc1_pins_default>;
996 pinctrl-names = "default";
999 ti,adc-channels = <0 1 2 3 4 5 6 7>;
1005 clock-frequency = <100000000>;
1010 assigned-clocks = <&k3_clks 218 2>,
1014 assigned-clock-parents = <&k3_clks 218 3>,
1028 cdns,num-lanes = <4>;
1029 #phy-cells = <0>;
1030 cdns,phy-type = <PHY_TYPE_DP>;
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&dp0_pins_default>;
1041 phy-names = "dpphy";
1048 remote-endpoint = <&dp0_in>;
1055 pinctrl-names = "default";
1056 pinctrl-0 = <&main_i2c4_pins_default>;
1057 clock-frequency = <400000>;
1062 gpio-controller;
1063 #gpio-cells = <2>;
1072 remote-endpoint = <&dpi0_out>;
1080 remote-endpoint = <&dp0_connector_in>;