1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "k3-j784s4.dtsi" 13 14/ { 15 compatible = "ti,j784s4-evm", "ti,j784s4"; 16 model = "Texas Instruments J784S4 EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 aliases { 23 serial0 = &wkup_uart0; 24 serial1 = &mcu_uart0; 25 serial2 = &main_uart8; 26 mmc0 = &main_sdhci0; 27 mmc1 = &main_sdhci1; 28 i2c0 = &wkup_i2c0; 29 i2c3 = &main_i2c0; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 /* 32G RAM */ 35 reg = <0x00 0x80000000 0x00 0x80000000>, 36 <0x08 0x80000000 0x07 0x80000000>; 37 }; 38 39 reserved_memory: reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 secure_ddr: optee@9e800000 { 45 reg = <0x00 0x9e800000 0x00 0x01800000>; 46 no-map; 47 }; 48 49 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 50 compatible = "shared-dma-pool"; 51 reg = <0x00 0xa0000000 0x00 0x100000>; 52 no-map; 53 }; 54 55 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 56 compatible = "shared-dma-pool"; 57 reg = <0x00 0xa0100000 0x00 0xf00000>; 58 no-map; 59 }; 60 61 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 62 compatible = "shared-dma-pool"; 63 reg = <0x00 0xa1000000 0x00 0x100000>; 64 no-map; 65 }; 66 67 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0xa1100000 0x00 0xf00000>; 70 no-map; 71 }; 72 73 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x00 0xa2000000 0x00 0x100000>; 76 no-map; 77 }; 78 79 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 80 compatible = "shared-dma-pool"; 81 reg = <0x00 0xa2100000 0x00 0xf00000>; 82 no-map; 83 }; 84 85 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 86 compatible = "shared-dma-pool"; 87 reg = <0x00 0xa3000000 0x00 0x100000>; 88 no-map; 89 }; 90 91 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 92 compatible = "shared-dma-pool"; 93 reg = <0x00 0xa3100000 0x00 0xf00000>; 94 no-map; 95 }; 96 97 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 98 compatible = "shared-dma-pool"; 99 reg = <0x00 0xa4000000 0x00 0x100000>; 100 no-map; 101 }; 102 103 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 104 compatible = "shared-dma-pool"; 105 reg = <0x00 0xa4100000 0x00 0xf00000>; 106 no-map; 107 }; 108 109 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 110 compatible = "shared-dma-pool"; 111 reg = <0x00 0xa5000000 0x00 0x100000>; 112 no-map; 113 }; 114 115 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 116 compatible = "shared-dma-pool"; 117 reg = <0x00 0xa5100000 0x00 0xf00000>; 118 no-map; 119 }; 120 121 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 122 compatible = "shared-dma-pool"; 123 reg = <0x00 0xa6000000 0x00 0x100000>; 124 no-map; 125 }; 126 127 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 128 compatible = "shared-dma-pool"; 129 reg = <0x00 0xa6100000 0x00 0xf00000>; 130 no-map; 131 }; 132 133 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 134 compatible = "shared-dma-pool"; 135 reg = <0x00 0xa7000000 0x00 0x100000>; 136 no-map; 137 }; 138 139 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 140 compatible = "shared-dma-pool"; 141 reg = <0x00 0xa7100000 0x00 0xf00000>; 142 no-map; 143 }; 144 145 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 146 compatible = "shared-dma-pool"; 147 reg = <0x00 0xa8000000 0x00 0x100000>; 148 no-map; 149 }; 150 151 c71_0_memory_region: c71-memory@a8100000 { 152 compatible = "shared-dma-pool"; 153 reg = <0x00 0xa8100000 0x00 0xf00000>; 154 no-map; 155 }; 156 157 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 158 compatible = "shared-dma-pool"; 159 reg = <0x00 0xa9000000 0x00 0x100000>; 160 no-map; 161 }; 162 163 c71_1_memory_region: c71-memory@a9100000 { 164 compatible = "shared-dma-pool"; 165 reg = <0x00 0xa9100000 0x00 0xf00000>; 166 no-map; 167 }; 168 169 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 170 compatible = "shared-dma-pool"; 171 reg = <0x00 0xaa000000 0x00 0x100000>; 172 no-map; 173 }; 174 175 c71_2_memory_region: c71-memory@aa100000 { 176 compatible = "shared-dma-pool"; 177 reg = <0x00 0xaa100000 0x00 0xf00000>; 178 no-map; 179 }; 180 181 c71_3_dma_memory_region: c71-dma-memory@ab000000 { 182 compatible = "shared-dma-pool"; 183 reg = <0x00 0xab000000 0x00 0x100000>; 184 no-map; 185 }; 186 187 c71_3_memory_region: c71-memory@ab100000 { 188 compatible = "shared-dma-pool"; 189 reg = <0x00 0xab100000 0x00 0xf00000>; 190 no-map; 191 }; 192 }; 193 194 evm_12v0: regulator-evm12v0 { 195 /* main supply */ 196 compatible = "regulator-fixed"; 197 regulator-name = "evm_12v0"; 198 regulator-min-microvolt = <12000000>; 199 regulator-max-microvolt = <12000000>; 200 regulator-always-on; 201 regulator-boot-on; 202 }; 203 204 vsys_3v3: regulator-vsys3v3 { 205 /* Output of LM5140 */ 206 compatible = "regulator-fixed"; 207 regulator-name = "vsys_3v3"; 208 regulator-min-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>; 210 vin-supply = <&evm_12v0>; 211 regulator-always-on; 212 regulator-boot-on; 213 }; 214 215 vsys_5v0: regulator-vsys5v0 { 216 /* Output of LM5140 */ 217 compatible = "regulator-fixed"; 218 regulator-name = "vsys_5v0"; 219 regulator-min-microvolt = <5000000>; 220 regulator-max-microvolt = <5000000>; 221 vin-supply = <&evm_12v0>; 222 regulator-always-on; 223 regulator-boot-on; 224 }; 225 226 vdd_mmc1: regulator-sd { 227 /* Output of TPS22918 */ 228 compatible = "regulator-fixed"; 229 regulator-name = "vdd_mmc1"; 230 regulator-min-microvolt = <3300000>; 231 regulator-max-microvolt = <3300000>; 232 regulator-boot-on; 233 enable-active-high; 234 vin-supply = <&vsys_3v3>; 235 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 236 }; 237 238 vdd_sd_dv: regulator-TLV71033 { 239 /* Output of TLV71033 */ 240 compatible = "regulator-gpio"; 241 regulator-name = "tlv71033"; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&vdd_sd_dv_pins_default>; 244 regulator-min-microvolt = <1800000>; 245 regulator-max-microvolt = <3300000>; 246 regulator-boot-on; 247 vin-supply = <&vsys_5v0>; 248 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 249 states = <1800000 0x0>, 250 <3300000 0x1>; 251 }; 252 253 dp0_pwr_3v3: regulator-dp0-prw { 254 compatible = "regulator-fixed"; 255 regulator-name = "dp0-pwr"; 256 regulator-min-microvolt = <3300000>; 257 regulator-max-microvolt = <3300000>; 258 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; 259 enable-active-high; 260 }; 261 262 dp0: connector-dp0 { 263 compatible = "dp-connector"; 264 label = "DP0"; 265 type = "full-size"; 266 dp-pwr-supply = <&dp0_pwr_3v3>; 267 268 port { 269 dp0_connector_in: endpoint { 270 remote-endpoint = <&dp0_out>; 271 }; 272 }; 273 }; 274}; 275 276&wkup_gpio0 { 277 status = "okay"; 278}; 279 280&main_pmx0 { 281 bootph-all; 282 main_uart8_pins_default: main-uart8-default-pins { 283 bootph-all; 284 pinctrl-single,pins = < 285 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 286 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 287 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 288 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 289 >; 290 }; 291 292 main_i2c0_pins_default: main-i2c0-default-pins { 293 pinctrl-single,pins = < 294 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 295 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 296 >; 297 }; 298 299 main_mmc1_pins_default: main-mmc1-default-pins { 300 bootph-all; 301 pinctrl-single,pins = < 302 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 303 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 304 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 305 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 306 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 307 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 308 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 309 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 310 >; 311 }; 312 313 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 314 pinctrl-single,pins = < 315 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 316 >; 317 }; 318 319 dp0_pins_default: dp0-default-pins { 320 pinctrl-single,pins = < 321 J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ 322 >; 323 }; 324 325 main_i2c4_pins_default: main-i2c4-default-pins { 326 pinctrl-single,pins = < 327 J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ 328 J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ 329 >; 330 }; 331}; 332 333&wkup_pmx2 { 334 bootph-all; 335 wkup_uart0_pins_default: wkup-uart0-default-pins { 336 bootph-all; 337 pinctrl-single,pins = < 338 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ 339 J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ 340 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 341 J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ 342 >; 343 }; 344 345 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 346 bootph-all; 347 pinctrl-single,pins = < 348 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 349 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 350 >; 351 }; 352 353 mcu_uart0_pins_default: mcu-uart0-default-pins { 354 bootph-all; 355 pinctrl-single,pins = < 356 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 357 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ 358 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 359 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 360 >; 361 }; 362 363 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 364 pinctrl-single,pins = < 365 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 366 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 367 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 368 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 369 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 370 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 371 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 372 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 373 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 374 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 375 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 376 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 377 >; 378 }; 379 380 mcu_mdio_pins_default: mcu-mdio-default-pins { 381 pinctrl-single,pins = < 382 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 383 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 384 >; 385 }; 386 387 mcu_adc0_pins_default: mcu-adc0-default-pins { 388 pinctrl-single,pins = < 389 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 390 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 391 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 392 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 393 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 394 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 395 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 396 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 397 >; 398 }; 399 400 mcu_adc1_pins_default: mcu-adc1-default-pins { 401 pinctrl-single,pins = < 402 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 403 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 404 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 405 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 406 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 407 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 408 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 409 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 410 >; 411 }; 412}; 413 414&wkup_pmx1 { 415 status = "okay"; 416 417 pmic_irq_pins_default: pmic-irq-default-pins { 418 pinctrl-single,pins = < 419 /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ 420 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) 421 >; 422 }; 423}; 424 425&wkup_pmx0 { 426 bootph-all; 427 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 428 bootph-all; 429 pinctrl-single,pins = < 430 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 431 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 432 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 433 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 434 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 435 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 436 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 437 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 438 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 439 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 440 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 441 >; 442 }; 443}; 444 445&wkup_pmx1 { 446 bootph-all; 447 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 448 bootph-all; 449 pinctrl-single,pins = < 450 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 451 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 452 >; 453 }; 454 455 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 456 bootph-all; 457 pinctrl-single,pins = < 458 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 459 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 460 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 461 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 462 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 463 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 464 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 465 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 466 >; 467 }; 468}; 469 470&wkup_uart0 { 471 /* Firmware usage */ 472 status = "reserved"; 473 pinctrl-names = "default"; 474 pinctrl-0 = <&wkup_uart0_pins_default>; 475}; 476 477&wkup_i2c0 { 478 bootph-all; 479 status = "okay"; 480 pinctrl-names = "default"; 481 pinctrl-0 = <&wkup_i2c0_pins_default>; 482 clock-frequency = <400000>; 483 484 eeprom@50 { 485 /* CAV24C256WE-GT3 */ 486 compatible = "atmel,24c256"; 487 reg = <0x50>; 488 }; 489 490 tps659413: pmic@48 { 491 compatible = "ti,tps6594-q1"; 492 reg = <0x48>; 493 system-power-controller; 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pmic_irq_pins_default>; 496 interrupt-parent = <&wkup_gpio0>; 497 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 498 gpio-controller; 499 #gpio-cells = <2>; 500 ti,primary-pmic; 501 buck12-supply = <&vsys_3v3>; 502 buck3-supply = <&vsys_3v3>; 503 buck4-supply = <&vsys_3v3>; 504 buck5-supply = <&vsys_3v3>; 505 ldo1-supply = <&vsys_3v3>; 506 ldo2-supply = <&vsys_3v3>; 507 ldo3-supply = <&vsys_3v3>; 508 ldo4-supply = <&vsys_3v3>; 509 510 regulators { 511 bucka12: buck12 { 512 regulator-name = "vdd_ddr_1v1"; 513 regulator-min-microvolt = <1100000>; 514 regulator-max-microvolt = <1100000>; 515 regulator-boot-on; 516 regulator-always-on; 517 }; 518 519 bucka3: buck3 { 520 regulator-name = "vdd_ram_0v85"; 521 regulator-min-microvolt = <850000>; 522 regulator-max-microvolt = <850000>; 523 regulator-boot-on; 524 regulator-always-on; 525 }; 526 527 bucka4: buck4 { 528 regulator-name = "vdd_io_1v8"; 529 regulator-min-microvolt = <1800000>; 530 regulator-max-microvolt = <1800000>; 531 regulator-boot-on; 532 regulator-always-on; 533 }; 534 535 bucka5: buck5 { 536 regulator-name = "vdd_mcu_0v85"; 537 regulator-min-microvolt = <850000>; 538 regulator-max-microvolt = <850000>; 539 regulator-boot-on; 540 regulator-always-on; 541 }; 542 543 ldoa1: ldo1 { 544 regulator-name = "vdd_mcuio_1v8"; 545 regulator-min-microvolt = <1800000>; 546 regulator-max-microvolt = <1800000>; 547 regulator-boot-on; 548 regulator-always-on; 549 }; 550 551 ldoa2: ldo2 { 552 regulator-name = "vdd_mcuio_3v3"; 553 regulator-min-microvolt = <3300000>; 554 regulator-max-microvolt = <3300000>; 555 regulator-boot-on; 556 regulator-always-on; 557 }; 558 559 ldoa3: ldo3 { 560 regulator-name = "vds_dll_0v8"; 561 regulator-min-microvolt = <800000>; 562 regulator-max-microvolt = <800000>; 563 regulator-boot-on; 564 regulator-always-on; 565 }; 566 567 ldoa4: ldo4 { 568 regulator-name = "vda_mcu_1v8"; 569 regulator-min-microvolt = <1800000>; 570 regulator-max-microvolt = <1800000>; 571 regulator-boot-on; 572 regulator-always-on; 573 }; 574 }; 575 }; 576}; 577 578&mcu_uart0 { 579 bootph-all; 580 status = "okay"; 581 pinctrl-names = "default"; 582 pinctrl-0 = <&mcu_uart0_pins_default>; 583}; 584 585&main_uart8 { 586 bootph-all; 587 status = "okay"; 588 pinctrl-names = "default"; 589 pinctrl-0 = <&main_uart8_pins_default>; 590}; 591 592&ufs_wrapper { 593 status = "okay"; 594}; 595 596&fss { 597 bootph-all; 598 status = "okay"; 599}; 600 601&ospi0 { 602 bootph-all; 603 status = "okay"; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 606 607 flash@0 { 608 bootph-all; 609 compatible = "jedec,spi-nor"; 610 reg = <0x0>; 611 spi-tx-bus-width = <8>; 612 spi-rx-bus-width = <8>; 613 spi-max-frequency = <25000000>; 614 cdns,tshsl-ns = <60>; 615 cdns,tsd2d-ns = <60>; 616 cdns,tchsh-ns = <60>; 617 cdns,tslch-ns = <60>; 618 cdns,read-delay = <4>; 619 620 partitions { 621 compatible = "fixed-partitions"; 622 #address-cells = <1>; 623 #size-cells = <1>; 624 625 partition@0 { 626 label = "ospi.tiboot3"; 627 reg = <0x0 0x80000>; 628 }; 629 630 partition@80000 { 631 label = "ospi.tispl"; 632 reg = <0x80000 0x200000>; 633 }; 634 635 partition@280000 { 636 label = "ospi.u-boot"; 637 reg = <0x280000 0x400000>; 638 }; 639 640 partition@680000 { 641 label = "ospi.env"; 642 reg = <0x680000 0x40000>; 643 }; 644 645 partition@6c0000 { 646 label = "ospi.env.backup"; 647 reg = <0x6c0000 0x40000>; 648 }; 649 650 partition@800000 { 651 label = "ospi.rootfs"; 652 reg = <0x800000 0x37c0000>; 653 }; 654 655 partition@3fc0000 { 656 bootph-all; 657 label = "ospi.phypattern"; 658 reg = <0x3fc0000 0x40000>; 659 }; 660 }; 661 }; 662}; 663 664&ospi1 { 665 bootph-all; 666 status = "okay"; 667 pinctrl-names = "default"; 668 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 669 670 flash@0 { 671 bootph-all; 672 compatible = "jedec,spi-nor"; 673 reg = <0x0>; 674 spi-tx-bus-width = <1>; 675 spi-rx-bus-width = <4>; 676 spi-max-frequency = <40000000>; 677 cdns,tshsl-ns = <60>; 678 cdns,tsd2d-ns = <60>; 679 cdns,tchsh-ns = <60>; 680 cdns,tslch-ns = <60>; 681 cdns,read-delay = <2>; 682 683 partitions { 684 compatible = "fixed-partitions"; 685 #address-cells = <1>; 686 #size-cells = <1>; 687 688 partition@0 { 689 label = "qspi.tiboot3"; 690 reg = <0x0 0x80000>; 691 }; 692 693 partition@80000 { 694 label = "qspi.tispl"; 695 reg = <0x80000 0x200000>; 696 }; 697 698 partition@280000 { 699 label = "qspi.u-boot"; 700 reg = <0x280000 0x400000>; 701 }; 702 703 partition@680000 { 704 label = "qspi.env"; 705 reg = <0x680000 0x40000>; 706 }; 707 708 partition@6c0000 { 709 label = "qspi.env.backup"; 710 reg = <0x6c0000 0x40000>; 711 }; 712 713 partition@800000 { 714 label = "qspi.rootfs"; 715 reg = <0x800000 0x37c0000>; 716 }; 717 718 partition@3fc0000 { 719 bootph-all; 720 label = "qspi.phypattern"; 721 reg = <0x3fc0000 0x40000>; 722 }; 723 }; 724 725 }; 726}; 727 728&main_i2c0 { 729 status = "okay"; 730 pinctrl-names = "default"; 731 pinctrl-0 = <&main_i2c0_pins_default>; 732 733 clock-frequency = <400000>; 734 735 exp1: gpio@20 { 736 compatible = "ti,tca6416"; 737 reg = <0x20>; 738 gpio-controller; 739 #gpio-cells = <2>; 740 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 741 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 742 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 743 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 744 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 745 }; 746 747 exp2: gpio@22 { 748 compatible = "ti,tca6424"; 749 reg = <0x22>; 750 gpio-controller; 751 #gpio-cells = <2>; 752 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 753 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 754 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 755 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 756 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 757 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 758 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 759 "USER_INPUT1", "USER_LED1", "USER_LED2"; 760 }; 761}; 762 763&main_sdhci0 { 764 bootph-all; 765 /* eMMC */ 766 status = "okay"; 767 non-removable; 768 ti,driver-strength-ohm = <50>; 769 disable-wp; 770}; 771 772&main_sdhci1 { 773 bootph-all; 774 /* SD card */ 775 status = "okay"; 776 pinctrl-0 = <&main_mmc1_pins_default>; 777 pinctrl-names = "default"; 778 disable-wp; 779 vmmc-supply = <&vdd_mmc1>; 780 vqmmc-supply = <&vdd_sd_dv>; 781}; 782 783&main_gpio0 { 784 status = "okay"; 785}; 786 787&mcu_cpsw { 788 status = "okay"; 789 pinctrl-names = "default"; 790 pinctrl-0 = <&mcu_cpsw_pins_default>; 791}; 792 793&davinci_mdio { 794 pinctrl-names = "default"; 795 pinctrl-0 = <&mcu_mdio_pins_default>; 796 797 mcu_phy0: ethernet-phy@0 { 798 reg = <0>; 799 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 800 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 801 ti,min-output-impedance; 802 }; 803}; 804 805&mcu_cpsw_port1 { 806 status = "okay"; 807 phy-mode = "rgmii-rxid"; 808 phy-handle = <&mcu_phy0>; 809}; 810 811&mailbox0_cluster0 { 812 status = "okay"; 813 interrupts = <436>; 814 815 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 816 ti,mbox-rx = <0 0 0>; 817 ti,mbox-tx = <1 0 0>; 818 }; 819 820 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 821 ti,mbox-rx = <2 0 0>; 822 ti,mbox-tx = <3 0 0>; 823 }; 824}; 825 826&mailbox0_cluster1 { 827 status = "okay"; 828 interrupts = <432>; 829 830 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 831 ti,mbox-rx = <0 0 0>; 832 ti,mbox-tx = <1 0 0>; 833 }; 834 835 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 836 ti,mbox-rx = <2 0 0>; 837 ti,mbox-tx = <3 0 0>; 838 }; 839}; 840 841&mailbox0_cluster2 { 842 status = "okay"; 843 interrupts = <428>; 844 845 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 846 ti,mbox-rx = <0 0 0>; 847 ti,mbox-tx = <1 0 0>; 848 }; 849 850 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 851 ti,mbox-rx = <2 0 0>; 852 ti,mbox-tx = <3 0 0>; 853 }; 854}; 855 856&mailbox0_cluster3 { 857 status = "okay"; 858 interrupts = <424>; 859 860 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 861 ti,mbox-rx = <0 0 0>; 862 ti,mbox-tx = <1 0 0>; 863 }; 864 865 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 866 ti,mbox-rx = <2 0 0>; 867 ti,mbox-tx = <3 0 0>; 868 }; 869}; 870 871&mailbox0_cluster4 { 872 status = "okay"; 873 interrupts = <420>; 874 875 mbox_c71_0: mbox-c71-0 { 876 ti,mbox-rx = <0 0 0>; 877 ti,mbox-tx = <1 0 0>; 878 }; 879 880 mbox_c71_1: mbox-c71-1 { 881 ti,mbox-rx = <2 0 0>; 882 ti,mbox-tx = <3 0 0>; 883 }; 884}; 885 886&mailbox0_cluster5 { 887 status = "okay"; 888 interrupts = <416>; 889 890 mbox_c71_2: mbox-c71-2 { 891 ti,mbox-rx = <0 0 0>; 892 ti,mbox-tx = <1 0 0>; 893 }; 894 895 mbox_c71_3: mbox-c71-3 { 896 ti,mbox-rx = <2 0 0>; 897 ti,mbox-tx = <3 0 0>; 898 }; 899}; 900 901&mcu_r5fss0_core0 { 902 status = "okay"; 903 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 904 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 905 <&mcu_r5fss0_core0_memory_region>; 906}; 907 908&mcu_r5fss0_core1 { 909 status = "okay"; 910 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 911 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 912 <&mcu_r5fss0_core1_memory_region>; 913}; 914 915&main_r5fss0_core0 { 916 status = "okay"; 917 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 918 memory-region = <&main_r5fss0_core0_dma_memory_region>, 919 <&main_r5fss0_core0_memory_region>; 920}; 921 922&main_r5fss0_core1 { 923 status = "okay"; 924 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 925 memory-region = <&main_r5fss0_core1_dma_memory_region>, 926 <&main_r5fss0_core1_memory_region>; 927}; 928 929&main_r5fss1_core0 { 930 status = "okay"; 931 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 932 memory-region = <&main_r5fss1_core0_dma_memory_region>, 933 <&main_r5fss1_core0_memory_region>; 934}; 935 936&main_r5fss1_core1 { 937 status = "okay"; 938 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 939 memory-region = <&main_r5fss1_core1_dma_memory_region>, 940 <&main_r5fss1_core1_memory_region>; 941}; 942 943&main_r5fss2_core0 { 944 status = "okay"; 945 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 946 memory-region = <&main_r5fss2_core0_dma_memory_region>, 947 <&main_r5fss2_core0_memory_region>; 948}; 949 950&main_r5fss2_core1 { 951 status = "okay"; 952 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 953 memory-region = <&main_r5fss2_core1_dma_memory_region>, 954 <&main_r5fss2_core1_memory_region>; 955}; 956 957&c71_0 { 958 status = "okay"; 959 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 960 memory-region = <&c71_0_dma_memory_region>, 961 <&c71_0_memory_region>; 962}; 963 964&c71_1 { 965 status = "okay"; 966 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 967 memory-region = <&c71_1_dma_memory_region>, 968 <&c71_1_memory_region>; 969}; 970 971&c71_2 { 972 status = "okay"; 973 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 974 memory-region = <&c71_2_dma_memory_region>, 975 <&c71_2_memory_region>; 976}; 977 978&c71_3 { 979 status = "okay"; 980 mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 981 memory-region = <&c71_3_dma_memory_region>, 982 <&c71_3_memory_region>; 983}; 984 985&tscadc0 { 986 pinctrl-0 = <&mcu_adc0_pins_default>; 987 pinctrl-names = "default"; 988 status = "okay"; 989 adc { 990 ti,adc-channels = <0 1 2 3 4 5 6 7>; 991 }; 992}; 993 994&tscadc1 { 995 pinctrl-0 = <&mcu_adc1_pins_default>; 996 pinctrl-names = "default"; 997 status = "okay"; 998 adc { 999 ti,adc-channels = <0 1 2 3 4 5 6 7>; 1000 }; 1001}; 1002 1003&serdes_refclk { 1004 status = "okay"; 1005 clock-frequency = <100000000>; 1006}; 1007 1008&dss { 1009 status = "okay"; 1010 assigned-clocks = <&k3_clks 218 2>, 1011 <&k3_clks 218 5>, 1012 <&k3_clks 218 14>, 1013 <&k3_clks 218 18>; 1014 assigned-clock-parents = <&k3_clks 218 3>, 1015 <&k3_clks 218 7>, 1016 <&k3_clks 218 16>, 1017 <&k3_clks 218 22>; 1018}; 1019 1020&serdes_wiz4 { 1021 status = "okay"; 1022}; 1023 1024&serdes4 { 1025 status = "okay"; 1026 serdes4_dp_link: phy@0 { 1027 reg = <0>; 1028 cdns,num-lanes = <4>; 1029 #phy-cells = <0>; 1030 cdns,phy-type = <PHY_TYPE_DP>; 1031 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, 1032 <&serdes_wiz4 3>, <&serdes_wiz4 4>; 1033 }; 1034}; 1035 1036&mhdp { 1037 status = "okay"; 1038 pinctrl-names = "default"; 1039 pinctrl-0 = <&dp0_pins_default>; 1040 phys = <&serdes4_dp_link>; 1041 phy-names = "dpphy"; 1042}; 1043 1044&dss_ports { 1045 /* DP */ 1046 port { 1047 dpi0_out: endpoint { 1048 remote-endpoint = <&dp0_in>; 1049 }; 1050 }; 1051}; 1052 1053&main_i2c4 { 1054 status = "okay"; 1055 pinctrl-names = "default"; 1056 pinctrl-0 = <&main_i2c4_pins_default>; 1057 clock-frequency = <400000>; 1058 1059 exp4: gpio@20 { 1060 compatible = "ti,tca6408"; 1061 reg = <0x20>; 1062 gpio-controller; 1063 #gpio-cells = <2>; 1064 }; 1065}; 1066 1067&dp0_ports { 1068 port@0 { 1069 reg = <0>; 1070 1071 dp0_in: endpoint { 1072 remote-endpoint = <&dpi0_out>; 1073 }; 1074 }; 1075 1076 port@4 { 1077 reg = <4>; 1078 1079 dp0_out: endpoint { 1080 remote-endpoint = <&dp0_connector_in>; 1081 }; 1082 }; 1083}; 1084