Lines Matching +full:- +full:1 +full:ul
1 /*-
11 * 1. Redistributions of source code must retain the above copyright
40 /* CNTHCTL_EL2 - Counter-timer Hypervisor Control register */
46 #define CNTHCTL_EL1PCEN_SHIFT 1
50 /* Valid if HCR_EL2.E2H == 1 */
55 #define CNTHCTL_E2H_EL0VCTEN_SHIFT 1
113 /* CNTPOFF_EL2 - Counter-timer Physical Offset Register */
121 /* CPTR_EL2 - Architecture feature trap register */
129 /* Valid if HCR_EL2.E2H == 1 */
137 /* HCR_EL2 - Hypervisor Config Register */
138 #define HCR_VM (UL(0x1) << 0)
139 #define HCR_SWIO (UL(0x1) << 1)
140 #define HCR_PTW (UL(0x1) << 2)
141 #define HCR_FMO (UL(0x1) << 3)
142 #define HCR_IMO (UL(0x1) << 4)
143 #define HCR_AMO (UL(0x1) << 5)
144 #define HCR_VF (UL(0x1) << 6)
145 #define HCR_VI (UL(0x1) << 7)
146 #define HCR_VSE (UL(0x1) << 8)
147 #define HCR_FB (UL(0x1) << 9)
148 #define HCR_BSU_MASK (UL(0x3) << 10)
149 #define HCR_BSU_IS (UL(0x1) << 10)
150 #define HCR_BSU_OS (UL(0x2) << 10)
151 #define HCR_BSU_FS (UL(0x3) << 10)
152 #define HCR_DC (UL(0x1) << 12)
153 #define HCR_TWI (UL(0x1) << 13)
154 #define HCR_TWE (UL(0x1) << 14)
155 #define HCR_TID0 (UL(0x1) << 15)
156 #define HCR_TID1 (UL(0x1) << 16)
157 #define HCR_TID2 (UL(0x1) << 17)
158 #define HCR_TID3 (UL(0x1) << 18)
159 #define HCR_TSC (UL(0x1) << 19)
160 #define HCR_TIDCP (UL(0x1) << 20)
161 #define HCR_TACR (UL(0x1) << 21)
162 #define HCR_TSW (UL(0x1) << 22)
163 #define HCR_TPCP (UL(0x1) << 23)
164 #define HCR_TPU (UL(0x1) << 24)
165 #define HCR_TTLB (UL(0x1) << 25)
166 #define HCR_TVM (UL(0x1) << 26)
167 #define HCR_TGE (UL(0x1) << 27)
168 #define HCR_TDZ (UL(0x1) << 28)
169 #define HCR_HCD (UL(0x1) << 29)
170 #define HCR_TRVM (UL(0x1) << 30)
171 #define HCR_RW (UL(0x1) << 31)
172 #define HCR_CD (UL(0x1) << 32)
173 #define HCR_ID (UL(0x1) << 33)
174 #define HCR_E2H (UL(0x1) << 34)
175 #define HCR_TLOR (UL(0x1) << 35)
176 #define HCR_TERR (UL(0x1) << 36)
177 #define HCR_TEA (UL(0x1) << 37)
178 #define HCR_MIOCNCE (UL(0x1) << 38)
180 #define HCR_APK (UL(0x1) << 40)
181 #define HCR_API (UL(0x1) << 41)
182 #define HCR_NV (UL(0x1) << 42)
183 #define HCR_NV1 (UL(0x1) << 43)
184 #define HCR_AT (UL(0x1) << 44)
185 #define HCR_NV2 (UL(0x1) << 45)
186 #define HCR_FWB (UL(0x1) << 46)
187 #define HCR_FIEN (UL(0x1) << 47)
189 #define HCR_TID4 (UL(0x1) << 49)
190 #define HCR_TICAB (UL(0x1) << 50)
191 #define HCR_AMVOFFEN (UL(0x1) << 51)
192 #define HCR_TOCU (UL(0x1) << 52)
193 #define HCR_EnSCXT (UL(0x1) << 53)
194 #define HCR_TTLBIS (UL(0x1) << 54)
195 #define HCR_TTLBOS (UL(0x1) << 55)
196 #define HCR_ATA (UL(0x1) << 56)
197 #define HCR_DCT (UL(0x1) << 57)
198 #define HCR_TID5 (UL(0x1) << 58)
199 #define HCR_TWEDEn (UL(0x1) << 59)
200 #define HCR_TWEDEL_MASK (UL(0xf) << 60)
202 /* HCRX_EL2 - Extended Hypervisor Configuration Register */
206 #define HCRX_EL2_CRn 1
210 #define HCRX_EnAS0 (UL(0x1) << 0)
211 #define HCRX_EnALS (UL(0x1) << 1)
212 #define HCRX_EnASR (UL(0x1) << 2)
213 #define HCRX_FnXS (UL(0x1) << 3)
214 #define HCRX_FGTnXS (UL(0x1) << 4)
215 #define HCRX_SMPME (UL(0x1) << 5)
216 #define HCRX_TALLINT (UL(0x1) << 6)
217 #define HCRX_VINMI (UL(0x1) << 7)
218 #define HCRX_VFNMI (UL(0x1) << 8)
219 #define HCRX_CMOW (UL(0x1) << 9)
220 #define HCRX_MCE2 (UL(0x1) << 10)
221 #define HCRX_MSCEn (UL(0x1) << 11)
223 #define HCRX_TCR2En (UL(0x1) << 14)
224 #define HCRX_SCTLR2En (UL(0x1) << 15)
225 #define HCRX_PTTWI (UL(0x1) << 16)
226 #define HCRX_D128En (UL(0x1) << 17)
227 #define HCRX_EnSNERR (UL(0x1) << 18)
228 #define HCRX_TMEA (UL(0x1) << 19)
229 #define HCRX_EnSDERR (UL(0x1) << 20)
230 #define HCRX_EnIDCP128 (UL(0x1) << 21)
231 #define HCRX_GCSEn (UL(0x1) << 22)
232 #define HCRX_EnFPM (UL(0x1) << 23)
233 #define HCRX_PACMEn (UL(0x1) << 24)
235 #define HCRX_SRMASKEn (UL(0x1) << 26)
237 /* HPFAR_EL2 - Hypervisor IPA Fault Address Register */
249 #define ICC_SRE_EL2_SRE (1UL << 0)
250 #define ICC_SRE_EL2_EN (1UL << 3)
252 /* MDCR_EL2 - Hyp Debug Control Register */
301 /* SCTLR_EL2 - System Control Register */
305 #define SCTLR_EL2_A_SHIFT 1
322 /* TCR_EL2 - Translation Control Register */
330 #define TCR_EL2_IRGN0_WBWA (1UL << TCR_EL2_IRGN0_SHIFT)
333 #define TCR_EL2_ORGN0_WBWA (1UL << TCR_EL2_ORGN0_SHIFT)
336 #define TCR_EL2_SH0_IS (3UL << TCR_EL2_SH0_SHIFT)
344 #define TCR_EL2_PS_32BITS (0UL << TCR_EL2_PS_SHIFT)
345 #define TCR_EL2_PS_36BITS (1UL << TCR_EL2_PS_SHIFT)
346 #define TCR_EL2_PS_40BITS (2UL << TCR_EL2_PS_SHIFT)
347 #define TCR_EL2_PS_42BITS (3UL << TCR_EL2_PS_SHIFT)
348 #define TCR_EL2_PS_44BITS (4UL << TCR_EL2_PS_SHIFT)
349 #define TCR_EL2_PS_48BITS (5UL << TCR_EL2_PS_SHIFT)
350 #define TCR_EL2_PS_52BITS (6UL << TCR_EL2_PS_SHIFT)
352 #define TCR_EL2_HPD (1UL << TCR_EL2_HPD_SHIFT)
354 #define TCR_EL2_HWU59 (1UL << TCR_EL2_HWU59_SHIFT)
356 #define TCR_EL2_HWU60 (1UL << TCR_EL2_HWU60_SHIFT)
358 #define TCR_EL2_HWU61 (1UL << TCR_EL2_HWU61_SHIFT)
360 #define TCR_EL2_HWU62 (1UL << TCR_EL2_HWU62_SHIFT)
364 /* VMPDIR_EL2 - Virtualization Multiprocessor ID Register */
369 /* VTCR_EL2 - Virtualization Translation Control Register */
404 /* VTTBR_EL2 - Virtualization Translation Table Base Register */