1 /*-
38 #include <dt-bindings/clock/tegra124-car.h>
213 	/* bank L ->  0-31 */
241 	/* bank H -> 32-63 */
270 	/* bank U  -> 64-95 */
299 	/* bank V  -> 96-127 */
325 	/* bank W   -> 128-159*/
334 	/* GATE(CEC, "cec", "clk_m", W(8)), */
354 	/* bank X -> 160-191*/
553 	if (sc->flags & DCF_HAVE_ENA)  in periph_init()
554 		MD4(sc, sc->base_reg, PERLCK_ENA_MASK, PERLCK_ENA_MASK);  in periph_init()
556 	RD4(sc, sc->base_reg, &reg);  in periph_init()
560 	if (sc->flags & DCF_HAVE_MUX)  in periph_init()
561 		sc->mux = (reg >> PERLCK_MUX_SHIFT) & PERLCK_MUX_MASK;  in periph_init()
563 		sc->mux = 0;  in periph_init()
564 	if (sc->flags & DCF_HAVE_DIV)  in periph_init()
565 		sc->divider = (reg & sc->div_mask) + 2;  in periph_init()
567 		sc->divider = 1;  in periph_init()
568 	if ((sc->flags & DCF_IS_MASK) == DCF_IS_UART) {  in periph_init()
570 			sc->divider = 2;  in periph_init()
574 	if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) {  in periph_init()
575 		if (!(reg & PERLCK_AMUX_DIS) && (sc->mux == 7)) {  in periph_init()
576 			sc->mux = 8 +  in periph_init()
580 	clknode_init_parent_idx(clk, sc->mux);  in periph_init()
591 	if (!(sc->flags & DCF_HAVE_MUX))  in periph_set_mux()
594 	sc->mux = idx;  in periph_set_mux()
596 	RD4(sc, sc->base_reg, &reg);  in periph_set_mux()
598 	if ((sc->flags & DCF_IS_MASK) == DCF_IS_AUDIO) {  in periph_set_mux()
606 			reg |= (idx - 8) << PERLCK_AMUX_SHIFT;  in periph_set_mux()
611 	WR4(sc, sc->base_reg, reg);  in periph_set_mux()
625 	if (sc->flags & DCF_HAVE_DIV) {  in periph_recalc()
627 		RD4(sc, sc->base_reg, &reg);  in periph_recalc()
629 		*freq = (*freq << sc->div_f_width) / sc->divider;  in periph_recalc()
642 	if (!(sc->flags & DCF_HAVE_DIV)) {  in periph_set_freq()
647 	tmp = fin << sc->div_f_width;  in periph_set_freq()
652 	if (divider < (1 << sc->div_f_width))  in periph_set_freq()
653 		 divider = 1 << (sc->div_f_width - 1);  in periph_set_freq()
661 		MD4(sc, sc->base_reg, sc->div_mask,  in periph_set_freq()
662 		    (divider - (1 << sc->div_f_width)));  in periph_set_freq()
664 		sc->divider = divider;  in periph_set_freq()
677 	clk = clknode_create(clkdom, &tegra124_periph_class, &clkdef->clkdef);  in periph_register()
682 	sc->clkdev = clknode_get_device(clk);  in periph_register()
683 	sc->base_reg = clkdef->base_reg;  in periph_register()
684 	sc->div_width = clkdef->div_width;  in periph_register()
685 	sc->div_mask = (1 <<clkdef->div_width) - 1;  in periph_register()
686 	sc->div_f_width = clkdef->div_f_width;  in periph_register()
687 	sc->div_f_mask = (1 <<clkdef->div_f_width) - 1;  in periph_register()
688 	sc->flags = clkdef->flags;  in periph_register()
694 /* -------------------------------------------------------------------------- */
740 	mask = 1 << (sc->idx % 32);  in pgate_init()
743 	RD4(sc, get_enable_reg(sc->idx), &ena_reg);  in pgate_init()
744 	RD4(sc, get_reset_reg(sc->idx), &rst_reg);  in pgate_init()
747 	sc->enabled = ena_reg & mask ? 1 : 0;  in pgate_init()
760 	mask = 1 << (sc->idx % 32);  in pgate_set_gate()
761 	sc->enabled = enable;  in pgate_set_gate()
762 	base_reg = get_enable_reg(sc->idx);  in pgate_set_gate()
780 	mask = 1 << (sc->idx % 32);  in pgate_get_gate()
781 	base_reg = get_enable_reg(sc->idx);  in pgate_get_gate()
798 	CLKDEV_DEVICE_LOCK(sc->dev);  in tegra124_hwreset_by_idx()
799 	CLKDEV_MODIFY_4(sc->dev, reset_reg, mask, reset ? mask : 0);  in tegra124_hwreset_by_idx()
800 	CLKDEV_READ_4(sc->dev, reset_reg, &reg);  in tegra124_hwreset_by_idx()
801 	CLKDEV_DEVICE_UNLOCK(sc->dev);  in tegra124_hwreset_by_idx()
812 	clk = clknode_create(clkdom, &tegra124_pgate_class, &clkdef->clkdef);  in pgate_register()
817 	sc->clkdev = clknode_get_device(clk);  in pgate_register()
818 	sc->idx = clkdef->idx;  in pgate_register()
819 	sc->flags = clkdef->flags;  in pgate_register()
831 		rv = periph_register(sc->clkdom, &periph_def[i]);  in tegra124_periph_clock()
836 		rv = pgate_register(sc->clkdom, &pgate_def[i]);  in tegra124_periph_clock()