Lines Matching +full:0 +full:x6800
40 #define IRQ_CAUSE_ERROR 0x0
41 #define IRQ_CAUSE 0x4
42 #define IRQ_CAUSE_HI 0x8
43 #define IRQ_MASK_ERROR 0xC
44 #define IRQ_MASK 0x10
45 #define IRQ_MASK_HI 0x14
46 #define IRQ_CAUSE_SELECT 0x18
47 #define FIQ_MASK_ERROR 0x1C
48 #define FIQ_MASK 0x20
49 #define FIQ_MASK_HI 0x24
50 #define FIQ_CAUSE_SELECT 0x28
51 #define ENDPOINT_IRQ_MASK_ERROR(n) 0x2C
52 #define ENDPOINT_IRQ_MASK(n) 0x30
53 #define ENDPOINT_IRQ_MASK_HI(n) 0x34
54 #define ENDPOINT_IRQ_CAUSE_SELECT 0x38
56 #define IRQ_CAUSE 0x0
57 #define IRQ_MASK 0x4
58 #define FIQ_MASK 0x8
59 #define ENDPOINT_IRQ_MASK(n) 0xC
60 #define IRQ_CAUSE_HI 0x10
61 #define IRQ_MASK_HI 0x14
62 #define FIQ_MASK_HI 0x18
63 #define ENDPOINT_IRQ_MASK_HI(n) 0x1C
76 #define IRQ_CPU_SELF 0x00000001
77 #define BRIDGE_IRQ_CAUSE_ARMADAXP 0x68
78 #define IRQ_TIMER0_ARMADAXP 0x00000001
79 #define IRQ_TIMER1_ARMADAXP 0x00000002
80 #define IRQ_TIMER_WD_ARMADAXP 0x00000004
82 #define BRIDGE_IRQ_CAUSE 0x10
83 #define IRQ_CPU_SELF 0x00000001
84 #define IRQ_TIMER0 0x00000002
85 #define IRQ_TIMER1 0x00000004
86 #define IRQ_TIMER_WD 0x00000008
88 #define BRIDGE_IRQ_MASK 0x14
89 #define IRQ_CPU_MASK 0x00000001
90 #define IRQ_TIMER0_MASK 0x00000002
91 #define IRQ_TIMER1_MASK 0x00000004
92 #define IRQ_TIMER_WD_MASK 0x00000008
104 #define RSTOUTn_MASK_ARMV7 0x60
105 #define SYSTEM_SOFT_RESET_ARMV7 0x64
106 #define SOFT_RST_OUT_EN_ARMV7 0x00000001
107 #define SYS_SOFT_RST_ARMV7 0x00000001
109 #define RSTOUTn_MASK 0x8
110 #define SOFT_RST_OUT_EN 0x00000004
111 #define SYSTEM_SOFT_RESET 0xc
112 #define SYS_SOFT_RST 0x00000001
113 #define RSTOUTn_MASK_WD 0x400
114 #define WD_RSTOUTn_MASK 0x4
115 #define WD_GLOBAL_MASK 0x00000100
116 #define WD_CPU0_MASK 0x00000001
117 #define WD_RST_OUT_EN 0x00000002
123 #define CPU_PM_CTRL 0x18
125 #define CPU_PM_CTRL 0x1C
127 #define CPU_PM_CTRL_NONE 0
128 #define CPU_PM_CTRL_ALL ~0x0
131 #define CPU_PM_CTRL_GE0 (1 << 0)
191 #define CPU_TIMERS_BASE 0x300
192 #define CPU_TIMER_CONTROL 0x0
193 #define CPU_TIMER0_EN 0x00000001
194 #define CPU_TIMER0_AUTO 0x00000002
195 #define CPU_TIMER1_EN 0x00000004
196 #define CPU_TIMER1_AUTO 0x00000008
197 #define CPU_TIMER2_EN 0x00000010
198 #define CPU_TIMER2_AUTO 0x00000020
199 #define CPU_TIMER_WD_EN 0x00000100
200 #define CPU_TIMER_WD_AUTO 0x00000200
202 #define CPU_TIMER_WD_25MHZ_EN 0x00000400
203 #define CPU_TIMER0_25MHZ_EN 0x00000800
204 #define CPU_TIMER1_25MHZ_EN 0x00001000
205 #define CPU_TIMER0_REL 0x10
206 #define CPU_TIMER0 0x14
213 #define EDMA_REGISTERS_OFFSET 0x2000
214 #define EDMA_REGISTERS_SIZE 0x2000
219 #define SATA_CR 0x000 /* Configuration Reg. */
226 #define SATA_ICTR 0x00C
230 #define SATA_ITTR 0x010
233 #define SATA_ICR 0x014 /* Interrupt Cause Reg. */
238 #define SATA_MICR 0x020 /* Main Interrupt Cause Reg. */
244 #define SATA_MIMR 0x024 /* Main Interrupt Mask Reg. */
247 #define SATA_SHADOWR_BASE(ch) (SATA_EDMA_BASE(ch) + 0x100)
248 #define SATA_SHADOWR_CONTROL(ch) (SATA_EDMA_BASE(ch) + 0x120)
251 #define SATA_SATA_SSTATUS(ch) (SATA_EDMA_BASE(ch) + 0x300)
252 #define SATA_SATA_SERROR(ch) (SATA_EDMA_BASE(ch) + 0x304)
253 #define SATA_SATA_SCONTROL(ch) (SATA_EDMA_BASE(ch) + 0x308)
254 #define SATA_SATA_FISICR(ch) (SATA_EDMA_BASE(ch) + 0x364)
257 #define SATA_EDMA_CFG(ch) (SATA_EDMA_BASE(ch) + 0x000)
261 #define SATA_EDMA_IECR(ch) (SATA_EDMA_BASE(ch) + 0x008)
263 #define SATA_EDMA_IEMR(ch) (SATA_EDMA_BASE(ch) + 0x00C)
264 #define SATA_EDMA_REQBAHR(ch) (SATA_EDMA_BASE(ch) + 0x010)
265 #define SATA_EDMA_REQIPR(ch) (SATA_EDMA_BASE(ch) + 0x014)
266 #define SATA_EDMA_REQOPR(ch) (SATA_EDMA_BASE(ch) + 0x018)
267 #define SATA_EDMA_RESBAHR(ch) (SATA_EDMA_BASE(ch) + 0x01C)
268 #define SATA_EDMA_RESIPR(ch) (SATA_EDMA_BASE(ch) + 0x020)
269 #define SATA_EDMA_RESOPR(ch) (SATA_EDMA_BASE(ch) + 0x024)
271 #define SATA_EDMA_CMD(ch) (SATA_EDMA_BASE(ch) + 0x028)
272 #define SATA_EDMA_CMD_ENABLE (1 << 0)
276 #define SATA_EDMA_STATUS(ch) (SATA_EDMA_BASE(ch) + 0x030)
288 #define GPIO_DATA_OUT 0x00
289 #define GPIO_DATA_OUT_EN_CTRL 0x04
290 #define GPIO_BLINK_EN 0x08
291 #define GPIO_DATA_IN_POLAR 0x0c
292 #define GPIO_DATA_IN 0x10
293 #define GPIO_INT_CAUSE 0x14
294 #define GPIO_INT_EDGE_MASK 0x18
295 #define GPIO_INT_LEV_MASK 0x1c
300 #define MV_GPIO_IN_NONE 0x0
306 #define MV_GPIO_OUT_NONE 0x0
307 #define MV_GPIO_OUT_BLINK 0x1
308 #define MV_GPIO_OUT_OPEN_DRAIN 0x2
309 #define MV_GPIO_OUT_OPEN_SRC 0x4
312 #define SAMPLE_AT_RESET 0x10
314 #define SAMPLE_AT_RESET 0x30
316 #define SAMPLE_AT_RESET_ARMADA38X 0x400
317 #define SAMPLE_AT_RESET_LO 0x30
318 #define SAMPLE_AT_RESET_HI 0x34
324 #define TCLK_MASK 0x00000300
325 #define TCLK_SHIFT 0x08
327 #define TCLK_MASK 0x00000180
328 #define TCLK_SHIFT 0x07
331 #define TCLK_MASK_ARMADA38X 0x00008000
344 #define A38X_CPU_DDR_CLK_MASK 0x00007c00
351 #define CPU_CONFIG 0x00000000
352 #define CPU_CONFIG_IC_PREF 0x00010000
353 #define CPU_CONFIG_DC_PREF 0x00020000
354 #define CPU_CONTROL 0x00000004
355 #define CPU_CONTROL_L2_SIZE 0x00200000 /* Only on Discovery */
356 #define CPU_CONTROL_L2_MODE 0x00020000 /* Only on Discovery */
357 #define CPU_L2_CONFIG 0x00000028 /* Only on Kirkwood */
358 #define CPU_L2_CONFIG_MODE 0x00000010 /* Only on Kirkwood */
368 #define PCI_VENDORID_MRVL 0x11AB
369 #define PCI_VENDORID_MRVL2 0x1B4B
374 #define MV_DEV_88F5181 0x5181
375 #define MV_DEV_88F5182 0x5182
376 #define MV_DEV_88F5281 0x5281
377 #define MV_DEV_88F6281 0x6281
378 #define MV_DEV_88F6282 0x6282
379 #define MV_DEV_88F6781 0x6781
380 #define MV_DEV_88F6828 0x6828
381 #define MV_DEV_88F6820 0x6820
382 #define MV_DEV_88F6810 0x6810
383 #define MV_DEV_MV78100_Z0 0x6381
384 #define MV_DEV_MV78100 0x7810
385 #define MV_DEV_MV78130 0x7813
386 #define MV_DEV_MV78160 0x7816
387 #define MV_DEV_MV78230 0x7823
388 #define MV_DEV_MV78260 0x7826
389 #define MV_DEV_MV78460 0x7846
390 #define MV_DEV_88RC8180 0x8180
391 #define MV_DEV_88RC9480 0x9480
392 #define MV_DEV_88RC9580 0x9580
394 #define MV_DEV_FAMILY_MASK 0xff00
395 #define MV_DEV_DISCOVERY 0x7800
396 #define MV_DEV_ARMADA38X 0x6800
401 #define MV_DRBL_PCIE_TO_CPU 0
404 #define MV_DRBL_CAUSE(d,u) (0x10 * (u) + 0x8 * (d))
405 #define MV_DRBL_MASK(d,u) (0x10 * (u) + 0x8 * (d) + 0x4)
406 #define MV_DRBL_MSG(m,d,u) (0x10 * (u) + 0x8 * (d) + 0x4 * (m) + 0x30)
411 #define MV_SCU_BASE (MV_BASE + 0xc000)
412 #define MV_SCU_REGS_LEN 0x100
413 #define MV_SCU_REG_CTRL 0x00
414 #define MV_SCU_REG_CONFIG 0x04
415 #define MV_SCU_ENABLE (1 << 0)
417 #define SCU_CFG_REG_NCPU_MASK 0x3
422 #define MV_PMSU_BASE (MV_BASE + 0x22000)
423 #define MV_PMSU_REGS_LEN 0x1000
424 #define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) (((cpu) * 0x100) + 0x124)
429 #define MV_CPU_RESET_BASE (MV_BASE + 0x20800)
430 #define MV_CPU_RESET_REGS_LEN 0x8
431 #define CPU_RESET_OFFSET(cpu) ((cpu) * 0x8)
432 #define CPU_RESET_ASSERT 0x1
434 #define MV_MBUS_CTRL_BASE (MV_BASE + 0x20420)
435 #define MV_MBUS_CTRL_REGS_LEN 0x10