Lines Matching full:c1

44 #define	CP14_DBGDSCRext_V6(rr)	p14, 0, rr, c0, c1, 0 /* Debug Status and Ctrl Register v6 */
47 #define	CP14_DBGOSLAR(rr)	p14, 0, rr, c1, c0, 4 /* OS Lock Access Register */
48 #define	CP14_DBGOSLSR(rr)	p14, 0, rr, c1, c1, 4 /* OS Lock Status Register */
49 #define	CP14_DBGOSDLR(rr)	p14, 0, rr, c1, c3, 4 /* OS Double Lock Register */
50 #define	CP14_DBGPRSR(rr)	p14, 0, rr, c1, c5, 4 /* Device Powerdown and Reset Status */
64 #define	CP15_ID_PFR0(rr)	p15, 0, rr, c0, c1,  0 /* Processor Feature Register 0 */
65 #define	CP15_ID_PFR1(rr)	p15, 0, rr, c0, c1,  1 /* Processor Feature Register 1 */
66 #define	CP15_ID_DFR0(rr)	p15, 0, rr, c0, c1,  2 /* Debug Feature Register 0 */
67 #define	CP15_ID_AFR0(rr)	p15, 0, rr, c0, c1,  3 /* Auxiliary Feature Register  0 */
68 #define	CP15_ID_MMFR0(rr)	p15, 0, rr, c0, c1,  4 /* Memory Model Feature Register 0 */
69 #define	CP15_ID_MMFR1(rr)	p15, 0, rr, c0, c1,  5 /* Memory Model Feature Register 1 */
70 #define	CP15_ID_MMFR2(rr)	p15, 0, rr, c0, c1,  6 /* Memory Model Feature Register 2 */
71 #define	CP15_ID_MMFR3(rr)	p15, 0, rr, c0, c1,  7 /* Memory Model Feature Register 3 */
90  * CP15 C1 registers
92 #define	CP15_SCTLR(rr)		p15, 0, rr, c1, c0,  0 /* System Control Register */
93 #define	CP15_ACTLR(rr)		p15, 0, rr, c1, c0,  1 /* IMPLEMENTATION DEFINED Auxiliary Control Register…
94 #define	CP15_CPACR(rr)		p15, 0, rr, c1, c0,  2 /* Coprocessor Access Control Register */
96 #define	CP15_SCR(rr)		p15, 0, rr, c1, c1,  0 /* Secure Configuration Register */
97 #define	CP15_SDER(rr)		p15, 0, rr, c1, c1,  1 /* Secure Debug Enable Register */
98 #define	CP15_NSACR(rr)		p15, 0, rr, c1, c1,  2 /* Non-Secure Access Control Register */
100 #define	CP15_HSCTLR(rr)		p15, 4, rr, c1, c0,  0 /* Hyp System Control Register */
102 #define	CP15_HCR(rr)		p15, 4, rr, c1, c1,  0 /* Hyp Configuration Register */
103 #define	CP15_HDCR(rr)		p15, 4, rr, c1, c1,  1 /* Hyp Debug Configuration Register */
104 #define	CP15_HCPTR(rr)		p15, 4, rr, c1, c1,  2 /* Hyp Coprocessor Trap Register */
105 #define	CP15_HSTR(rr)		p15, 4, rr, c1, c1,  3 /* Hyp System Trap Register */
115 #define	CP15_VTCR(rr)		p15, 4, rr, c2, c1,  2 /* Virtualization Translation Control Register */
131 #define	CP15_ADFSR(rr)		p15, 0, rr, c5, c1,  0 /* Auxiliary Data Fault Status Register */
132 #define	CP15_AIFSR(rr)		p15, 0, rr, c5, c1,  1 /* Auxiliary Instruction Fault Status Register */
150 #define	CP15_ICIALLUIS		p15, 0, r0, c7, c1,  0 /* Instruction cache invalidate all PoU, IS */
151 #define	CP15_BPIALLIS		p15, 0, r0, c7, c1,  6 /* Branch predictor invalidate all IS */
243 #define	CP15_ISR(rr)		p15, 0, rr, c12, c1, 0 /* Interrupt Status Register */
262 #define	CP15_CNTKCTL(rr)	p15, 0, rr, c14, c1, 0 /* Timer PL1 Control Register */
267 #define	CP15_CNTHCTL(rr)	p15, 4, rr, c14, c1, 0 /* Timer PL2 Control Register */