Lines Matching full:denoting
156 .IP "bit #4 denoting presence of Time-Stamp Counter." 4
157 .IX Item "bit #4 denoting presence of Time-Stamp Counter."
159 .IP "bit #19 denoting availability of \s-1CLFLUSH\s0 instruction;" 4
160 .IX Item "bit #19 denoting availability of CLFLUSH instruction;"
163 .IP "bit #23 denoting \s-1MMX\s0 support;" 4
164 .IX Item "bit #23 denoting MMX support;"
165 .IP "bit #24, \s-1FXSR\s0 bit, denoting availability of \s-1XMM\s0 registers;" 4
166 .IX Item "bit #24, FXSR bit, denoting availability of XMM registers;"
167 .IP "bit #25 denoting \s-1SSE\s0 support;" 4
168 .IX Item "bit #25 denoting SSE support;"
169 .IP "bit #26 denoting \s-1SSE2\s0 support;" 4
170 .IX Item "bit #26 denoting SSE2 support;"
171 .IP "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;" 4
172 .IX Item "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;"
175 .IP "bit #33 denoting availability of \s-1PCLMULQDQ\s0 instruction;" 4
176 .IX Item "bit #33 denoting availability of PCLMULQDQ instruction;"
177 .IP "bit #41 denoting \s-1SSSE3,\s0 Supplemental \s-1SSE3,\s0 support;" 4
178 .IX Item "bit #41 denoting SSSE3, Supplemental SSE3, support;"
179 .IP "bit #43 denoting \s-1AMD XOP\s0 support (forced to zero on non-AMD CPUs);" 4
180 .IX Item "bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);"
181 .IP "bit #54 denoting availability of \s-1MOVBE\s0 instruction;" 4
182 .IX Item "bit #54 denoting availability of MOVBE instruction;"
183 .IP "bit #57 denoting AES-NI instruction set extension;" 4
184 .IX Item "bit #57 denoting AES-NI instruction set extension;"
187 .IP "bit #59, \s-1OSXSAVE\s0 bit, denoting availability of \s-1YMM\s0 registers;" 4
188 .IX Item "bit #59, OSXSAVE bit, denoting availability of YMM registers;"
189 .IP "bit #60 denoting \s-1AVX\s0 extension;" 4
190 .IX Item "bit #60 denoting AVX extension;"
191 .IP "bit #62 denoting availability of \s-1RDRAND\s0 instruction;" 4
192 .IX Item "bit #62 denoting availability of RDRAND instruction;"
219 .IP "bit #64+3 denoting availability of \s-1BMI1\s0 instructions, e.g. \s-1ANDN\s0;" 4
220 .IX Item "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;"
222 .IP "bit #64+5 denoting availability of \s-1AVX2\s0 instructions;" 4
223 .IX Item "bit #64+5 denoting availability of AVX2 instructions;"
224 .IP "bit #64+8 denoting availability of \s-1BMI2\s0 instructions, e.g. \s-1MULX\s0 and \s-1RORX\s0;…
225 .IX Item "bit #64+8 denoting availability of BMI2 instructions, e.g. MULX and RORX;"
226 .IP "bit #64+16 denoting availability of \s-1AVX512F\s0 extension;" 4
227 .IX Item "bit #64+16 denoting availability of AVX512F extension;"
228 .IP "bit #64+17 denoting availability of \s-1AVX512DQ\s0 extension;" 4
229 .IX Item "bit #64+17 denoting availability of AVX512DQ extension;"
230 .IP "bit #64+18 denoting availability of \s-1RDSEED\s0 instruction;" 4
231 .IX Item "bit #64+18 denoting availability of RDSEED instruction;"
232 .IP "bit #64+19 denoting availability of \s-1ADCX\s0 and \s-1ADOX\s0 instructions;" 4
233 .IX Item "bit #64+19 denoting availability of ADCX and ADOX instructions;"
234 .IP "bit #64+21 denoting availability of VPMADD52[\s-1LH\s0]UQ instructions, aka \s-1AVX512IFMA\s0 …
235 .IX Item "bit #64+21 denoting availability of VPMADD52[LH]UQ instructions, aka AVX512IFMA extension…
236 .IP "bit #64+29 denoting availability of \s-1SHA\s0 extension;" 4
237 .IX Item "bit #64+29 denoting availability of SHA extension;"
238 .IP "bit #64+30 denoting availability of \s-1AVX512BW\s0 extension;" 4
239 .IX Item "bit #64+30 denoting availability of AVX512BW extension;"
240 .IP "bit #64+31 denoting availability of \s-1AVX512VL\s0 extension;" 4
241 .IX Item "bit #64+31 denoting availability of AVX512VL extension;"
242 .IP "bit #64+41 denoting availability of \s-1VAES\s0 extension;" 4
243 .IX Item "bit #64+41 denoting availability of VAES extension;"
244 .IP "bit #64+42 denoting availability of \s-1VPCLMULQDQ\s0 extension;" 4
245 .IX Item "bit #64+42 denoting availability of VPCLMULQDQ extension;"